Enum CInstruction

pub enum CInstruction {
    ADDI4SPN {
        dest: CIRegister,
        imm: CWideImmediate,
    },
    FLD {
        dest: CFRegister,
        base: CIRegister,
        offset: CDImmediate,
    },
    LW {
        dest: CIRegister,
        base: CIRegister,
        offset: CWImmediate,
    },
    LD {
        dest: CIRegister,
        base: CIRegister,
        offset: CDImmediate,
    },
    FSD {
        src: CFRegister,
        base: CIRegister,
        offset: CDImmediate,
    },
    SW {
        src: CIRegister,
        base: CIRegister,
        offset: CWImmediate,
    },
    SD {
        src: CIRegister,
        base: CIRegister,
        offset: CDImmediate,
    },
    ADDI {
        dest: IRegister,
        imm: CIImmediate,
    },
    ADDIW {
        dest: IRegister,
        imm: CIImmediate,
    },
    LI {
        dest: IRegister,
        imm: CIImmediate,
    },
    ADDI16SP {
        imm: C16SPImmediate,
    },
    LUI {
        dest: IRegister,
        imm: CIImmediate,
    },
    SRLI {
        dest: CIRegister,
        shamt: CShamt,
    },
    SRAI {
        dest: CIRegister,
        shamt: CShamt,
    },
    ANDI {
        dest: CIRegister,
        imm: CIImmediate,
    },
    SUB {
        dest: CIRegister,
        src: CIRegister,
    },
    XOR {
        dest: CIRegister,
        src: CIRegister,
    },
    OR {
        dest: CIRegister,
        src: CIRegister,
    },
    AND {
        dest: CIRegister,
        src: CIRegister,
    },
    SUBW {
        dest: CIRegister,
        src: CIRegister,
    },
    ADDW {
        dest: CIRegister,
        src: CIRegister,
    },
    J {
        offset: CJImmediate,
    },
    BEQZ {
        src: CIRegister,
        offset: CBImmediate,
    },
    BNEZ {
        src: CIRegister,
        offset: CBImmediate,
    },
    SLLI {
        dest: IRegister,
        shamt: CShamt,
    },
    FLDSP {
        dest: FRegister,
        offset: CDSPImmediate,
    },
    LWSP {
        dest: IRegister,
        offset: CWSPImmediate,
    },
    LDSP {
        dest: IRegister,
        offset: CDSPImmediate,
    },
    JR {
        src: IRegister,
    },
    MV {
        dest: IRegister,
        src: IRegister,
    },
    EBREAK,
    JALR {
        src: IRegister,
    },
    ADD {
        dest: IRegister,
        src: IRegister,
    },
    FSDSP {
        src: FRegister,
        offset: CSDSPImmediate,
    },
    SWSP {
        src: IRegister,
        offset: CSWSPImmediate,
    },
    SDSP {
        src: IRegister,
        offset: CSDSPImmediate,
    },
}

Variants

ADDI4SPN

Fields

dest: CIRegister

imm: CWideImmediate

FLD

Fields

dest: CFRegister

base: CIRegister

offset: CDImmediate

LW

Fields

dest: CIRegister

base: CIRegister

offset: CWImmediate

LD

Fields

dest: CIRegister

base: CIRegister

offset: CDImmediate

FSD

Fields

src: CFRegister

base: CIRegister

offset: CDImmediate

SW

Fields

src: CIRegister

base: CIRegister

offset: CWImmediate

SD

Fields

src: CIRegister

base: CIRegister

offset: CDImmediate

ADDI

Fields

dest: IRegister

imm: CIImmediate

ADDIW

Fields

dest: IRegister

imm: CIImmediate

LI

Fields

dest: IRegister

imm: CIImmediate

ADDI16SP

Fields

imm: C16SPImmediate

LUI

Fields

dest: IRegister

imm: CIImmediate

SRLI

Fields

dest: CIRegister

shamt: CShamt

SRAI

Fields

dest: CIRegister

shamt: CShamt

ANDI

Fields

dest: CIRegister

imm: CIImmediate

SUB

Fields

dest: CIRegister

src: CIRegister

XOR

Fields

dest: CIRegister

src: CIRegister

OR

Fields

dest: CIRegister

src: CIRegister

AND

Fields

dest: CIRegister

src: CIRegister

SUBW

Fields

dest: CIRegister

src: CIRegister

ADDW

Fields

dest: CIRegister

src: CIRegister

J

Fields

offset: CJImmediate

BEQZ

Fields

src: CIRegister

offset: CBImmediate

BNEZ

Fields

src: CIRegister

offset: CBImmediate

SLLI

Fields

dest: IRegister

shamt: CShamt

FLDSP

Fields

dest: FRegister

offset: CDSPImmediate

LWSP

Fields

dest: IRegister

offset: CWSPImmediate

LDSP

Fields

dest: IRegister

offset: CDSPImmediate

JR

Fields

src: IRegister

MV

Fields

dest: IRegister

src: IRegister

EBREAK

JALR

Fields

src: IRegister

ADD

Fields

dest: IRegister

src: IRegister

FSDSP

Fields

src: FRegister

offset: CSDSPImmediate

SWSP

Fields

src: IRegister

offset: CSWSPImmediate

SDSP

Fields

src: IRegister

offset: CSDSPImmediate

Implementations

impl CInstruction

pub fn decode(instruction: u16) -> Result<Self, String>

Decodes a u16 into a CInstruction.

pub fn disassemble(instruction: &CInstruction) -> String

pub fn expand(&self) -> Instruction

Converts a compressed instruction into the corresponding 32-bit Instruction.

Note that C.JALR does not have exactly the same effect as the corresponding JALR as described in the manual:

Strictly speaking, C.JALR does not expand exactly to a base RVI instruction as the value added to the PC to form the link address is 2 rather than 4 as in the base ISA, but supporting both offsets of 2 and 4 bytes is only a very minor change to the base microarchitecture.

pub fn encode(instruction: &CInstruction) -> u16

Encodes a CInstruction into a u16.

Trait Implementations

impl Debug for CInstruction

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for CInstruction

fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter.

impl PartialEq for CInstruction

fn eq(&self, other: &CInstruction) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl StructuralPartialEq for CInstruction