riscv_codec::instruction

Enum Instruction

Source 
pub enum Instruction {

Show 124 variants    LUI {
        dest: IRegister,
        imm: UImmediate,
    },
    AUIPC {
        dest: IRegister,
        imm: UImmediate,
    },
    JAL {
        dest: IRegister,
        offset: JImmediate,
    },
    JALR {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    BEQ {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    BNE {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    BLT {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    BGE {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    BLTU {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    BGEU {
        src1: IRegister,
        src2: IRegister,
        offset: BImmediate,
    },
    LB {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    LH {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    LW {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    LBU {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    LHU {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    SB {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    SH {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    SW {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    ADDI {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    SLTI {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    SLTIU {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    XORI {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    ORI {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    ANDI {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    SLLI {
        dest: IRegister,
        src: IRegister,
        shamt: Shamt,
    },
    SRLI {
        dest: IRegister,
        src: IRegister,
        shamt: Shamt,
    },
    SRAI {
        dest: IRegister,
        src: IRegister,
        shamt: Shamt,
    },
    ADD {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SUB {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SLL {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SLT {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SLTU {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    XOR {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SRL {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SRA {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    OR {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    AND {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    FENCE {
        rd: IRegister,
        rs1: IRegister,
        ops: u8,
        fm: u8,
    },
    ECALL,
    EBREAK,
    LWU {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    LD {
        dest: IRegister,
        base: IRegister,
        offset: IImmediate,
    },
    SD {
        src: IRegister,
        base: IRegister,
        offset: SImmediate,
    },
    ADDIW {
        dest: IRegister,
        src: IRegister,
        imm: IImmediate,
    },
    SLLIW {
        dest: IRegister,
        src: IRegister,
        shamt: ShamtW,
    },
    SRLIW {
        dest: IRegister,
        src: IRegister,
        shamt: ShamtW,
    },
    SRAIW {
        dest: IRegister,
        src: IRegister,
        shamt: ShamtW,
    },
    ADDW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SUBW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SLLW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SRLW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    SRAW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    MUL {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    MULH {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    MULHSU {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    MULHU {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    DIV {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    DIVU {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    REM {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    REMU {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    MULW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    DIVW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    DIVUW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    REMW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    REMUW {
        dest: IRegister,
        src1: IRegister,
        src2: IRegister,
    },
    LRW {
        dest: IRegister,
        addr: IRegister,
        aq: bool,
        rl: bool,
    },
    SCW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOSWAPW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOADDW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOXORW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOANDW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOORW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMINW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMAXW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMINUW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMAXUW {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    LRD {
        dest: IRegister,
        addr: IRegister,
        aq: bool,
        rl: bool,
    },
    SCD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOSWAPD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOADDD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOXORD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOANDD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOORD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMIND {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMAXD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMINUD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    AMOMAXUD {
        dest: IRegister,
        addr: IRegister,
        src: IRegister,
        aq: bool,
        rl: bool,
    },
    FLW {
        dest: FRegister,
        base: IRegister,
        offset: IImmediate,
    },
    FSW {
        base: IRegister,
        src: FRegister,
        offset: SImmediate,
    },
    FMADDS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FMSUBS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FNMSUBS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FNMADDS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        src3: FRegister,
        rm: RoundingMode,
    },
    FADDS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FSUBS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FMULS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FDIVS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
        rm: RoundingMode,
    },
    FSQRTS {
        dest: FRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FSGNJS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FSGNJNS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FSGNJXS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FMINS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FMAXS {
        dest: FRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FCVTWS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FCVTWUS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FMVXW {
        dest: IRegister,
        src: FRegister,
    },
    FEQS {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FLTS {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FLES {
        dest: IRegister,
        src1: FRegister,
        src2: FRegister,
    },
    FCLASSS {
        dest: IRegister,
        src: FRegister,
    },
    FCVTSW {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FCVTSWU {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FMVWX {
        dest: FRegister,
        src: IRegister,
    },
    FCVTLS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FCVTLUS {
        dest: IRegister,
        src: FRegister,
        rm: RoundingMode,
    },
    FCVTSL {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    FCVTSLU {
        dest: FRegister,
        src: IRegister,
        rm: RoundingMode,
    },
    CSRRW {
        dest: IRegister,
        src: IRegister,
        csr: CSR,
    },
    CSRRS {
        dest: IRegister,
        src: IRegister,
        csr: CSR,
    },
    CSRRC {
        dest: IRegister,
        src: IRegister,
        csr: CSR,
    },
    CSRRWI {
        dest: IRegister,
        imm: CSRImmediate,
        csr: CSR,
    },
    CSRRSI {
        dest: IRegister,
        imm: CSRImmediate,
        csr: CSR,
    },
    CSRRCI {
        dest: IRegister,
        imm: CSRImmediate,
        csr: CSR,
    },
    FENCEI,

}

Variants§

§

LUI

Load upper immediate

Fields

§dest: IRegister
§imm: UImmediate
§

AUIPC

Add upper immediate to PC

Fields

§dest: IRegister
§imm: UImmediate
§

JAL

Jump and Link

Fields

§dest: IRegister
§offset: JImmediate
§

JALR

Jump and Link Register

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

BEQ

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

BNE

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

BLT

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

BGE

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

BLTU

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

BGEU

Fields

§src1: IRegister
§src2: IRegister
§offset: BImmediate
§

LB

Load Byte

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

LH

Load Halfword

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

LW

Load Word

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

LBU

Load Byte Unsigned

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

LHU

Load Halfword Unsigned

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

SB

Store Byte

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

SH

Store Halfword

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

SW

Store Word

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

ADDI

§

SLTI

§

SLTIU

§

XORI

§

ORI

§

ANDI

§

SLLI

Left Shift Immediate

Fields

§dest: IRegister
§src: IRegister
§shamt: Shamt
§

SRLI

Logical Right Shift Immediate

Fields

§dest: IRegister
§src: IRegister
§shamt: Shamt
§

SRAI

Arithmetic Right Shift Immediate

Fields

§dest: IRegister
§src: IRegister
§shamt: Shamt
§

ADD

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SUB

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SLL

Left Shift

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SLT

Branch if Equal

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SLTU

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

XOR

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SRL

Logical Right Shift Immediate

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SRA

Arithmetic Right Shift Immediate

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

OR

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

AND

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

FENCE

Fields

§rd: IRegister
§rs1: IRegister
§ops: u8
§fm: u8
§

ECALL

§

EBREAK

§

LWU

Load Word Unsigned

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

LD

Load Doubleword

Fields

§dest: IRegister
§base: IRegister
§offset: IImmediate
§

SD

Store Doubleword

Fields

§src: IRegister
§base: IRegister
§offset: SImmediate
§

ADDIW

Add Immediate (word)

§

SLLIW

Left Shift Immediate (word)

Fields

§dest: IRegister
§src: IRegister
§shamt: ShamtW
§

SRLIW

Logical Right Shift Immediate (word)

Fields

§dest: IRegister
§src: IRegister
§shamt: ShamtW
§

SRAIW

Arithmetic Right Shift Immediate (word)

Fields

§dest: IRegister
§src: IRegister
§shamt: ShamtW
§

ADDW

Add (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SUBW

Subtract (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SLLW

Left Shift (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SRLW

Logical Right Shift (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

SRAW

Arithmetic Right Shift (word)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

MUL

Multiply

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

MULH

Multiply (High bits)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

MULHSU

Multiply Signed-Unsigned (High bits)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

MULHU

Multiply Unsigned (High)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

DIV

Divide

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

DIVU

Divide (Unsigned)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

REM

Remainder

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

REMU

Remainder (Unsigned)

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

MULW

Multiply Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

DIVW

Divide Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

DIVUW

Divide Unsigned Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

REMW

Remainder Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

REMUW

Remainder Unsigned Word

Fields

§dest: IRegister
§src1: IRegister
§src2: IRegister
§

LRW

Load Reserved Word

Fields

§dest: IRegister
§addr: IRegister
§aq: bool
§rl: bool
§

SCW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOSWAPW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOADDW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOXORW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOANDW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOORW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMINW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMAXW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMINUW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMAXUW

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

LRD

Fields

§dest: IRegister
§addr: IRegister
§aq: bool
§rl: bool
§

SCD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOSWAPD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOADDD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOXORD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOANDD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOORD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMIND

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMAXD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMINUD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

AMOMAXUD

Fields

§dest: IRegister
§addr: IRegister
§src: IRegister
§aq: bool
§rl: bool
§

FLW

Fields

§dest: FRegister
§base: IRegister
§offset: IImmediate
§

FSW

Fields

§base: IRegister
§src: FRegister
§offset: SImmediate
§

FMADDS

§

FMSUBS

§

FNMSUBS

§

FNMADDS

§

FADDS

§

FSUBS

§

FMULS

§

FDIVS

§

FSQRTS

§

FSGNJS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FSGNJNS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FSGNJXS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FMINS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FMAXS

Fields

§dest: FRegister
§src1: FRegister
§src2: FRegister
§

FCVTWS

§

FCVTWUS

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FMVXW

Fields

§dest: IRegister
§src: FRegister
§

FEQS

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FLTS

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FLES

Fields

§dest: IRegister
§src1: FRegister
§src2: FRegister
§

FCLASSS

Fields

§dest: IRegister
§src: FRegister
§

FCVTSW

§

FCVTSWU

§

FMVWX

Fields

§dest: FRegister
§src: IRegister
§

FCVTLS

§

FCVTLUS

§

FCVTSL

§

FCVTSLU

§

CSRRW

Fields

§dest: IRegister
§src: IRegister
§csr: CSR
§

CSRRS

Fields

§dest: IRegister
§src: IRegister
§csr: CSR
§

CSRRC

Fields

§dest: IRegister
§src: IRegister
§csr: CSR
§

CSRRWI

Fields

§dest: IRegister
§imm: CSRImmediate
§csr: CSR
§

CSRRSI

Fields

§dest: IRegister
§imm: CSRImmediate
§csr: CSR
§

CSRRCI

Fields

§dest: IRegister
§imm: CSRImmediate
§csr: CSR
§

FENCEI

Implementations§

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impl Instruction

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pub fn decode(instruction: u32) -> Result<Instruction, String>

Constructs an Instruction from it’s machine code representation.

Examples found in repository?
examples/simple.rs (line 9)
2fn main() {
3    // instruction can be assembled from strings
4    let instr: Instruction = assemble_line("addi t0, t1, 1024").unwrap().i();
5    // and disassembled
6    println!("assembled instruction: {}", instr);
7
8    // instructions can also be decoded from binary
9    let instr2 = Instruction::decode(0xe0058513).unwrap();
10
11    // and encoded
12    assert_eq!(Instruction::encode(&instr2), 0xe0058513);
13}
Source

pub fn encode(instruction: &Instruction) -> u32

Examples found in repository?
examples/simple.rs (line 12)
2fn main() {
3    // instruction can be assembled from strings
4    let instr: Instruction = assemble_line("addi t0, t1, 1024").unwrap().i();
5    // and disassembled
6    println!("assembled instruction: {}", instr);
7
8    // instructions can also be decoded from binary
9    let instr2 = Instruction::decode(0xe0058513).unwrap();
10
11    // and encoded
12    assert_eq!(Instruction::encode(&instr2), 0xe0058513);
13}

Trait Implementations§

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impl Debug for Instruction

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fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter. Read more
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impl Display for Instruction

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fn fmt(&self, f: &mut Formatter<'_>) -> Result<(), Error>

Formats the value using the given formatter. Read more
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impl PartialEq for Instruction

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fn eq(&self, other: &Instruction) -> bool

Tests for self and other values to be equal, and is used by ==.
1.0.0 · Source§

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.
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impl StructuralPartialEq for Instruction

Auto Trait Implementations§

Blanket Implementations§

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impl<T> Any for T
where T: 'static + ?Sized,

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fn type_id(&self) -> TypeId

Gets the TypeId of self. Read more
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impl<T> Borrow<T> for T
where T: ?Sized,

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fn borrow(&self) -> &T

Immutably borrows from an owned value. Read more
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impl<T> BorrowMut<T> for T
where T: ?Sized,

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fn borrow_mut(&mut self) -> &mut T

Mutably borrows from an owned value. Read more
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impl<T> From<T> for T

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fn from(t: T) -> T

Returns the argument unchanged.

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impl<T, U> Into<U> for T
where U: From<T>,

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fn into(self) -> U

Calls U::from(self).

That is, this conversion is whatever the implementation of From<T> for U chooses to do.

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impl<T> ToString for T
where T: Display + ?Sized,

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fn to_string(&self) -> String

Converts the given value to a String. Read more
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impl<T, U> TryFrom<U> for T
where U: Into<T>,

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type Error = Infallible

The type returned in the event of a conversion error.
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fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>

Performs the conversion.
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impl<T, U> TryInto<U> for T
where U: TryFrom<T>,

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type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.
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fn try_into(self) -> Result<U, <U as TryFrom<T>>::Error>

Performs the conversion.