Trait probe_rs::architecture::riscv::sequences::RiscvDebugSequence

pub trait RiscvDebugSequence: Send + Sync {
    fn on_connect(
        &self,
        _interface: &mut RiscvCommunicationInterface
    ) -> Result<(), Error> { ... }
}

A interface to operate debug sequences for RISC-V targets.

Should be implemented on a custom handle for chips that require special sequence code.

Provided Methods

fn on_connect(
    &self,
    _interface: &mut RiscvCommunicationInterface
) -> Result<(), Error>

Executed when the probe establishes a connection to the target.

Implementors

impl RiscvDebugSequence for ESP32C3

impl RiscvDebugSequence for DefaultRiscvSequence