Module probe_rs::architecture::riscv
source · Expand description
All the interface bits for RISC-V.
Modules
Debug Module Communication
Debug sequences to operate special requirements RISC-V targets.
Structs
Abstract Control and Status (see 3.12.6)
“data0” register.
“data1” register.
“data2” register.
“data3” register.
“data4” register.
“data5” register.
“data6” register.
“data7” register.
“data8” register.
“data9” register.
“data10” register.
“data11” register.
dmcontrol register, located at
address 0x10Readonly
dmstatus register.Hart Info (see 3.12.3)
Isa and Extensions (see RISC-V Privileged Spec, 3.1.1)
“progbuf0” register.
“progbuf1” register.
“progbuf2” register.
“progbuf3” register.
“progbuf4” register.
“progbuf5” register.
“progbuf6” register.
“progbuf7” register.
“progbuf8” register.
“progbuf9” register.
“progbuf10” register.
“progbuf11” register.
“progbuf12” register.
“progbuf13” register.
“progbuf14” register.
“progbuf15” register.
Flags used to control the
SpecificCoreState for RiscV architectureA interface to operate RISC-V cores.