Struct probe_rs::architecture::arm::armv8m::Armv8m

pub struct Armv8m<'probe> { /* private fields */ }

The state of a core that can be used to persist core state across calls to multiple different cores.

Trait Implementations

impl<'probe> CoreInterface for Armv8m<'probe>

fn hw_breakpoints(&mut self) -> Result<Vec<Option<u64>>, Error>

See docs on the CoreInterface::hw_breakpoints trait

fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>

Wait until the core is halted. If the core does not halt on its own, a DebugProbeError::Timeout error will be returned.

fn core_halted(&mut self) -> Result<bool, Error>

Check if the core is halted. If the core does not halt on its own, a DebugProbeError::Timeout error will be returned.

fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>

Try to halt the core. This function ensures the core is actually halted, and returns a DebugProbeError::Timeout otherwise.

fn run(&mut self) -> Result<(), Error>

Continue to execute instructions.

fn reset(&mut self) -> Result<(), Error>

Reset the core, and then continue to execute instructions. If the core should be halted after reset, use the reset_and_halt function.

fn reset_and_halt(
    &mut self,
    _timeout: Duration
) -> Result<CoreInformation, Error>

Reset the core, and then immediately halt. To continue execution after reset, use the reset function.

fn step(&mut self) -> Result<CoreInformation, Error>

Steps one instruction and then enters halted state again.

fn read_core_reg(&mut self, address: RegisterId) -> Result<RegisterValue, Error>

Read the value of a core register.

fn write_core_reg(
    &mut self,
    address: RegisterId,
    value: RegisterValue
) -> Result<(), Error>

Write the value of a core register.

fn available_breakpoint_units(&mut self) -> Result<u32, Error>

Returns all the available breakpoint units of the core.

fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>

Enables breakpoints on this core. If a breakpoint is set, it will halt as soon as it is hit.

fn set_hw_breakpoint(
    &mut self,
    bp_unit_index: usize,
    addr: u64
) -> Result<(), Error>

Sets a breakpoint at addr. It does so by using unit bp_unit_index.

fn registers(&self) -> &'static RegisterFile

Returns a list of all the registers of this core.

fn clear_hw_breakpoint(&mut self, bp_unit_index: usize) -> Result<(), Error>

Clears the breakpoint configured in unit unit_index.

fn hw_breakpoints_enabled(&self) -> bool

Returns true if hwardware breakpoints are enabled, false otherwise.

fn architecture(&self) -> Architecture

Get the Architecture of the Core.

fn core_type(&self) -> CoreType

Get the CoreType of the Core

fn instruction_set(&mut self) -> Result<InstructionSet, Error>

Determine the instruction set the core is operating in This must be queried while halted as this is a runtime decision for some core types

fn status(&mut self) -> Result<CoreStatus, Error>

Returns the current status of the core.

fn fpu_support(&mut self) -> Result<bool, Error>

Determine if an FPU is present. This must be queried while halted as this is a runtime decision for some core types.

fn debug_on_sw_breakpoint(&mut self, _enabled: bool) -> Result<(), Error>

Configure the target to ensure software breakpoints will enter Debug Mode.

fn on_session_stop(&mut self) -> Result<(), Error>

Called during session stop to do any pending cleanup

impl<'probe> MemoryInterface for Armv8m<'probe>

fn supports_native_64bit_access(&mut self) -> bool

Does this interface support native 64-bit wide accesses

fn read_word_32(&mut self, address: u64) -> Result<u32, Error>

Read a 32bit word of at address.

fn read_word_8(&mut self, address: u64) -> Result<u8, Error>

Read an 8bit word of at address.

fn read_64(&mut self, address: u64, data: &mut [u64]) -> Result<(), Error>

Read a block of 64bit words at address.

fn read_32(&mut self, address: u64, data: &mut [u32]) -> Result<(), Error>

Read a block of 32bit words at address.

fn read_8(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>

Read a block of 8bit words at address.

fn read_word_64(&mut self, address: u64) -> Result<u64, Error>

Read a 64bit word of at address.

fn write_word_64(&mut self, address: u64, data: u64) -> Result<(), Error>

Write a 64bit word at address.

fn write_word_32(&mut self, address: u64, data: u32) -> Result<(), Error>

Write a 32bit word at address.

fn write_word_8(&mut self, address: u64, data: u8) -> Result<(), Error>

Write an 8bit word at address.

fn write_64(&mut self, address: u64, data: &[u64]) -> Result<(), Error>

Write a block of 64bit words at address.

fn write_32(&mut self, address: u64, data: &[u32]) -> Result<(), Error>

Write a block of 32bit words at address.

fn write_8(&mut self, address: u64, data: &[u8]) -> Result<(), Error>

Write a block of 8bit words at address.

fn write(&mut self, address: u64, data: &[u8]) -> Result<(), Error>

Write a block of 8bit words at address. May use 64 bit memory access, so should only be used if reading memory locations that don’t have side effects. Generally faster than MemoryInterface::write_8.

fn supports_8bit_transfers(&self) -> Result<bool, Error>

Returns whether the current platform supports native 8bit transfers.

fn flush(&mut self) -> Result<(), Error>

Flush any outstanding operations.

fn read_mem_64bit(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>

Reads bytes using 64 bit memory access. Address must be 64 bit aligned and data must be an exact multiple of 8.

fn read_mem_32bit(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>

Reads bytes using 32 bit memory access. Address must be 32 bit aligned and data must be an exact multiple of 4.

fn read(&mut self, address: u64, data: &mut [u8]) -> Result<(), Error>

Read data from address.

fn write_mem_64bit(&mut self, address: u64, data: &[u8]) -> Result<(), Error>

Writes bytes using 64 bit memory access. Address must be 64 bit aligned and data must be an exact multiple of 8.

fn write_mem_32bit(&mut self, address: u64, data: &[u8]) -> Result<(), Error>

Writes bytes using 32 bit memory access. Address must be 32 bit aligned and data must be an exact multiple of 8.