Expand description
Phase 3: Cranelift JIT compilation of Polydat Kernels.
Generates native machine code from the DAG. The entire kernel
becomes a single function: fn(coords: *const u64, buffer: *mut u64).
No closures, no function pointers, no gather/scatter — direct
buffer reads and writes with inlined arithmetic.
The buffer is Vec<u64>. For f64 values, they are stored as their
bit representation (f64::to_bits() / f64::from_bits()). The JIT
uses Cranelift bitcast (free, no instruction emitted) to convert
between i64 and f64 representations when crossing type boundaries.
Feature-gated behind jit.
For nodes that can’t be JIT-compiled inline (hash, shuffle, interleave), we emit a call to an extern function. Simple ops are fully inlined, complex ops are extern calls with zero overhead beyond the call itself.
Modules§
- host_
isa - One source of truth for the effective native Cranelift ISA.
- simd
- Cranelift-SIMD compute kernels for element-wise vector math (type_system_alignment.md §8.2, execution level).
Structs§
- JitCode
- Finalized native code, shared by every kernel created from one program. The module’s memory is never written after finalization, so sharing it across threads is sound; the wrapper exists so a kernel clone is a new state over the same code. The slot kits the code calls by address live beside it, for as long as it does.
- Slot
KitRef - A node’s slot kit as native code holds it: shared by every kernel compiled from the program, compared by identity.
Enums§
- JitOp
- Description of a JIT step — what operation to generate.
- RegLane
Read - The register lane reads with a named lowering: each returns the lane as the slot word its port stores.
- RegProducer
- The register producers that run through a helper: a bounds check on a wire index, or a lane operation Cranelift has no instruction for. Each writes its word into the output slots.
- VecProducer
- The vector producers with a named lowering (compiled_handles.md
§6): each writes its result into the step’s own
F32entry and publishes the pair. - VecReducer
- The vector reductions with a named lowering: each returns the
bits of its
f64result.
Functions§
- classify_
node - Classify a Polydat node into a JIT-able operation.
- classify_
node_ typed - Classify a node with the types of its wire inputs known. A node
with a named native lowering takes it; any other node with a kit
is a
JitOp::SlotCallof that kit, so a reference pair on either side is no bar to native code, and neither is nondeterminism or a side effect: the kernels that run the code keep such a step’s currency its own (a segment of its own on the hybrid kernel, a never-current step on pure native code). A node with neither stays interpreted.
Type Aliases§
- JitParts
- A raw native kernel taken apart: its entry point and its code.
- Native
Fn - A native entry point over a state’s slot buffer and scratch.
- Native
Prov Fn - The provenance variant: a clean flag per step follows the scratch.