Enum JitOp 

pub enum JitOp {
    Identity,
    AddConst(u64),
    MulConst(u64),
    DivConst(u64),
    ModConst(u64),
    ClampConst(u64, u64),
    Interleave,
    MixedRadixConst(Vec<u64>),
    Hash,
    SplitMix64,
    Popcnt,
    Clz,
    Ctz,
    Bswap,
    ShuffleConst(u64, u64, u64),
    UnitInterval,
    F64ToU64,
    RoundToU64,
    FloorToU64,
    CeilToU64,
    ClampF64Const(u64, u64),
    LerpConst(u64, u64),
    ScaleRangeConst(u64, u64),
    QuantizeConst(u64),
    DiscretizeConst(u64, u64),
    LutSampleConst(u64, u64),
    WeightedPickConst(u64, u64, u64, u64, u64),
    MathUnary(u8),
    MathBinary(u8),
    U64Add2,
    U64Sub2,
    U64Mul2,
    U64Div2,
    U64Mod2,
    U64And,
    U64Or,
    U64Xor,
    U64Shl,
    U64Shr,
    U64Not,
    ToF64,
    F64Add,
    F64Sub,
    F64Mul,
    F64Div,
    F64Mod,
    U64DivWire,
    U64ModWire,
    SlotCall {
        kit: SlotKitRef,
        scratch_base: usize,
    },
    U64ToStr {
        scratch_base: usize,
    },
    I64ToStr {
        scratch_base: usize,
    },
    F64ToStr {
        scratch_base: usize,
    },
    StrConcat {
        scratch_base: usize,
    },
    JsonToStr {
        scratch_base: usize,
    },
    VecProduce {
        kind: VecProducer,
        scratch_base: usize,
    },
    VecReduce(VecReducer),
    RegLane(RegLaneRead),
    RegProduce(RegProducer),
    RegDotF32,
    RegShuffleConst([u8; 16]),
    IsPositiveCheck {
        name_ptr: u64,
        name_len: u64,
    },
    InRangeCheck(u64, u64),
    IsOneOfCheck {
        allowed: Vec<u64>,
        set_ptr: u64,
        set_len: u64,
    },
    RegBinOp(u8, u8),
    RegCopy,
    RegSplat(u8),
    U64Cmp(IntCC),
    F64Cmp(FloatCC),
    SelectU64,
    SelectF64,
    I64ToF64,
    F64ToI64,
    SignExtendI32,
    SignExtendI16,
    SignExtendI8,
    ZeroExtendU32,
    ZeroExtendU16,
    ZeroExtendU8,
    ToBool,
    ConstU64(u64),
    ConstF64(u64),
    HashRangeConst(u64),
    HashIntervalConst(u64, u64),
    InvLerpConst(u64, u64),
    RemapConst(u64, u64, u64, u64),
    EpochOffsetConst(u64),
    EpochScaleConst(u64),
    ThreadId,
    CurrentEpochMillis,
    Perlin1dConst(u64, u64),
    Perlin2dConst(u64, u64),
    Simplex2dConst(u64, u64),
    FractalNoise1dConst(u64, u64, u64),
    FractalNoise2dConst(u64, u64, u64),
    VariadicSum,
    VariadicProduct,
    VariadicMin,
    VariadicMax,
    CheckedAdd,
    CheckedSub,
    CheckedMul,
    CeilToMultiple,
    MultiplesAtLeast,
    FairCoin,
    BlendConst(u64),
    LfsrStepConst(u64),
    PcgConst(u64, u64),
    PcgStreamConst(u64),
    CycleWalkConst(u64, u64, u64),
    UnfairCoinConst(u64),
    CoinFlipConst(u64),
    ChanceConst(u64),
    NOfConst(u64, u64),
    Fallback,
}

Description of a JIT step — what operation to generate.

For f64 operations, values are stored in the u64 buffer as their bit representation. Cranelift bitcast converts between i64/f64.

Variants

Identity

output[0] = input[0] (identity / copy)

AddConst(u64)

output[0] = input[0] + constant

MulConst(u64)

output[0] = input[0] * constant

DivConst(u64)

output[0] = input[0] / constant

ModConst(u64)

output[0] = input[0] % constant

ClampConst(u64, u64)

output[0] = clamp(input[0], min, max) (unsigned)

Interleave

output[0] = interleave_bits(input[0], input[1]) (extern call)

MixedRadixConst(Vec<u64>)

output[i] = mixed-radix decomposition of input[0] (inline urem/udiv)

Hash

output[0] = xxh3_hash(input[0]) (extern call)

SplitMix64

output[0] = splitmix64(input[0]) (fully inlined 64-bit ALU bit mixer)

Popcnt

output[0] = popcount(input[0])

Clz

output[0] = leading_zeros(input[0])

Ctz

output[0] = trailing_zeros(input[0])

Bswap

output[0] = byte_swap(input[0])

ShuffleConst(u64, u64, u64)

output[0] = shuffle(input[0]) (extern call: feedback, size, min)

UnitInterval

output[0] = input[0] as f64 / u64::MAX as f64 (u64 → f64 bits)

F64ToU64

output[0] = f64::from_bits(input[0]) as u64 (f64 bits → u64, truncate)

RoundToU64

output[0] = f64::from_bits(input[0]).round() as u64: half away from zero, as Rust rounds, then the saturating conversion.

FloorToU64

output[0] = f64::from_bits(input[0]).floor() as u64

CeilToU64

output[0] = f64::from_bits(input[0]).ceil() as u64

ClampF64Const(u64, u64)

output[0] = clamp(f64::from_bits(input[0]), min, max) → f64 bits

LerpConst(u64, u64)

output[0] = a + (b - a) * f64::from_bits(input[0]) → f64 bits

ScaleRangeConst(u64, u64)

output[0] = min + range * (input[0] as f64 / MAX) → f64 bits (u64 input)

QuantizeConst(u64)

output[0] = round(f64::from_bits(input[0]) / step) * step → f64 bits

DiscretizeConst(u64, u64)

output[0] = discretize(f64 input, range, buckets) → u64

LutSampleConst(u64, u64)

output[0] = lut_sample(f64 input, lut_ptr, lut_len) → f64 bits (extern call)

WeightedPickConst(u64, u64, u64, u64, u64)

output[0] = weighted_pick(input, values_ptr, biases_ptr, primaries_ptr, aliases_ptr, n)

MathUnary(u8)

Unary f64 math function via extern call. The u8 identifies which function. 0=sin 1=cos 2=tan 3=asin 4=acos 5=atan 6=sqrt 7=abs 8=ln 9=exp

MathBinary(u8)

Binary f64 math function via extern call. 0=atan2 1=pow

U64Add2

output = input[0] + input[1] (wrapping)

U64Sub2

output = input[0] - input[1] (wrapping)

U64Mul2

output = input[0] * input[1] (wrapping)

U64Div2

output = input[0] / input[1] (0 if divisor is 0)

U64Mod2

output = input[0] % input[1] (0 if divisor is 0)

U64And

output = input[0] & input[1]

U64Or

output = input[0] | input[1]

U64Xor

output = input[0] ^ input[1]

U64Shl

output = input[0] << input[1]

U64Shr

output = input[0] >> input[1] (logical)

U64Not

output = !input[0] (unary bitwise NOT)

ToF64

output = input as f64 (integer to float conversion, not bit reinterpret)

F64Add

output = f64(a) + f64(b)

F64Sub

output = f64(a) - f64(b)

F64Mul

output = f64(a) * f64(b)

F64Div

output = f64(a) / f64(b) (0 if b==0)

F64Mod

output = f64(a) % f64(b) (0 if b==0), through jit_f64_mod

U64DivWire

output[0] = input[0] / input[1], failing on a zero divisor as the body’s / does (div_wire)

U64ModWire

output[0] = input[0] % input[1], failing on a zero divisor as the body’s % does (mod_wire)

SlotCall

A call of the node’s own slot kit from native code (compiled_handles.md §6): the inputs are gathered into the frame, jit_slot_call runs the kit’s closure over them and the state’s scratch entries at scratch_base, and the outputs are scattered back. Every node with a kit lowers this way, so a reference pair rides through a segment or a cone as it rides through a closure step.

Fields

kit: SlotKitRef

The kit, shared by every kernel compiled from the program and kept alive by the code that calls it.

scratch_base: usize

Index of the kit’s first scratch entry in the state’s scratch, assigned by the builder that lays the state out.

U64ToStr

output = decimal digits of input[0] as a u64

Fields

scratch_base: usize

The step’s string entry in the state’s scratch.

I64ToStr

output = decimal digits of input[0] as an i64

Fields

scratch_base: usize

The step’s string entry in the state’s scratch.

F64ToStr

output = Display form of input[0] as an f64

Fields

scratch_base: usize

The step’s string entry in the state’s scratch.

StrConcat

output = the concatenation of every input pair's bytes, for a str_concat whose wires are all strings.

Fields

scratch_base: usize

The step’s string entry in the state’s scratch.

JsonToStr

output = compact serialization of the JSON value input[0..2] names

Fields

scratch_base: usize

The step’s string entry in the state’s scratch.

VecProduce

output = a vec_f32 written into the step's own F32 entry by the producer’s body over the input words.

Fields

kind: VecProducer

Which producer.

scratch_base: usize

The step’s F32 entry in the state’s scratch.

VecReduce(VecReducer)

output[0] = f64 bits of the reduction over the input words

RegLane(RegLaneRead)

output[0] = lane input[2] of the register word input[0..2], bounds-checked by the helper.

RegProduce(RegProducer)

output[0..2] = the producer's word over the input words

RegDotF32

output[0] = ((a0*b0 + a1*b1) + (a2*b2 + a3*b3)) as f64, the fixed tree of reg_dot_f32, over f32x4 words: one fmul, four lane extracts, three adds, one promotion.

RegShuffleConst([u8; 16])

output[0..2] = byte permutation of input[0..2] by a baked 16-entry mask, one shuffle.

IsPositiveCheck

Parameter predicate: pass input[0] through to output[0]; if input[0] == 0, call jit_is_positive_fail (panics) with the configured predicate name — (ptr, len) into the node’s meta const, (0, 0) for the default. Message parity with the interpreter’s is_positive({name}): … is asserted by the SRD-105 battery.

Fields

name_ptr: u64

Address of the predicate’s name, or 0 for the default.

name_len: u64

Its length in bytes.

InRangeCheck(u64, u64)

Parameter predicate: pass input[0] through to output[0]; if input[0] < lo or input[0] > hi, call jit_in_range_fail (panics). Stored as (lo, hi).

IsOneOfCheck

Parameter predicate: pass input[0] through to output[0]; if input[0] is not in the allow-list, call jit_is_one_of_fail (panics) with the allow-list contents — (ptr, len) into the node’s meta VecU64 const, (0, 0) when unavailable. Message parity with the interpreter’s is_one_of: … not in allowed set […] is asserted by the SRD-105 battery. Inline comparisons use the baked vector.

Fields

allowed: Vec<u64>

The allow-list, baked into the comparisons.

set_ptr: u64

Address of the node’s allow-list constant for the message, or 0.

set_len: u64

Its length.

RegBinOp(u8, u8)

Element-wise register binop. (lane_ty index, arith index) — lanes: 0=i8x16 1=i16x8 2=i32x4 3=i64x2 4=f32x4 5=f64x2; arith: 0=add 1=sub 2=mul.

RegCopy

View retag / two-slot copy (__reg_view_*): one 128-bit load + store; the lane typing is static, so no instruction beyond the move.

RegSplat(u8)

Broadcast a scalar wire into all lanes. Same lane index vocabulary as RegBinOp; float lanes read the f64 slot and demote as needed, integer lanes reduce from u64.

U64Cmp(IntCC)

Integer comparison: output[0] = if a <cond> b { 1 } else { 0 }

F64Cmp(FloatCC)

Float comparison: output[0] = if a <cond> b { 1 } else { 0 }

SelectU64

Conditional select for u64: output[0] = if cond != 0 { a } else { b }

SelectF64

Conditional select for f64: output[0] = if cond != 0 { a } else { b }

I64ToF64

Signed integer to float: output[0] = (input[0] as i64 as f64).to_bits()

F64ToI64

Float to signed integer: output[0] = (f64::from_bits(input[0]) as i64) as u64

SignExtendI32

Sign-extend 32-bit integer: output[0] = ((input[0] as i32) as i64) as u64

SignExtendI16

Sign-extend 16-bit integer: output[0] = ((input[0] as i16) as i64) as u64

SignExtendI8

Sign-extend 8-bit integer: output[0] = ((input[0] as i8) as i64) as u64

ZeroExtendU32

Zero-extend 32-bit integer: output[0] = (input[0] as u32) as u64

ZeroExtendU16

Zero-extend 16-bit integer: output[0] = (input[0] as u16) as u64

ZeroExtendU8

Zero-extend 8-bit integer: output[0] = (input[0] as u8) as u64

ToBool

Truthiness boolean coercion: output[0] = if input[0] != 0 { 1 } else { 0 }

ConstU64(u64)

Constant u64: output[0] = val

ConstF64(u64)

Constant f64: output[0] = val_bits

HashRangeConst(u64)

Hash range: output[0] = if max == 0 { 0 } else { hash(input[0]) % max }

HashIntervalConst(u64, u64)

Hash interval: output[0] = min + (hash(input[0]) / MAX) * (max - min)

InvLerpConst(u64, u64)

Inverse lerp: output[0] = ((input[0] - a) / (b - a)).clamp(0, 1)

RemapConst(u64, u64, u64, u64)

Remap: output[0] = out_min + ((input[0] - in_min) / (in_max - in_min)) * (out_max - out_min)

EpochOffsetConst(u64)

Epoch offset: output[0] = input[0].wrapping_add(base)

EpochScaleConst(u64)

Epoch scale: output[0] = input[0].wrapping_mul(factor)

ThreadId

OS thread ID

CurrentEpochMillis

Wall clock millis

Perlin1dConst(u64, u64)

output[0] = jit_perlin_1d(input[0], perm, freq): (permutation table address, frequency bits).

Perlin2dConst(u64, u64)

jit_perlin_2d over two inputs: (permutation table address, frequency bits).

Simplex2dConst(u64, u64)

jit_simplex_2d over two inputs: (permutation table address, frequency bits).

FractalNoise1dConst(u64, u64, u64)

jit_fractal_noise_1d: (permutation table address, frequency bits, octaves).

FractalNoise2dConst(u64, u64, u64)

jit_fractal_noise_2d over two inputs: (permutation table address, frequency bits, octaves).

VariadicSum

Variadic sum across all inputs

VariadicProduct

Variadic product across all inputs

VariadicMin

Variadic minimum across all inputs (unsigned)

VariadicMax

Variadic maximum across all inputs (unsigned)

CheckedAdd

Checked unsigned addition: output[0] = a.checked_add(b).unwrap_or(0)

CheckedSub

Saturating unsigned subtraction: output[0] = a.saturating_sub(b)

CheckedMul

Checked unsigned multiplication: output[0] = a.checked_mul(b).unwrap_or(0)

CeilToMultiple

Smallest multiple of multiple >= value: output[0] = if m == 0 { v } else { v.div_ceil(m).saturating_mul(m) }

MultiplesAtLeast

Multiples at least: output[0] = if m == 0 { 0 } else { v.div_ceil(m) }

FairCoin

Fair coin flip: output[0] = input[0] & 1

BlendConst(u64)

Float blend with constant mix: output[0] = (fa * (1 - mix) + fb * mix).round() as u64

LfsrStepConst(u64)

LFSR advance step with constant feedback polynomial: output[0] = (input[0] >> 1) ^ (if input[0] & 1 != 0 { feedback } else { 0 })

PcgConst(u64, u64)

PCG random with constant seed and stream: (seed, stream)

PcgStreamConst(u64)

PCG random with wire stream and constant seed: (seed)

CycleWalkConst(u64, u64, u64)

Cycle walk: (range, seed, inc)

UnfairCoinConst(u64)

Unfair coin with constant probability: (p_bits)

CoinFlipConst(u64)

coin_flip: the input compared unsigned against a threshold the node computed from its probability at construction; no hash.

ChanceConst(u64)

Chance with constant probability: (p_bits)

NOfConst(u64, u64)

N-of-M selection with constant n and m: (n, m)

Fallback

Fallback: call the Phase 2 closure

Trait Implementations

impl Clone for JitOp

fn clone(&self) -> JitOp

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for JitOp

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl PartialEq for JitOp

fn eq(&self, other: &JitOp) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for JitOp