Enum RiscVInstr 

pub enum RiscVInstr {
    LUI(RiscVReg, u32),
    AUIPC(RiscVReg, u32),
    JAL(RiscVReg, i32),
    JALR(RiscVReg, RiscVReg, i16),
    BEQ(RiscVReg, RiscVReg, i16),
    BNE(RiscVReg, RiscVReg, i16),
    BLT(RiscVReg, RiscVReg, i16),
    BGE(RiscVReg, RiscVReg, i16),
    BLTU(RiscVReg, RiscVReg, i16),
    BGEU(RiscVReg, RiscVReg, i16),
    LB(RiscVReg, RiscVReg, i16),
    LH(RiscVReg, RiscVReg, i16),
    LW(RiscVReg, RiscVReg, i16),
    LBU(RiscVReg, RiscVReg, i16),
    LHU(RiscVReg, RiscVReg, i16),
    LD(RiscVReg, RiscVReg, i16),
    LWU(RiscVReg, RiscVReg, i16),
    SB(RiscVReg, RiscVReg, i16),
    SH(RiscVReg, RiscVReg, i16),
    SW(RiscVReg, RiscVReg, i16),
    SD(RiscVReg, RiscVReg, i16),
    ADDI(RiscVReg, RiscVReg, i16),
    SLTI(RiscVReg, RiscVReg, i16),
    SLTIU(RiscVReg, RiscVReg, i16),
    XORI(RiscVReg, RiscVReg, i16),
    ORI(RiscVReg, RiscVReg, i16),
    ANDI(RiscVReg, RiscVReg, i16),
    SLLI(RiscVReg, RiscVReg, u8),
    SRLI(RiscVReg, RiscVReg, u8),
    SRAI(RiscVReg, RiscVReg, u8),
    ADDIW(RiscVReg, RiscVReg, i16),
    ADD(RiscVReg, RiscVReg, RiscVReg),
    SUB(RiscVReg, RiscVReg, RiscVReg),
    SLL(RiscVReg, RiscVReg, RiscVReg),
    SLT(RiscVReg, RiscVReg, RiscVReg),
    SLTU(RiscVReg, RiscVReg, RiscVReg),
    XOR(RiscVReg, RiscVReg, RiscVReg),
    SRL(RiscVReg, RiscVReg, RiscVReg),
    SRA(RiscVReg, RiscVReg, RiscVReg),
    OR(RiscVReg, RiscVReg, RiscVReg),
    AND(RiscVReg, RiscVReg, RiscVReg),
    MUL(RiscVReg, RiscVReg, RiscVReg),
    MULH(RiscVReg, RiscVReg, RiscVReg),
    DIV(RiscVReg, RiscVReg, RiscVReg),
    REM(RiscVReg, RiscVReg, RiscVReg),
    ECALL,
    EBREAK,
    Label(String),
    Directive(String, String),
    LI(RiscVReg, i64),
    MV(RiscVReg, RiscVReg),
    NOP,
    RET,
    CALL(String),
}

RISC-V instructions (RV32I/RV64I base subset).

Variants

LUI(RiscVReg, u32)

AUIPC(RiscVReg, u32)

JAL(RiscVReg, i32)

JALR(RiscVReg, RiscVReg, i16)

BEQ(RiscVReg, RiscVReg, i16)

BNE(RiscVReg, RiscVReg, i16)

BLT(RiscVReg, RiscVReg, i16)

BGE(RiscVReg, RiscVReg, i16)

BLTU(RiscVReg, RiscVReg, i16)

BGEU(RiscVReg, RiscVReg, i16)

LB(RiscVReg, RiscVReg, i16)

LH(RiscVReg, RiscVReg, i16)

LW(RiscVReg, RiscVReg, i16)

LBU(RiscVReg, RiscVReg, i16)

LHU(RiscVReg, RiscVReg, i16)

LD(RiscVReg, RiscVReg, i16)

LWU(RiscVReg, RiscVReg, i16)

SB(RiscVReg, RiscVReg, i16)

SH(RiscVReg, RiscVReg, i16)

SW(RiscVReg, RiscVReg, i16)

SD(RiscVReg, RiscVReg, i16)

ADDI(RiscVReg, RiscVReg, i16)

SLTI(RiscVReg, RiscVReg, i16)

SLTIU(RiscVReg, RiscVReg, i16)

XORI(RiscVReg, RiscVReg, i16)

ORI(RiscVReg, RiscVReg, i16)

ANDI(RiscVReg, RiscVReg, i16)

SLLI(RiscVReg, RiscVReg, u8)

SRLI(RiscVReg, RiscVReg, u8)

SRAI(RiscVReg, RiscVReg, u8)

ADDIW(RiscVReg, RiscVReg, i16)

ADD(RiscVReg, RiscVReg, RiscVReg)

SUB(RiscVReg, RiscVReg, RiscVReg)

SLL(RiscVReg, RiscVReg, RiscVReg)

SLT(RiscVReg, RiscVReg, RiscVReg)

SLTU(RiscVReg, RiscVReg, RiscVReg)

XOR(RiscVReg, RiscVReg, RiscVReg)

SRL(RiscVReg, RiscVReg, RiscVReg)

SRA(RiscVReg, RiscVReg, RiscVReg)

OR(RiscVReg, RiscVReg, RiscVReg)

AND(RiscVReg, RiscVReg, RiscVReg)

MUL(RiscVReg, RiscVReg, RiscVReg)

MULH(RiscVReg, RiscVReg, RiscVReg)

DIV(RiscVReg, RiscVReg, RiscVReg)

REM(RiscVReg, RiscVReg, RiscVReg)

ECALL

EBREAK

Label(String)

Directive(String, String)

LI(RiscVReg, i64)

Pseudo-instruction: load immediate (expanded by assembler).

MV(RiscVReg, RiscVReg)

Pseudo-instruction: move.

NOP

Pseudo-instruction: no-op.

RET

Pseudo-instruction: return (jalr zero, ra, 0).

CALL(String)

Pseudo-instruction: call function by name.

Trait Implementations

impl Clone for RiscVInstr

fn clone(&self) -> RiscVInstr

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for RiscVInstr

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.