pub enum RiscVReg {
Show 32 variants
Zero,
Ra,
Sp,
Gp,
Tp,
T0,
T1,
T2,
S0,
S1,
A0,
A1,
A2,
A3,
A4,
A5,
A6,
A7,
S2,
S3,
S4,
S5,
S6,
S7,
S8,
S9,
S10,
S11,
T3,
T4,
T5,
T6,
}Expand description
RISC-V register set (integer registers, ABI names).
Variants§
Zero
Ra
Sp
Gp
Tp
T0
T1
T2
S0
S1
A0
A1
A2
A3
A4
A5
A6
A7
S2
S3
S4
S5
S6
S7
S8
S9
S10
S11
T3
T4
T5
T6
Implementations§
Trait Implementations§
impl StructuralPartialEq for RiscVReg
Auto Trait Implementations§
impl Freeze for RiscVReg
impl RefUnwindSafe for RiscVReg
impl Send for RiscVReg
impl Sync for RiscVReg
impl Unpin for RiscVReg
impl UnsafeUnpin for RiscVReg
impl UnwindSafe for RiscVReg
Blanket Implementations§
Source§impl<T> BorrowMut<T> for Twhere
T: ?Sized,
impl<T> BorrowMut<T> for Twhere
T: ?Sized,
Source§fn borrow_mut(&mut self) -> &mut T
fn borrow_mut(&mut self) -> &mut T
Mutably borrows from an owned value. Read more