[−][src]Struct nrf52832_hal::pac::generic::W
Implementations
impl<U, REG> W<U, REG>
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impl W<u32, Reg<u32, _NRFFW>>
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impl W<u32, Reg<u32, _NRFHW>>
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impl W<u32, Reg<u32, _CUSTOMER>>
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pub fn customer(&mut self) -> CUSTOMER_W<'_>
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Bits 0:31 - Reserved for customer
impl W<u32, Reg<u32, _PSELRESET>>
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pub fn pin(&mut self) -> PIN_W<'_>
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Bits 0:5 - GPIO number P0.n onto which Reset is exposed
pub fn connect(&mut self) -> CONNECT_W<'_>
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Bit 31 - Connection
impl W<u32, Reg<u32, _APPROTECT>>
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pub fn pall(&mut self) -> PALL_W<'_>
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Bits 0:7 - Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection.
impl W<u32, Reg<u32, _NFCPINS>>
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pub fn protect(&mut self) -> PROTECT_W<'_>
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Bit 0 - Setting of pins dedicated to NFC functionality
impl W<u32, Reg<u32, _CONFIG0>>
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pub fn region0(&mut self) -> REGION0_W<'_>
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Bit 0 - Enable protection for region 0. Write '0' has no effect.
pub fn region1(&mut self) -> REGION1_W<'_>
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Bit 1 - Enable protection for region 1. Write '0' has no effect.
pub fn region2(&mut self) -> REGION2_W<'_>
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Bit 2 - Enable protection for region 2. Write '0' has no effect.
pub fn region3(&mut self) -> REGION3_W<'_>
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Bit 3 - Enable protection for region 3. Write '0' has no effect.
pub fn region4(&mut self) -> REGION4_W<'_>
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Bit 4 - Enable protection for region 4. Write '0' has no effect.
pub fn region5(&mut self) -> REGION5_W<'_>
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Bit 5 - Enable protection for region 5. Write '0' has no effect.
pub fn region6(&mut self) -> REGION6_W<'_>
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Bit 6 - Enable protection for region 6. Write '0' has no effect.
pub fn region7(&mut self) -> REGION7_W<'_>
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Bit 7 - Enable protection for region 7. Write '0' has no effect.
pub fn region8(&mut self) -> REGION8_W<'_>
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Bit 8 - Enable protection for region 8. Write '0' has no effect.
pub fn region9(&mut self) -> REGION9_W<'_>
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Bit 9 - Enable protection for region 9. Write '0' has no effect.
pub fn region10(&mut self) -> REGION10_W<'_>
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Bit 10 - Enable protection for region 10. Write '0' has no effect.
pub fn region11(&mut self) -> REGION11_W<'_>
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Bit 11 - Enable protection for region 11. Write '0' has no effect.
pub fn region12(&mut self) -> REGION12_W<'_>
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Bit 12 - Enable protection for region 12. Write '0' has no effect.
pub fn region13(&mut self) -> REGION13_W<'_>
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Bit 13 - Enable protection for region 13. Write '0' has no effect.
pub fn region14(&mut self) -> REGION14_W<'_>
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Bit 14 - Enable protection for region 14. Write '0' has no effect.
pub fn region15(&mut self) -> REGION15_W<'_>
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Bit 15 - Enable protection for region 15. Write '0' has no effect.
pub fn region16(&mut self) -> REGION16_W<'_>
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Bit 16 - Enable protection for region 16. Write '0' has no effect.
pub fn region17(&mut self) -> REGION17_W<'_>
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Bit 17 - Enable protection for region 17. Write '0' has no effect.
pub fn region18(&mut self) -> REGION18_W<'_>
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Bit 18 - Enable protection for region 18. Write '0' has no effect.
pub fn region19(&mut self) -> REGION19_W<'_>
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Bit 19 - Enable protection for region 19. Write '0' has no effect.
pub fn region20(&mut self) -> REGION20_W<'_>
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Bit 20 - Enable protection for region 20. Write '0' has no effect.
pub fn region21(&mut self) -> REGION21_W<'_>
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Bit 21 - Enable protection for region 21. Write '0' has no effect.
pub fn region22(&mut self) -> REGION22_W<'_>
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Bit 22 - Enable protection for region 22. Write '0' has no effect.
pub fn region23(&mut self) -> REGION23_W<'_>
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Bit 23 - Enable protection for region 23. Write '0' has no effect.
pub fn region24(&mut self) -> REGION24_W<'_>
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Bit 24 - Enable protection for region 24. Write '0' has no effect.
pub fn region25(&mut self) -> REGION25_W<'_>
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Bit 25 - Enable protection for region 25. Write '0' has no effect.
pub fn region26(&mut self) -> REGION26_W<'_>
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Bit 26 - Enable protection for region 26. Write '0' has no effect.
pub fn region27(&mut self) -> REGION27_W<'_>
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Bit 27 - Enable protection for region 27. Write '0' has no effect.
pub fn region28(&mut self) -> REGION28_W<'_>
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Bit 28 - Enable protection for region 28. Write '0' has no effect.
pub fn region29(&mut self) -> REGION29_W<'_>
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Bit 29 - Enable protection for region 29. Write '0' has no effect.
pub fn region30(&mut self) -> REGION30_W<'_>
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Bit 30 - Enable protection for region 30. Write '0' has no effect.
pub fn region31(&mut self) -> REGION31_W<'_>
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Bit 31 - Enable protection for region 31. Write '0' has no effect.
impl W<u32, Reg<u32, _CONFIG1>>
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pub fn region32(&mut self) -> REGION32_W<'_>
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Bit 0 - Enable protection for region 32. Write '0' has no effect.
pub fn region33(&mut self) -> REGION33_W<'_>
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Bit 1 - Enable protection for region 33. Write '0' has no effect.
pub fn region34(&mut self) -> REGION34_W<'_>
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Bit 2 - Enable protection for region 34. Write '0' has no effect.
pub fn region35(&mut self) -> REGION35_W<'_>
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Bit 3 - Enable protection for region 35. Write '0' has no effect.
pub fn region36(&mut self) -> REGION36_W<'_>
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Bit 4 - Enable protection for region 36. Write '0' has no effect.
pub fn region37(&mut self) -> REGION37_W<'_>
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Bit 5 - Enable protection for region 37. Write '0' has no effect.
pub fn region38(&mut self) -> REGION38_W<'_>
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Bit 6 - Enable protection for region 38. Write '0' has no effect.
pub fn region39(&mut self) -> REGION39_W<'_>
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Bit 7 - Enable protection for region 39. Write '0' has no effect.
pub fn region40(&mut self) -> REGION40_W<'_>
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Bit 8 - Enable protection for region 40. Write '0' has no effect.
pub fn region41(&mut self) -> REGION41_W<'_>
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Bit 9 - Enable protection for region 41. Write '0' has no effect.
pub fn region42(&mut self) -> REGION42_W<'_>
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Bit 10 - Enable protection for region 42. Write '0' has no effect.
pub fn region43(&mut self) -> REGION43_W<'_>
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Bit 11 - Enable protection for region 43. Write '0' has no effect.
pub fn region44(&mut self) -> REGION44_W<'_>
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Bit 12 - Enable protection for region 44. Write '0' has no effect.
pub fn region45(&mut self) -> REGION45_W<'_>
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Bit 13 - Enable protection for region 45. Write '0' has no effect.
pub fn region46(&mut self) -> REGION46_W<'_>
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Bit 14 - Enable protection for region 46. Write '0' has no effect.
pub fn region47(&mut self) -> REGION47_W<'_>
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Bit 15 - Enable protection for region 47. Write '0' has no effect.
pub fn region48(&mut self) -> REGION48_W<'_>
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Bit 16 - Enable protection for region 48. Write '0' has no effect.
pub fn region49(&mut self) -> REGION49_W<'_>
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Bit 17 - Enable protection for region 49. Write '0' has no effect.
pub fn region50(&mut self) -> REGION50_W<'_>
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Bit 18 - Enable protection for region 50. Write '0' has no effect.
pub fn region51(&mut self) -> REGION51_W<'_>
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Bit 19 - Enable protection for region 51. Write '0' has no effect.
pub fn region52(&mut self) -> REGION52_W<'_>
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Bit 20 - Enable protection for region 52. Write '0' has no effect.
pub fn region53(&mut self) -> REGION53_W<'_>
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Bit 21 - Enable protection for region 53. Write '0' has no effect.
pub fn region54(&mut self) -> REGION54_W<'_>
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Bit 22 - Enable protection for region 54. Write '0' has no effect.
pub fn region55(&mut self) -> REGION55_W<'_>
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Bit 23 - Enable protection for region 55. Write '0' has no effect.
pub fn region56(&mut self) -> REGION56_W<'_>
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Bit 24 - Enable protection for region 56. Write '0' has no effect.
pub fn region57(&mut self) -> REGION57_W<'_>
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Bit 25 - Enable protection for region 57. Write '0' has no effect.
pub fn region58(&mut self) -> REGION58_W<'_>
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Bit 26 - Enable protection for region 58. Write '0' has no effect.
pub fn region59(&mut self) -> REGION59_W<'_>
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Bit 27 - Enable protection for region 59. Write '0' has no effect.
pub fn region60(&mut self) -> REGION60_W<'_>
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Bit 28 - Enable protection for region 60. Write '0' has no effect.
pub fn region61(&mut self) -> REGION61_W<'_>
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Bit 29 - Enable protection for region 61. Write '0' has no effect.
pub fn region62(&mut self) -> REGION62_W<'_>
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Bit 30 - Enable protection for region 62. Write '0' has no effect.
pub fn region63(&mut self) -> REGION63_W<'_>
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Bit 31 - Enable protection for region 63. Write '0' has no effect.
impl W<u32, Reg<u32, _DISABLEINDEBUG>>
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pub fn disableindebug(&mut self) -> DISABLEINDEBUG_W<'_>
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Bit 0 - Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode.
impl W<u32, Reg<u32, _CONFIG2>>
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pub fn region64(&mut self) -> REGION64_W<'_>
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Bit 0 - Enable protection for region 64. Write '0' has no effect.
pub fn region65(&mut self) -> REGION65_W<'_>
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Bit 1 - Enable protection for region 65. Write '0' has no effect.
pub fn region66(&mut self) -> REGION66_W<'_>
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Bit 2 - Enable protection for region 66. Write '0' has no effect.
pub fn region67(&mut self) -> REGION67_W<'_>
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Bit 3 - Enable protection for region 67. Write '0' has no effect.
pub fn region68(&mut self) -> REGION68_W<'_>
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Bit 4 - Enable protection for region 68. Write '0' has no effect.
pub fn region69(&mut self) -> REGION69_W<'_>
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Bit 5 - Enable protection for region 69. Write '0' has no effect.
pub fn region70(&mut self) -> REGION70_W<'_>
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Bit 6 - Enable protection for region 70. Write '0' has no effect.
pub fn region71(&mut self) -> REGION71_W<'_>
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Bit 7 - Enable protection for region 71. Write '0' has no effect.
pub fn region72(&mut self) -> REGION72_W<'_>
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Bit 8 - Enable protection for region 72. Write '0' has no effect.
pub fn region73(&mut self) -> REGION73_W<'_>
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Bit 9 - Enable protection for region 73. Write '0' has no effect.
pub fn region74(&mut self) -> REGION74_W<'_>
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Bit 10 - Enable protection for region 74. Write '0' has no effect.
pub fn region75(&mut self) -> REGION75_W<'_>
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Bit 11 - Enable protection for region 75. Write '0' has no effect.
pub fn region76(&mut self) -> REGION76_W<'_>
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Bit 12 - Enable protection for region 76. Write '0' has no effect.
pub fn region77(&mut self) -> REGION77_W<'_>
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Bit 13 - Enable protection for region 77. Write '0' has no effect.
pub fn region78(&mut self) -> REGION78_W<'_>
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Bit 14 - Enable protection for region 78. Write '0' has no effect.
pub fn region79(&mut self) -> REGION79_W<'_>
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Bit 15 - Enable protection for region 79. Write '0' has no effect.
pub fn region80(&mut self) -> REGION80_W<'_>
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Bit 16 - Enable protection for region 80. Write '0' has no effect.
pub fn region81(&mut self) -> REGION81_W<'_>
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Bit 17 - Enable protection for region 81. Write '0' has no effect.
pub fn region82(&mut self) -> REGION82_W<'_>
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Bit 18 - Enable protection for region 82. Write '0' has no effect.
pub fn region83(&mut self) -> REGION83_W<'_>
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Bit 19 - Enable protection for region 83. Write '0' has no effect.
pub fn region84(&mut self) -> REGION84_W<'_>
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Bit 20 - Enable protection for region 84. Write '0' has no effect.
pub fn region85(&mut self) -> REGION85_W<'_>
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Bit 21 - Enable protection for region 85. Write '0' has no effect.
pub fn region86(&mut self) -> REGION86_W<'_>
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Bit 22 - Enable protection for region 86. Write '0' has no effect.
pub fn region87(&mut self) -> REGION87_W<'_>
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Bit 23 - Enable protection for region 87. Write '0' has no effect.
pub fn region88(&mut self) -> REGION88_W<'_>
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Bit 24 - Enable protection for region 88. Write '0' has no effect.
pub fn region89(&mut self) -> REGION89_W<'_>
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Bit 25 - Enable protection for region 89. Write '0' has no effect.
pub fn region90(&mut self) -> REGION90_W<'_>
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Bit 26 - Enable protection for region 90. Write '0' has no effect.
pub fn region91(&mut self) -> REGION91_W<'_>
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Bit 27 - Enable protection for region 91. Write '0' has no effect.
pub fn region92(&mut self) -> REGION92_W<'_>
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Bit 28 - Enable protection for region 92. Write '0' has no effect.
pub fn region93(&mut self) -> REGION93_W<'_>
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Bit 29 - Enable protection for region 93. Write '0' has no effect.
pub fn region94(&mut self) -> REGION94_W<'_>
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Bit 30 - Enable protection for region 94. Write '0' has no effect.
pub fn region95(&mut self) -> REGION95_W<'_>
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Bit 31 - Enable protection for region 95. Write '0' has no effect.
impl W<u32, Reg<u32, _CONFIG3>>
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pub fn region96(&mut self) -> REGION96_W<'_>
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Bit 0 - Enable protection for region 96. Write '0' has no effect.
pub fn region97(&mut self) -> REGION97_W<'_>
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Bit 1 - Enable protection for region 97. Write '0' has no effect.
pub fn region98(&mut self) -> REGION98_W<'_>
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Bit 2 - Enable protection for region 98. Write '0' has no effect.
pub fn region99(&mut self) -> REGION99_W<'_>
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Bit 3 - Enable protection for region 99. Write '0' has no effect.
pub fn region100(&mut self) -> REGION100_W<'_>
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Bit 4 - Enable protection for region 100. Write '0' has no effect.
pub fn region101(&mut self) -> REGION101_W<'_>
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Bit 5 - Enable protection for region 101. Write '0' has no effect.
pub fn region102(&mut self) -> REGION102_W<'_>
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Bit 6 - Enable protection for region 102. Write '0' has no effect.
pub fn region103(&mut self) -> REGION103_W<'_>
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Bit 7 - Enable protection for region 103. Write '0' has no effect.
pub fn region104(&mut self) -> REGION104_W<'_>
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Bit 8 - Enable protection for region 104. Write '0' has no effect.
pub fn region105(&mut self) -> REGION105_W<'_>
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Bit 9 - Enable protection for region 105. Write '0' has no effect.
pub fn region106(&mut self) -> REGION106_W<'_>
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Bit 10 - Enable protection for region 106. Write '0' has no effect.
pub fn region107(&mut self) -> REGION107_W<'_>
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Bit 11 - Enable protection for region 107. Write '0' has no effect.
pub fn region108(&mut self) -> REGION108_W<'_>
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Bit 12 - Enable protection for region 108. Write '0' has no effect.
pub fn region109(&mut self) -> REGION109_W<'_>
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Bit 13 - Enable protection for region 109. Write '0' has no effect.
pub fn region110(&mut self) -> REGION110_W<'_>
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Bit 14 - Enable protection for region 110. Write '0' has no effect.
pub fn region111(&mut self) -> REGION111_W<'_>
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Bit 15 - Enable protection for region 111. Write '0' has no effect.
pub fn region112(&mut self) -> REGION112_W<'_>
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Bit 16 - Enable protection for region 112. Write '0' has no effect.
pub fn region113(&mut self) -> REGION113_W<'_>
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Bit 17 - Enable protection for region 113. Write '0' has no effect.
pub fn region114(&mut self) -> REGION114_W<'_>
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Bit 18 - Enable protection for region 114. Write '0' has no effect.
pub fn region115(&mut self) -> REGION115_W<'_>
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Bit 19 - Enable protection for region 115. Write '0' has no effect.
pub fn region116(&mut self) -> REGION116_W<'_>
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Bit 20 - Enable protection for region 116. Write '0' has no effect.
pub fn region117(&mut self) -> REGION117_W<'_>
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Bit 21 - Enable protection for region 117. Write '0' has no effect.
pub fn region118(&mut self) -> REGION118_W<'_>
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Bit 22 - Enable protection for region 118. Write '0' has no effect.
pub fn region119(&mut self) -> REGION119_W<'_>
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Bit 23 - Enable protection for region 119. Write '0' has no effect.
pub fn region120(&mut self) -> REGION120_W<'_>
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Bit 24 - Enable protection for region 120. Write '0' has no effect.
pub fn region121(&mut self) -> REGION121_W<'_>
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Bit 25 - Enable protection for region 121. Write '0' has no effect.
pub fn region122(&mut self) -> REGION122_W<'_>
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Bit 26 - Enable protection for region 122. Write '0' has no effect.
pub fn region123(&mut self) -> REGION123_W<'_>
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Bit 27 - Enable protection for region 123. Write '0' has no effect.
pub fn region124(&mut self) -> REGION124_W<'_>
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Bit 28 - Enable protection for region 124. Write '0' has no effect.
pub fn region125(&mut self) -> REGION125_W<'_>
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Bit 29 - Enable protection for region 125. Write '0' has no effect.
pub fn region126(&mut self) -> REGION126_W<'_>
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Bit 30 - Enable protection for region 126. Write '0' has no effect.
pub fn region127(&mut self) -> REGION127_W<'_>
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Bit 31 - Enable protection for region 127. Write '0' has no effect.
impl W<u32, Reg<u32, _POWER>>
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pub fn s0power(&mut self) -> S0POWER_W<'_>
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Bit 0 - Keep RAM section S0 ON or OFF in System ON mode.
pub fn s1power(&mut self) -> S1POWER_W<'_>
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Bit 1 - Keep RAM section S1 ON or OFF in System ON mode.
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
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Bit 16 - Keep retention on RAM section S0 when RAM section is in OFF
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
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Bit 17 - Keep retention on RAM section S1 when RAM section is in OFF
impl W<u32, Reg<u32, _POWERSET>>
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pub fn s0power(&mut self) -> S0POWER_W<'_>
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Bit 0 - Keep RAM section S0 of RAM0 on or off in System ON mode
pub fn s1power(&mut self) -> S1POWER_W<'_>
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Bit 1 - Keep RAM section S1 of RAM0 on or off in System ON mode
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
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Bit 16 - Keep retention on RAM section S0 when RAM section is switched off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
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Bit 17 - Keep retention on RAM section S1 when RAM section is switched off
impl W<u32, Reg<u32, _POWERCLR>>
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pub fn s0power(&mut self) -> S0POWER_W<'_>
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Bit 0 - Keep RAM section S0 of RAM0 on or off in System ON mode
pub fn s1power(&mut self) -> S1POWER_W<'_>
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Bit 1 - Keep RAM section S1 of RAM0 on or off in System ON mode
pub fn s0retention(&mut self) -> S0RETENTION_W<'_>
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Bit 16 - Keep retention on RAM section S0 when RAM section is switched off
pub fn s1retention(&mut self) -> S1RETENTION_W<'_>
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Bit 17 - Keep retention on RAM section S1 when RAM section is switched off
impl W<u32, Reg<u32, _INTENSET>>
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pub fn pofwarn(&mut self) -> POFWARN_W<'_>
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Bit 2 - Write '1' to Enable interrupt for POFWARN event
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
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Bit 5 - Write '1' to Enable interrupt for SLEEPENTER event
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
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Bit 6 - Write '1' to Enable interrupt for SLEEPEXIT event
impl W<u32, Reg<u32, _INTENCLR>>
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pub fn pofwarn(&mut self) -> POFWARN_W<'_>
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Bit 2 - Write '1' to Disable interrupt for POFWARN event
pub fn sleepenter(&mut self) -> SLEEPENTER_W<'_>
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Bit 5 - Write '1' to Disable interrupt for SLEEPENTER event
pub fn sleepexit(&mut self) -> SLEEPEXIT_W<'_>
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Bit 6 - Write '1' to Disable interrupt for SLEEPEXIT event
impl W<u32, Reg<u32, _RESETREAS>>
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pub fn resetpin(&mut self) -> RESETPIN_W<'_>
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Bit 0 - Reset from pin-reset detected
pub fn dog(&mut self) -> DOG_W<'_>
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Bit 1 - Reset from watchdog detected
pub fn sreq(&mut self) -> SREQ_W<'_>
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Bit 2 - Reset from soft reset detected
pub fn lockup(&mut self) -> LOCKUP_W<'_>
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Bit 3 - Reset from CPU lock-up detected
pub fn off(&mut self) -> OFF_W<'_>
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Bit 16 - Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
pub fn lpcomp(&mut self) -> LPCOMP_W<'_>
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Bit 17 - Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
pub fn dif(&mut self) -> DIF_W<'_>
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Bit 18 - Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
pub fn nfc(&mut self) -> NFC_W<'_>
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Bit 19 - Reset due to wake up from System OFF mode by NFC field detect
impl W<u32, Reg<u32, _SYSTEMOFF>>
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pub fn systemoff(&mut self) -> SYSTEMOFF_W<'_>
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Bit 0 - Enable System OFF mode
impl W<u32, Reg<u32, _POFCON>>
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pub fn pof(&mut self) -> POF_W<'_>
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Bit 0 - Enable or disable power failure comparator
pub fn threshold(&mut self) -> THRESHOLD_W<'_>
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Bits 1:4 - Power failure comparator threshold setting
impl W<u32, Reg<u32, _GPREGRET>>
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pub fn gpregret(&mut self) -> GPREGRET_W<'_>
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Bits 0:7 - General purpose retention register
impl W<u32, Reg<u32, _GPREGRET2>>
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pub fn gpregret(&mut self) -> GPREGRET_W<'_>
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Bits 0:7 - General purpose retention register
impl W<u32, Reg<u32, _RAMON>>
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pub fn onram0(&mut self) -> ONRAM0_W<'_>
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Bit 0 - Keep RAM block 0 on or off in system ON Mode
pub fn onram1(&mut self) -> ONRAM1_W<'_>
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Bit 1 - Keep RAM block 1 on or off in system ON Mode
pub fn offram0(&mut self) -> OFFRAM0_W<'_>
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Bit 16 - Keep retention on RAM block 0 when RAM block is switched off
pub fn offram1(&mut self) -> OFFRAM1_W<'_>
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Bit 17 - Keep retention on RAM block 1 when RAM block is switched off
impl W<u32, Reg<u32, _RAMONB>>
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pub fn onram2(&mut self) -> ONRAM2_W<'_>
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Bit 0 - Keep RAM block 2 on or off in system ON Mode
pub fn onram3(&mut self) -> ONRAM3_W<'_>
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Bit 1 - Keep RAM block 3 on or off in system ON Mode
pub fn offram2(&mut self) -> OFFRAM2_W<'_>
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Bit 16 - Keep retention on RAM block 2 when RAM block is switched off
pub fn offram3(&mut self) -> OFFRAM3_W<'_>
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Bit 17 - Keep retention on RAM block 3 when RAM block is switched off
impl W<u32, Reg<u32, _DCDCEN>>
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impl W<u32, Reg<u32, _INTENSET>>
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pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
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Bit 0 - Write '1' to Enable interrupt for HFCLKSTARTED event
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
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Bit 1 - Write '1' to Enable interrupt for LFCLKSTARTED event
pub fn done(&mut self) -> DONE_W<'_>
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Bit 3 - Write '1' to Enable interrupt for DONE event
pub fn ctto(&mut self) -> CTTO_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for CTTO event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn hfclkstarted(&mut self) -> HFCLKSTARTED_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for HFCLKSTARTED event
pub fn lfclkstarted(&mut self) -> LFCLKSTARTED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for LFCLKSTARTED event
pub fn done(&mut self) -> DONE_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for DONE event
pub fn ctto(&mut self) -> CTTO_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for CTTO event
impl W<u32, Reg<u32, _LFCLKSRC>>
[src]
pub fn src(&mut self) -> SRC_W<'_>
[src]
Bits 0:1 - Clock source
pub fn bypass(&mut self) -> BYPASS_W<'_>
[src]
Bit 16 - Enable or disable bypass of LFCLK crystal oscillator with external clock source
pub fn external(&mut self) -> EXTERNAL_W<'_>
[src]
Bit 17 - Enable or disable external source for LFCLK
impl W<u32, Reg<u32, _CTIV>>
[src]
pub fn ctiv(&mut self) -> CTIV_W<'_>
[src]
Bits 0:6 - Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
impl W<u32, Reg<u32, _TRACECONFIG>>
[src]
pub fn traceportspeed(&mut self) -> TRACEPORTSPEED_W<'_>
[src]
Bits 0:1 - Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.
pub fn tracemux(&mut self) -> TRACEMUX_W<'_>
[src]
Bits 16:17 - Pin multiplexing of trace signals.
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn ready_start(&mut self) -> READY_START_W<'_>
[src]
Bit 0 - Shortcut between READY event and START task
pub fn end_disable(&mut self) -> END_DISABLE_W<'_>
[src]
Bit 1 - Shortcut between END event and DISABLE task
pub fn disabled_txen(&mut self) -> DISABLED_TXEN_W<'_>
[src]
Bit 2 - Shortcut between DISABLED event and TXEN task
pub fn disabled_rxen(&mut self) -> DISABLED_RXEN_W<'_>
[src]
Bit 3 - Shortcut between DISABLED event and RXEN task
pub fn address_rssistart(&mut self) -> ADDRESS_RSSISTART_W<'_>
[src]
Bit 4 - Shortcut between ADDRESS event and RSSISTART task
pub fn end_start(&mut self) -> END_START_W<'_>
[src]
Bit 5 - Shortcut between END event and START task
pub fn address_bcstart(&mut self) -> ADDRESS_BCSTART_W<'_>
[src]
Bit 6 - Shortcut between ADDRESS event and BCSTART task
pub fn disabled_rssistop(&mut self) -> DISABLED_RSSISTOP_W<'_>
[src]
Bit 8 - Shortcut between DISABLED event and RSSISTOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for READY event
pub fn address(&mut self) -> ADDRESS_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for ADDRESS event
pub fn payload(&mut self) -> PAYLOAD_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for PAYLOAD event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for END event
pub fn disabled(&mut self) -> DISABLED_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for DISABLED event
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for DEVMATCH event
pub fn devmiss(&mut self) -> DEVMISS_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for DEVMISS event
pub fn rssiend(&mut self) -> RSSIEND_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for RSSIEND event
pub fn bcmatch(&mut self) -> BCMATCH_W<'_>
[src]
Bit 10 - Write '1' to Enable interrupt for BCMATCH event
pub fn crcok(&mut self) -> CRCOK_W<'_>
[src]
Bit 12 - Write '1' to Enable interrupt for CRCOK event
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]
Bit 13 - Write '1' to Enable interrupt for CRCERROR event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for READY event
pub fn address(&mut self) -> ADDRESS_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for ADDRESS event
pub fn payload(&mut self) -> PAYLOAD_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for PAYLOAD event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for END event
pub fn disabled(&mut self) -> DISABLED_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for DISABLED event
pub fn devmatch(&mut self) -> DEVMATCH_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for DEVMATCH event
pub fn devmiss(&mut self) -> DEVMISS_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for DEVMISS event
pub fn rssiend(&mut self) -> RSSIEND_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for RSSIEND event
pub fn bcmatch(&mut self) -> BCMATCH_W<'_>
[src]
Bit 10 - Write '1' to Disable interrupt for BCMATCH event
pub fn crcok(&mut self) -> CRCOK_W<'_>
[src]
Bit 12 - Write '1' to Disable interrupt for CRCOK event
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]
Bit 13 - Write '1' to Disable interrupt for CRCERROR event
impl W<u32, Reg<u32, _PACKETPTR>>
[src]
pub fn packetptr(&mut self) -> PACKETPTR_W<'_>
[src]
Bits 0:31 - Packet pointer
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
Bits 0:6 - Radio channel frequency
pub fn map(&mut self) -> MAP_W<'_>
[src]
Bit 8 - Channel map selection.
impl W<u32, Reg<u32, _TXPOWER>>
[src]
impl W<u32, Reg<u32, _MODE>>
[src]
pub fn mode(&mut self) -> MODE_W<'_>
[src]
Bits 0:3 - Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.
impl W<u32, Reg<u32, _PCNF0>>
[src]
pub fn lflen(&mut self) -> LFLEN_W<'_>
[src]
Bits 0:3 - Length on air of LENGTH field in number of bits.
pub fn s0len(&mut self) -> S0LEN_W<'_>
[src]
Bit 8 - Length on air of S0 field in number of bytes.
pub fn s1len(&mut self) -> S1LEN_W<'_>
[src]
Bits 16:19 - Length on air of S1 field in number of bits.
pub fn s1incl(&mut self) -> S1INCL_W<'_>
[src]
Bit 20 - Include or exclude S1 field in RAM
pub fn plen(&mut self) -> PLEN_W<'_>
[src]
Bit 24 - Length of preamble on air. Decision point: TASKS_START task
impl W<u32, Reg<u32, _PCNF1>>
[src]
pub fn maxlen(&mut self) -> MAXLEN_W<'_>
[src]
Bits 0:7 - Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
pub fn statlen(&mut self) -> STATLEN_W<'_>
[src]
Bits 8:15 - Static length in number of bytes
pub fn balen(&mut self) -> BALEN_W<'_>
[src]
Bits 16:18 - Base address length in number of bytes
pub fn endian(&mut self) -> ENDIAN_W<'_>
[src]
Bit 24 - On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.
pub fn whiteen(&mut self) -> WHITEEN_W<'_>
[src]
Bit 25 - Enable or disable packet whitening
impl W<u32, Reg<u32, _BASE0>>
[src]
impl W<u32, Reg<u32, _BASE1>>
[src]
impl W<u32, Reg<u32, _PREFIX0>>
[src]
pub fn ap0(&mut self) -> AP0_W<'_>
[src]
Bits 0:7 - Address prefix 0.
pub fn ap1(&mut self) -> AP1_W<'_>
[src]
Bits 8:15 - Address prefix 1.
pub fn ap2(&mut self) -> AP2_W<'_>
[src]
Bits 16:23 - Address prefix 2.
pub fn ap3(&mut self) -> AP3_W<'_>
[src]
Bits 24:31 - Address prefix 3.
impl W<u32, Reg<u32, _PREFIX1>>
[src]
pub fn ap4(&mut self) -> AP4_W<'_>
[src]
Bits 0:7 - Address prefix 4.
pub fn ap5(&mut self) -> AP5_W<'_>
[src]
Bits 8:15 - Address prefix 5.
pub fn ap6(&mut self) -> AP6_W<'_>
[src]
Bits 16:23 - Address prefix 6.
pub fn ap7(&mut self) -> AP7_W<'_>
[src]
Bits 24:31 - Address prefix 7.
impl W<u32, Reg<u32, _TXADDRESS>>
[src]
pub fn txaddress(&mut self) -> TXADDRESS_W<'_>
[src]
Bits 0:2 - Transmit address select
impl W<u32, Reg<u32, _RXADDRESSES>>
[src]
pub fn addr0(&mut self) -> ADDR0_W<'_>
[src]
Bit 0 - Enable or disable reception on logical address 0.
pub fn addr1(&mut self) -> ADDR1_W<'_>
[src]
Bit 1 - Enable or disable reception on logical address 1.
pub fn addr2(&mut self) -> ADDR2_W<'_>
[src]
Bit 2 - Enable or disable reception on logical address 2.
pub fn addr3(&mut self) -> ADDR3_W<'_>
[src]
Bit 3 - Enable or disable reception on logical address 3.
pub fn addr4(&mut self) -> ADDR4_W<'_>
[src]
Bit 4 - Enable or disable reception on logical address 4.
pub fn addr5(&mut self) -> ADDR5_W<'_>
[src]
Bit 5 - Enable or disable reception on logical address 5.
pub fn addr6(&mut self) -> ADDR6_W<'_>
[src]
Bit 6 - Enable or disable reception on logical address 6.
pub fn addr7(&mut self) -> ADDR7_W<'_>
[src]
Bit 7 - Enable or disable reception on logical address 7.
impl W<u32, Reg<u32, _CRCCNF>>
[src]
pub fn len(&mut self) -> LEN_W<'_>
[src]
Bits 0:1 - CRC length in number of bytes.
pub fn skipaddr(&mut self) -> SKIPADDR_W<'_>
[src]
Bit 8 - Include or exclude packet address field out of CRC calculation.
impl W<u32, Reg<u32, _CRCPOLY>>
[src]
impl W<u32, Reg<u32, _CRCINIT>>
[src]
impl W<u32, Reg<u32, _TIFS>>
[src]
impl W<u32, Reg<u32, _DATAWHITEIV>>
[src]
pub fn datawhiteiv(&mut self) -> DATAWHITEIV_W<'_>
[src]
Bits 0:6 - Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
impl W<u32, Reg<u32, _BCC>>
[src]
impl W<u32, Reg<u32, _DAB>>
[src]
impl W<u32, Reg<u32, _DAP>>
[src]
impl W<u32, Reg<u32, _DACNF>>
[src]
pub fn ena0(&mut self) -> ENA0_W<'_>
[src]
Bit 0 - Enable or disable device address matching using device address 0
pub fn ena1(&mut self) -> ENA1_W<'_>
[src]
Bit 1 - Enable or disable device address matching using device address 1
pub fn ena2(&mut self) -> ENA2_W<'_>
[src]
Bit 2 - Enable or disable device address matching using device address 2
pub fn ena3(&mut self) -> ENA3_W<'_>
[src]
Bit 3 - Enable or disable device address matching using device address 3
pub fn ena4(&mut self) -> ENA4_W<'_>
[src]
Bit 4 - Enable or disable device address matching using device address 4
pub fn ena5(&mut self) -> ENA5_W<'_>
[src]
Bit 5 - Enable or disable device address matching using device address 5
pub fn ena6(&mut self) -> ENA6_W<'_>
[src]
Bit 6 - Enable or disable device address matching using device address 6
pub fn ena7(&mut self) -> ENA7_W<'_>
[src]
Bit 7 - Enable or disable device address matching using device address 7
pub fn txadd0(&mut self) -> TXADD0_W<'_>
[src]
Bit 8 - TxAdd for device address 0
pub fn txadd1(&mut self) -> TXADD1_W<'_>
[src]
Bit 9 - TxAdd for device address 1
pub fn txadd2(&mut self) -> TXADD2_W<'_>
[src]
Bit 10 - TxAdd for device address 2
pub fn txadd3(&mut self) -> TXADD3_W<'_>
[src]
Bit 11 - TxAdd for device address 3
pub fn txadd4(&mut self) -> TXADD4_W<'_>
[src]
Bit 12 - TxAdd for device address 4
pub fn txadd5(&mut self) -> TXADD5_W<'_>
[src]
Bit 13 - TxAdd for device address 5
pub fn txadd6(&mut self) -> TXADD6_W<'_>
[src]
Bit 14 - TxAdd for device address 6
pub fn txadd7(&mut self) -> TXADD7_W<'_>
[src]
Bit 15 - TxAdd for device address 7
impl W<u32, Reg<u32, _MODECNF0>>
[src]
pub fn ru(&mut self) -> RU_W<'_>
[src]
Bit 0 - Radio ramp-up time
pub fn dtx(&mut self) -> DTX_W<'_>
[src]
Bits 8:9 - Default TX value
impl W<u32, Reg<u32, _POWER>>
[src]
pub fn power(&mut self) -> POWER_W<'_>
[src]
Bit 0 - Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
impl W<u32, Reg<u32, _RTS>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _TXD>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _CTS>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _RXD>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn endrx_startrx(&mut self) -> ENDRX_STARTRX_W<'_>
[src]
Bit 5 - Shortcut between ENDRX event and STARTRX task
pub fn endrx_stoprx(&mut self) -> ENDRX_STOPRX_W<'_>
[src]
Bit 6 - Shortcut between ENDRX event and STOPRX task
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn cts(&mut self) -> CTS_W<'_>
[src]
Bit 0 - Enable or disable interrupt for CTS event
pub fn ncts(&mut self) -> NCTS_W<'_>
[src]
Bit 1 - Enable or disable interrupt for NCTS event
pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]
Bit 2 - Enable or disable interrupt for RXDRDY event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Enable or disable interrupt for ENDRX event
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]
Bit 7 - Enable or disable interrupt for TXDRDY event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 8 - Enable or disable interrupt for ENDTX event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Enable or disable interrupt for ERROR event
pub fn rxto(&mut self) -> RXTO_W<'_>
[src]
Bit 17 - Enable or disable interrupt for RXTO event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Enable or disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Enable or disable interrupt for TXSTARTED event
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]
Bit 22 - Enable or disable interrupt for TXSTOPPED event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn cts(&mut self) -> CTS_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for CTS event
pub fn ncts(&mut self) -> NCTS_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for NCTS event
pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for RXDRDY event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for ENDRX event
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for TXDRDY event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 8 - Write '1' to Enable interrupt for ENDTX event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for ERROR event
pub fn rxto(&mut self) -> RXTO_W<'_>
[src]
Bit 17 - Write '1' to Enable interrupt for RXTO event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Write '1' to Enable interrupt for TXSTARTED event
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]
Bit 22 - Write '1' to Enable interrupt for TXSTOPPED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn cts(&mut self) -> CTS_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for CTS event
pub fn ncts(&mut self) -> NCTS_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for NCTS event
pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for RXDRDY event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for ENDRX event
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for TXDRDY event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 8 - Write '1' to Disable interrupt for ENDTX event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for ERROR event
pub fn rxto(&mut self) -> RXTO_W<'_>
[src]
Bit 17 - Write '1' to Disable interrupt for RXTO event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Write '1' to Disable interrupt for TXSTARTED event
pub fn txstopped(&mut self) -> TXSTOPPED_W<'_>
[src]
Bit 22 - Write '1' to Disable interrupt for TXSTOPPED event
impl W<u32, Reg<u32, _ERRORSRC>>
[src]
pub fn overrun(&mut self) -> OVERRUN_W<'_>
[src]
Bit 0 - Overrun error
pub fn parity(&mut self) -> PARITY_W<'_>
[src]
Bit 1 - Parity error
pub fn framing(&mut self) -> FRAMING_W<'_>
[src]
Bit 2 - Framing error occurred
pub fn break_(&mut self) -> BREAK_W<'_>
[src]
Bit 3 - Break condition
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _BAUDRATE>>
[src]
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
[src]
Bits 0:31 - Baud rate
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn hwfc(&mut self) -> HWFC_W<'_>
[src]
Bit 0 - Hardware flow control
pub fn parity(&mut self) -> PARITY_W<'_>
[src]
Bits 1:3 - Parity
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn cts_startrx(&mut self) -> CTS_STARTRX_W<'_>
[src]
Bit 3 - Shortcut between CTS event and STARTRX task
pub fn ncts_stoprx(&mut self) -> NCTS_STOPRX_W<'_>
[src]
Bit 4 - Shortcut between NCTS event and STOPRX task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn cts(&mut self) -> CTS_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for CTS event
pub fn ncts(&mut self) -> NCTS_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for NCTS event
pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for RXDRDY event
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for TXDRDY event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for ERROR event
pub fn rxto(&mut self) -> RXTO_W<'_>
[src]
Bit 17 - Write '1' to Enable interrupt for RXTO event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn cts(&mut self) -> CTS_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for CTS event
pub fn ncts(&mut self) -> NCTS_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for NCTS event
pub fn rxdrdy(&mut self) -> RXDRDY_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for RXDRDY event
pub fn txdrdy(&mut self) -> TXDRDY_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for TXDRDY event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for ERROR event
pub fn rxto(&mut self) -> RXTO_W<'_>
[src]
Bit 17 - Write '1' to Disable interrupt for RXTO event
impl W<u32, Reg<u32, _ERRORSRC>>
[src]
pub fn overrun(&mut self) -> OVERRUN_W<'_>
[src]
Bit 0 - Overrun error
pub fn parity(&mut self) -> PARITY_W<'_>
[src]
Bit 1 - Parity error
pub fn framing(&mut self) -> FRAMING_W<'_>
[src]
Bit 2 - Framing error occurred
pub fn break_(&mut self) -> BREAK_W<'_>
[src]
Bit 3 - Break condition
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _PSELRTS>>
[src]
pub fn pselrts(&mut self) -> PSELRTS_W<'_>
[src]
Bits 0:31 - Pin number configuration for UART RTS signal
impl W<u32, Reg<u32, _PSELTXD>>
[src]
pub fn pseltxd(&mut self) -> PSELTXD_W<'_>
[src]
Bits 0:31 - Pin number configuration for UART TXD signal
impl W<u32, Reg<u32, _PSELCTS>>
[src]
pub fn pselcts(&mut self) -> PSELCTS_W<'_>
[src]
Bits 0:31 - Pin number configuration for UART CTS signal
impl W<u32, Reg<u32, _PSELRXD>>
[src]
pub fn pselrxd(&mut self) -> PSELRXD_W<'_>
[src]
Bits 0:31 - Pin number configuration for UART RXD signal
impl W<u32, Reg<u32, _TXD>>
[src]
impl W<u32, Reg<u32, _BAUDRATE>>
[src]
pub fn baudrate(&mut self) -> BAUDRATE_W<'_>
[src]
Bits 0:31 - Baud rate
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn hwfc(&mut self) -> HWFC_W<'_>
[src]
Bit 0 - Hardware flow control
pub fn parity(&mut self) -> PARITY_W<'_>
[src]
Bits 1:3 - Parity
impl W<u32, Reg<u32, _SCK>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _MOSI>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _MISO>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _LIST>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _LIST>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn end_start(&mut self) -> END_START_W<'_>
[src]
Bit 17 - Shortcut between END event and START task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for STOPPED event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for ENDRX event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for END event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 8 - Write '1' to Enable interrupt for ENDTX event
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for STARTED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for STOPPED event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for ENDRX event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for END event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 8 - Write '1' to Disable interrupt for ENDTX event
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for STARTED event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
Bits 0:31 - SPI master data rate
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn order(&mut self) -> ORDER_W<'_>
[src]
Bit 0 - Bit order
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 1 - Serial clock (SCK) phase
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 2 - Serial clock (SCK) polarity
impl W<u32, Reg<u32, _ORC>>
[src]
pub fn orc(&mut self) -> ORC_W<'_>
[src]
Bits 0:7 - Over-read character. Character clocked out in case and over-read of the TXD buffer.
impl W<u32, Reg<u32, _SCK>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _MISO>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _MOSI>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _CSN>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn end_acquire(&mut self) -> END_ACQUIRE_W<'_>
[src]
Bit 2 - Shortcut between END event and ACQUIRE task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for END event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for ENDRX event
pub fn acquired(&mut self) -> ACQUIRED_W<'_>
[src]
Bit 10 - Write '1' to Enable interrupt for ACQUIRED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for END event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for ENDRX event
pub fn acquired(&mut self) -> ACQUIRED_W<'_>
[src]
Bit 10 - Write '1' to Disable interrupt for ACQUIRED event
impl W<u32, Reg<u32, _STATUS>>
[src]
pub fn overread(&mut self) -> OVERREAD_W<'_>
[src]
Bit 0 - TX buffer over-read detected, and prevented
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
[src]
Bit 1 - RX buffer overflow detected, and prevented
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn order(&mut self) -> ORDER_W<'_>
[src]
Bit 0 - Bit order
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 1 - Serial clock (SCK) phase
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 2 - Serial clock (SCK) polarity
impl W<u32, Reg<u32, _DEF>>
[src]
pub fn def(&mut self) -> DEF_W<'_>
[src]
Bits 0:7 - Default character. Character clocked out in case of an ignored transaction.
impl W<u32, Reg<u32, _ORC>>
[src]
pub fn orc(&mut self) -> ORC_W<'_>
[src]
Bits 0:7 - Over-read character. Character clocked out after an over-read of the transmit buffer.
impl W<u32, Reg<u32, _SCL>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SDA>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _LIST>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _LIST>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn lasttx_startrx(&mut self) -> LASTTX_STARTRX_W<'_>
[src]
Bit 7 - Shortcut between LASTTX event and STARTRX task
pub fn lasttx_suspend(&mut self) -> LASTTX_SUSPEND_W<'_>
[src]
Bit 8 - Shortcut between LASTTX event and SUSPEND task
pub fn lasttx_stop(&mut self) -> LASTTX_STOP_W<'_>
[src]
Bit 9 - Shortcut between LASTTX event and STOP task
pub fn lastrx_starttx(&mut self) -> LASTRX_STARTTX_W<'_>
[src]
Bit 10 - Shortcut between LASTRX event and STARTTX task
pub fn lastrx_stop(&mut self) -> LASTRX_STOP_W<'_>
[src]
Bit 12 - Shortcut between LASTRX event and STOP task
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Enable or disable interrupt for STOPPED event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Enable or disable interrupt for ERROR event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
Bit 18 - Enable or disable interrupt for SUSPENDED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Enable or disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Enable or disable interrupt for TXSTARTED event
pub fn lastrx(&mut self) -> LASTRX_W<'_>
[src]
Bit 23 - Enable or disable interrupt for LASTRX event
pub fn lasttx(&mut self) -> LASTTX_W<'_>
[src]
Bit 24 - Enable or disable interrupt for LASTTX event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for STOPPED event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for ERROR event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for SUSPENDED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Write '1' to Enable interrupt for TXSTARTED event
pub fn lastrx(&mut self) -> LASTRX_W<'_>
[src]
Bit 23 - Write '1' to Enable interrupt for LASTRX event
pub fn lasttx(&mut self) -> LASTTX_W<'_>
[src]
Bit 24 - Write '1' to Enable interrupt for LASTTX event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for STOPPED event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for ERROR event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for SUSPENDED event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Write '1' to Disable interrupt for TXSTARTED event
pub fn lastrx(&mut self) -> LASTRX_W<'_>
[src]
Bit 23 - Write '1' to Disable interrupt for LASTRX event
pub fn lasttx(&mut self) -> LASTTX_W<'_>
[src]
Bit 24 - Write '1' to Disable interrupt for LASTTX event
impl W<u32, Reg<u32, _ERRORSRC>>
[src]
pub fn overrun(&mut self) -> OVERRUN_W<'_>
[src]
Bit 0 - Overrun error
pub fn anack(&mut self) -> ANACK_W<'_>
[src]
Bit 1 - NACK received after sending the address (write '1' to clear)
pub fn dnack(&mut self) -> DNACK_W<'_>
[src]
Bit 2 - NACK received after sending a data byte (write '1' to clear)
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
Bits 0:31 - TWI master clock frequency
impl W<u32, Reg<u32, _ADDRESS>>
[src]
impl W<u32, Reg<u32, _SCL>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SDA>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn write_suspend(&mut self) -> WRITE_SUSPEND_W<'_>
[src]
Bit 13 - Shortcut between WRITE event and SUSPEND task
pub fn read_suspend(&mut self) -> READ_SUSPEND_W<'_>
[src]
Bit 14 - Shortcut between READ event and SUSPEND task
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Enable or disable interrupt for STOPPED event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Enable or disable interrupt for ERROR event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Enable or disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Enable or disable interrupt for TXSTARTED event
pub fn write(&mut self) -> WRITE_W<'_>
[src]
Bit 25 - Enable or disable interrupt for WRITE event
pub fn read(&mut self) -> READ_W<'_>
[src]
Bit 26 - Enable or disable interrupt for READ event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for STOPPED event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for ERROR event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Write '1' to Enable interrupt for TXSTARTED event
pub fn write(&mut self) -> WRITE_W<'_>
[src]
Bit 25 - Write '1' to Enable interrupt for WRITE event
pub fn read(&mut self) -> READ_W<'_>
[src]
Bit 26 - Write '1' to Enable interrupt for READ event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for STOPPED event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for ERROR event
pub fn rxstarted(&mut self) -> RXSTARTED_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for RXSTARTED event
pub fn txstarted(&mut self) -> TXSTARTED_W<'_>
[src]
Bit 20 - Write '1' to Disable interrupt for TXSTARTED event
pub fn write(&mut self) -> WRITE_W<'_>
[src]
Bit 25 - Write '1' to Disable interrupt for WRITE event
pub fn read(&mut self) -> READ_W<'_>
[src]
Bit 26 - Write '1' to Disable interrupt for READ event
impl W<u32, Reg<u32, _ERRORSRC>>
[src]
pub fn overflow(&mut self) -> OVERFLOW_W<'_>
[src]
Bit 0 - RX buffer overflow detected, and prevented
pub fn dnack(&mut self) -> DNACK_W<'_>
[src]
Bit 2 - NACK sent after receiving a data byte
pub fn overread(&mut self) -> OVERREAD_W<'_>
[src]
Bit 3 - TX buffer over-read detected, and prevented
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _ADDRESS>>
[src]
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn address0(&mut self) -> ADDRESS0_W<'_>
[src]
Bit 0 - Enable or disable address matching on ADDRESS[0]
pub fn address1(&mut self) -> ADDRESS1_W<'_>
[src]
Bit 1 - Enable or disable address matching on ADDRESS[1]
impl W<u32, Reg<u32, _ORC>>
[src]
pub fn orc(&mut self) -> ORC_W<'_>
[src]
Bits 0:7 - Over-read character. Character sent out in case of an over-read of the transmit buffer.
impl W<u32, Reg<u32, _SCK>>
[src]
pub fn pselsck(&mut self) -> PSELSCK_W<'_>
[src]
Bits 0:31 - Pin number configuration for SPI SCK signal
impl W<u32, Reg<u32, _MOSI>>
[src]
pub fn pselmosi(&mut self) -> PSELMOSI_W<'_>
[src]
Bits 0:31 - Pin number configuration for SPI MOSI signal
impl W<u32, Reg<u32, _MISO>>
[src]
pub fn pselmiso(&mut self) -> PSELMISO_W<'_>
[src]
Bits 0:31 - Pin number configuration for SPI MISO signal
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _TXD>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
Bits 0:31 - SPI master data rate
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn order(&mut self) -> ORDER_W<'_>
[src]
Bit 0 - Bit order
pub fn cpha(&mut self) -> CPHA_W<'_>
[src]
Bit 1 - Serial clock (SCK) phase
pub fn cpol(&mut self) -> CPOL_W<'_>
[src]
Bit 2 - Serial clock (SCK) polarity
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn bb_suspend(&mut self) -> BB_SUSPEND_W<'_>
[src]
Bit 0 - Shortcut between BB event and SUSPEND task
pub fn bb_stop(&mut self) -> BB_STOP_W<'_>
[src]
Bit 1 - Shortcut between BB event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for STOPPED event
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for RXDREADY event
pub fn txdsent(&mut self) -> TXDSENT_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for TXDSENT event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for ERROR event
pub fn bb(&mut self) -> BB_W<'_>
[src]
Bit 14 - Write '1' to Enable interrupt for BB event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for SUSPENDED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for STOPPED event
pub fn rxdready(&mut self) -> RXDREADY_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for RXDREADY event
pub fn txdsent(&mut self) -> TXDSENT_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for TXDSENT event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for ERROR event
pub fn bb(&mut self) -> BB_W<'_>
[src]
Bit 14 - Write '1' to Disable interrupt for BB event
pub fn suspended(&mut self) -> SUSPENDED_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for SUSPENDED event
impl W<u32, Reg<u32, _ERRORSRC>>
[src]
pub fn overrun(&mut self) -> OVERRUN_W<'_>
[src]
Bit 0 - Overrun error
pub fn anack(&mut self) -> ANACK_W<'_>
[src]
Bit 1 - NACK received after sending the address (write '1' to clear)
pub fn dnack(&mut self) -> DNACK_W<'_>
[src]
Bit 2 - NACK received after sending a data byte (write '1' to clear)
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _PSELSCL>>
[src]
pub fn pselscl(&mut self) -> PSELSCL_W<'_>
[src]
Bits 0:31 - Pin number configuration for TWI SCL signal
impl W<u32, Reg<u32, _PSELSDA>>
[src]
pub fn pselsda(&mut self) -> PSELSDA_W<'_>
[src]
Bits 0:31 - Pin number configuration for TWI SDA signal
impl W<u32, Reg<u32, _TXD>>
[src]
impl W<u32, Reg<u32, _FREQUENCY>>
[src]
pub fn frequency(&mut self) -> FREQUENCY_W<'_>
[src]
Bits 0:31 - TWI master clock frequency
impl W<u32, Reg<u32, _ADDRESS>>
[src]
impl W<u32, Reg<u32, _RX>>
[src]
pub fn crcerror(&mut self) -> CRCERROR_W<'_>
[src]
Bit 0 - No valid End of Frame detected
pub fn paritystatus(&mut self) -> PARITYSTATUS_W<'_>
[src]
Bit 2 - Parity status of received frame
pub fn overrun(&mut self) -> OVERRUN_W<'_>
[src]
Bit 3 - Overrun detected
impl W<u32, Reg<u32, _FRAMECONFIG>>
[src]
pub fn parity(&mut self) -> PARITY_W<'_>
[src]
Bit 0 - Adding parity or not in the frame
pub fn discardmode(&mut self) -> DISCARDMODE_W<'_>
[src]
Bit 1 - Discarding unused bits in start or at end of a Frame
pub fn sof(&mut self) -> SOF_W<'_>
[src]
Bit 2 - Adding SoF or not in TX frames
pub fn crcmodetx(&mut self) -> CRCMODETX_W<'_>
[src]
Bit 4 - CRC mode for outgoing frames
impl W<u32, Reg<u32, _AMOUNT>>
[src]
pub fn txdatabits(&mut self) -> TXDATABITS_W<'_>
[src]
Bits 0:2 - Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit).
pub fn txdatabytes(&mut self) -> TXDATABYTES_W<'_>
[src]
Bits 3:11 - Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing
impl W<u32, Reg<u32, _FRAMECONFIG>>
[src]
pub fn parity(&mut self) -> PARITY_W<'_>
[src]
Bit 0 - Parity expected or not in RX frame
pub fn sof(&mut self) -> SOF_W<'_>
[src]
Bit 2 - SoF expected or not in RX frames
pub fn crcmoderx(&mut self) -> CRCMODERX_W<'_>
[src]
Bit 4 - CRC mode for incoming frames
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn fielddetected_activate(&mut self) -> FIELDDETECTED_ACTIVATE_W<'_>
[src]
Bit 0 - Shortcut between FIELDDETECTED event and ACTIVATE task
pub fn fieldlost_sense(&mut self) -> FIELDLOST_SENSE_W<'_>
[src]
Bit 1 - Shortcut between FIELDLOST event and SENSE task
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Enable or disable interrupt for READY event
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]
Bit 1 - Enable or disable interrupt for FIELDDETECTED event
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]
Bit 2 - Enable or disable interrupt for FIELDLOST event
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]
Bit 3 - Enable or disable interrupt for TXFRAMESTART event
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]
Bit 4 - Enable or disable interrupt for TXFRAMEEND event
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]
Bit 5 - Enable or disable interrupt for RXFRAMESTART event
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]
Bit 6 - Enable or disable interrupt for RXFRAMEEND event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 7 - Enable or disable interrupt for ERROR event
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]
Bit 10 - Enable or disable interrupt for RXERROR event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 11 - Enable or disable interrupt for ENDRX event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 12 - Enable or disable interrupt for ENDTX event
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]
Bit 14 - Enable or disable interrupt for AUTOCOLRESSTARTED event
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]
Bit 18 - Enable or disable interrupt for COLLISION event
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]
Bit 19 - Enable or disable interrupt for SELECTED event
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 20 - Enable or disable interrupt for STARTED event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for READY event
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for FIELDDETECTED event
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for FIELDLOST event
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for TXFRAMESTART event
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for TXFRAMEEND event
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for RXFRAMESTART event
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for RXFRAMEEND event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for ERROR event
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]
Bit 10 - Write '1' to Enable interrupt for RXERROR event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 11 - Write '1' to Enable interrupt for ENDRX event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 12 - Write '1' to Enable interrupt for ENDTX event
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]
Bit 14 - Write '1' to Enable interrupt for AUTOCOLRESSTARTED event
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for COLLISION event
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for SELECTED event
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 20 - Write '1' to Enable interrupt for STARTED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for READY event
pub fn fielddetected(&mut self) -> FIELDDETECTED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for FIELDDETECTED event
pub fn fieldlost(&mut self) -> FIELDLOST_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for FIELDLOST event
pub fn txframestart(&mut self) -> TXFRAMESTART_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for TXFRAMESTART event
pub fn txframeend(&mut self) -> TXFRAMEEND_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for TXFRAMEEND event
pub fn rxframestart(&mut self) -> RXFRAMESTART_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for RXFRAMESTART event
pub fn rxframeend(&mut self) -> RXFRAMEEND_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for RXFRAMEEND event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for ERROR event
pub fn rxerror(&mut self) -> RXERROR_W<'_>
[src]
Bit 10 - Write '1' to Disable interrupt for RXERROR event
pub fn endrx(&mut self) -> ENDRX_W<'_>
[src]
Bit 11 - Write '1' to Disable interrupt for ENDRX event
pub fn endtx(&mut self) -> ENDTX_W<'_>
[src]
Bit 12 - Write '1' to Disable interrupt for ENDTX event
pub fn autocolresstarted(&mut self) -> AUTOCOLRESSTARTED_W<'_>
[src]
Bit 14 - Write '1' to Disable interrupt for AUTOCOLRESSTARTED event
pub fn collision(&mut self) -> COLLISION_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for COLLISION event
pub fn selected(&mut self) -> SELECTED_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for SELECTED event
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 20 - Write '1' to Disable interrupt for STARTED event
impl W<u32, Reg<u32, _ERRORSTATUS>>
[src]
pub fn framedelaytimeout(&mut self) -> FRAMEDELAYTIMEOUT_W<'_>
[src]
Bit 0 - No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
pub fn nfcfieldtoostrong(&mut self) -> NFCFIELDTOOSTRONG_W<'_>
[src]
Bit 2 - Field level is too high at max load resistance
pub fn nfcfieldtooweak(&mut self) -> NFCFIELDTOOWEAK_W<'_>
[src]
Bit 3 - Field level is too low at min load resistance
impl W<u32, Reg<u32, _FRAMEDELAYMIN>>
[src]
pub fn framedelaymin(&mut self) -> FRAMEDELAYMIN_W<'_>
[src]
Bits 0:15 - Minimum frame delay in number of 13.56 MHz clocks
impl W<u32, Reg<u32, _FRAMEDELAYMAX>>
[src]
pub fn framedelaymax(&mut self) -> FRAMEDELAYMAX_W<'_>
[src]
Bits 0:15 - Maximum frame delay in number of 13.56 MHz clocks
impl W<u32, Reg<u32, _FRAMEDELAYMODE>>
[src]
pub fn framedelaymode(&mut self) -> FRAMEDELAYMODE_W<'_>
[src]
Bits 0:1 - Configuration register for the Frame Delay Timer
impl W<u32, Reg<u32, _PACKETPTR>>
[src]
pub fn ptr(&mut self) -> PTR_W<'_>
[src]
Bits 0:31 - Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address.
impl W<u32, Reg<u32, _MAXLEN>>
[src]
pub fn maxlen(&mut self) -> MAXLEN_W<'_>
[src]
Bits 0:8 - Size of allocated for TXD and RXD data storage buffer in Data RAM
impl W<u32, Reg<u32, _NFCID1_LAST>>
[src]
pub fn nfcid1_z(&mut self) -> NFCID1_Z_W<'_>
[src]
Bits 0:7 - NFCID1 byte Z (very last byte sent)
pub fn nfcid1_y(&mut self) -> NFCID1_Y_W<'_>
[src]
Bits 8:15 - NFCID1 byte Y
pub fn nfcid1_x(&mut self) -> NFCID1_X_W<'_>
[src]
Bits 16:23 - NFCID1 byte X
pub fn nfcid1_w(&mut self) -> NFCID1_W_W<'_>
[src]
Bits 24:31 - NFCID1 byte W
impl W<u32, Reg<u32, _NFCID1_2ND_LAST>>
[src]
pub fn nfcid1_v(&mut self) -> NFCID1_V_W<'_>
[src]
Bits 0:7 - NFCID1 byte V
pub fn nfcid1_u(&mut self) -> NFCID1_U_W<'_>
[src]
Bits 8:15 - NFCID1 byte U
pub fn nfcid1_t(&mut self) -> NFCID1_T_W<'_>
[src]
Bits 16:23 - NFCID1 byte T
impl W<u32, Reg<u32, _NFCID1_3RD_LAST>>
[src]
pub fn nfcid1_s(&mut self) -> NFCID1_S_W<'_>
[src]
Bits 0:7 - NFCID1 byte S
pub fn nfcid1_r(&mut self) -> NFCID1_R_W<'_>
[src]
Bits 8:15 - NFCID1 byte R
pub fn nfcid1_q(&mut self) -> NFCID1_Q_W<'_>
[src]
Bits 16:23 - NFCID1 byte Q
impl W<u32, Reg<u32, _SENSRES>>
[src]
pub fn bitframesdd(&mut self) -> BITFRAMESDD_W<'_>
[src]
Bits 0:4 - Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
pub fn rfu5(&mut self) -> RFU5_W<'_>
[src]
Bit 5 - Reserved for future use. Shall be 0.
pub fn nfcidsize(&mut self) -> NFCIDSIZE_W<'_>
[src]
Bits 6:7 - NFCID1 size. This value is used by the Auto collision resolution engine.
pub fn platfconfig(&mut self) -> PLATFCONFIG_W<'_>
[src]
Bits 8:11 - Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
pub fn rfu74(&mut self) -> RFU74_W<'_>
[src]
Bits 12:15 - Reserved for future use. Shall be 0.
impl W<u32, Reg<u32, _SELRES>>
[src]
pub fn rfu10(&mut self) -> RFU10_W<'_>
[src]
Bits 0:1 - Reserved for future use. Shall be 0.
pub fn cascade(&mut self) -> CASCADE_W<'_>
[src]
Bit 2 - Cascade bit (controlled by hardware, write has no effect)
pub fn rfu43(&mut self) -> RFU43_W<'_>
[src]
Bits 3:4 - Reserved for future use. Shall be 0.
pub fn protocol(&mut self) -> PROTOCOL_W<'_>
[src]
Bits 5:6 - Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
pub fn rfu7(&mut self) -> RFU7_W<'_>
[src]
Bit 7 - Reserved for future use. Shall be 0.
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn in0(&mut self) -> IN0_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for IN[0] event
pub fn in1(&mut self) -> IN1_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for IN[1] event
pub fn in2(&mut self) -> IN2_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for IN[2] event
pub fn in3(&mut self) -> IN3_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for IN[3] event
pub fn in4(&mut self) -> IN4_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for IN[4] event
pub fn in5(&mut self) -> IN5_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for IN[5] event
pub fn in6(&mut self) -> IN6_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for IN[6] event
pub fn in7(&mut self) -> IN7_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for IN[7] event
pub fn port(&mut self) -> PORT_W<'_>
[src]
Bit 31 - Write '1' to Enable interrupt for PORT event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn in0(&mut self) -> IN0_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for IN[0] event
pub fn in1(&mut self) -> IN1_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for IN[1] event
pub fn in2(&mut self) -> IN2_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for IN[2] event
pub fn in3(&mut self) -> IN3_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for IN[3] event
pub fn in4(&mut self) -> IN4_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for IN[4] event
pub fn in5(&mut self) -> IN5_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for IN[5] event
pub fn in6(&mut self) -> IN6_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for IN[6] event
pub fn in7(&mut self) -> IN7_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for IN[7] event
pub fn port(&mut self) -> PORT_W<'_>
[src]
Bit 31 - Write '1' to Disable interrupt for PORT event
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn mode(&mut self) -> MODE_W<'_>
[src]
Bits 0:1 - Mode
pub fn psel(&mut self) -> PSEL_W<'_>
[src]
Bits 8:12 - GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
pub fn polarity(&mut self) -> POLARITY_W<'_>
[src]
Bits 16:17 - When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
pub fn outinit(&mut self) -> OUTINIT_W<'_>
[src]
Bit 20 - When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
impl W<u32, Reg<u32, _PSELP>>
[src]
impl W<u32, Reg<u32, _PSELN>>
[src]
pub fn pseln(&mut self) -> PSELN_W<'_>
[src]
Bits 0:4 - Analog negative input, enables differential channel
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn resp(&mut self) -> RESP_W<'_>
[src]
Bits 0:1 - Positive channel resistor control
pub fn resn(&mut self) -> RESN_W<'_>
[src]
Bits 4:5 - Negative channel resistor control
pub fn gain(&mut self) -> GAIN_W<'_>
[src]
Bits 8:10 - Gain control
pub fn refsel(&mut self) -> REFSEL_W<'_>
[src]
Bit 12 - Reference control
pub fn tacq(&mut self) -> TACQ_W<'_>
[src]
Bits 16:18 - Acquisition time, the time the ADC uses to sample the input voltage
pub fn mode(&mut self) -> MODE_W<'_>
[src]
Bit 20 - Enable differential mode
pub fn burst(&mut self) -> BURST_W<'_>
[src]
Bit 24 - Enable burst mode
impl W<u32, Reg<u32, _LIMIT>>
[src]
pub fn low(&mut self) -> LOW_W<'_>
[src]
Bits 0:15 - Low level limit
pub fn high(&mut self) -> HIGH_W<'_>
[src]
Bits 16:31 - High level limit
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _MAXCNT>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 0 - Enable or disable interrupt for STARTED event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 1 - Enable or disable interrupt for END event
pub fn done(&mut self) -> DONE_W<'_>
[src]
Bit 2 - Enable or disable interrupt for DONE event
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]
Bit 3 - Enable or disable interrupt for RESULTDONE event
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]
Bit 4 - Enable or disable interrupt for CALIBRATEDONE event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 5 - Enable or disable interrupt for STOPPED event
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]
Bit 6 - Enable or disable interrupt for CH[0].LIMITH event
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]
Bit 7 - Enable or disable interrupt for CH[0].LIMITL event
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]
Bit 8 - Enable or disable interrupt for CH[1].LIMITH event
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]
Bit 9 - Enable or disable interrupt for CH[1].LIMITL event
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]
Bit 10 - Enable or disable interrupt for CH[2].LIMITH event
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]
Bit 11 - Enable or disable interrupt for CH[2].LIMITL event
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]
Bit 12 - Enable or disable interrupt for CH[3].LIMITH event
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]
Bit 13 - Enable or disable interrupt for CH[3].LIMITL event
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]
Bit 14 - Enable or disable interrupt for CH[4].LIMITH event
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]
Bit 15 - Enable or disable interrupt for CH[4].LIMITL event
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]
Bit 16 - Enable or disable interrupt for CH[5].LIMITH event
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]
Bit 17 - Enable or disable interrupt for CH[5].LIMITL event
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]
Bit 18 - Enable or disable interrupt for CH[6].LIMITH event
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]
Bit 19 - Enable or disable interrupt for CH[6].LIMITL event
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]
Bit 20 - Enable or disable interrupt for CH[7].LIMITH event
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]
Bit 21 - Enable or disable interrupt for CH[7].LIMITL event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for STARTED event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for END event
pub fn done(&mut self) -> DONE_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for DONE event
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for RESULTDONE event
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for CALIBRATEDONE event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for STOPPED event
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for CH[0].LIMITH event
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for CH[0].LIMITL event
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]
Bit 8 - Write '1' to Enable interrupt for CH[1].LIMITH event
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for CH[1].LIMITL event
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]
Bit 10 - Write '1' to Enable interrupt for CH[2].LIMITH event
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]
Bit 11 - Write '1' to Enable interrupt for CH[2].LIMITL event
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]
Bit 12 - Write '1' to Enable interrupt for CH[3].LIMITH event
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]
Bit 13 - Write '1' to Enable interrupt for CH[3].LIMITL event
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]
Bit 14 - Write '1' to Enable interrupt for CH[4].LIMITH event
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]
Bit 15 - Write '1' to Enable interrupt for CH[4].LIMITL event
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]
Bit 16 - Write '1' to Enable interrupt for CH[5].LIMITH event
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]
Bit 17 - Write '1' to Enable interrupt for CH[5].LIMITL event
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for CH[6].LIMITH event
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for CH[6].LIMITL event
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]
Bit 20 - Write '1' to Enable interrupt for CH[7].LIMITH event
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]
Bit 21 - Write '1' to Enable interrupt for CH[7].LIMITL event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for STARTED event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for END event
pub fn done(&mut self) -> DONE_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for DONE event
pub fn resultdone(&mut self) -> RESULTDONE_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for RESULTDONE event
pub fn calibratedone(&mut self) -> CALIBRATEDONE_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for CALIBRATEDONE event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for STOPPED event
pub fn ch0limith(&mut self) -> CH0LIMITH_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for CH[0].LIMITH event
pub fn ch0limitl(&mut self) -> CH0LIMITL_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for CH[0].LIMITL event
pub fn ch1limith(&mut self) -> CH1LIMITH_W<'_>
[src]
Bit 8 - Write '1' to Disable interrupt for CH[1].LIMITH event
pub fn ch1limitl(&mut self) -> CH1LIMITL_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for CH[1].LIMITL event
pub fn ch2limith(&mut self) -> CH2LIMITH_W<'_>
[src]
Bit 10 - Write '1' to Disable interrupt for CH[2].LIMITH event
pub fn ch2limitl(&mut self) -> CH2LIMITL_W<'_>
[src]
Bit 11 - Write '1' to Disable interrupt for CH[2].LIMITL event
pub fn ch3limith(&mut self) -> CH3LIMITH_W<'_>
[src]
Bit 12 - Write '1' to Disable interrupt for CH[3].LIMITH event
pub fn ch3limitl(&mut self) -> CH3LIMITL_W<'_>
[src]
Bit 13 - Write '1' to Disable interrupt for CH[3].LIMITL event
pub fn ch4limith(&mut self) -> CH4LIMITH_W<'_>
[src]
Bit 14 - Write '1' to Disable interrupt for CH[4].LIMITH event
pub fn ch4limitl(&mut self) -> CH4LIMITL_W<'_>
[src]
Bit 15 - Write '1' to Disable interrupt for CH[4].LIMITL event
pub fn ch5limith(&mut self) -> CH5LIMITH_W<'_>
[src]
Bit 16 - Write '1' to Disable interrupt for CH[5].LIMITH event
pub fn ch5limitl(&mut self) -> CH5LIMITL_W<'_>
[src]
Bit 17 - Write '1' to Disable interrupt for CH[5].LIMITL event
pub fn ch6limith(&mut self) -> CH6LIMITH_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for CH[6].LIMITH event
pub fn ch6limitl(&mut self) -> CH6LIMITL_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for CH[6].LIMITL event
pub fn ch7limith(&mut self) -> CH7LIMITH_W<'_>
[src]
Bit 20 - Write '1' to Disable interrupt for CH[7].LIMITH event
pub fn ch7limitl(&mut self) -> CH7LIMITL_W<'_>
[src]
Bit 21 - Write '1' to Disable interrupt for CH[7].LIMITL event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _RESOLUTION>>
[src]
impl W<u32, Reg<u32, _OVERSAMPLE>>
[src]
pub fn oversample(&mut self) -> OVERSAMPLE_W<'_>
[src]
Bits 0:3 - Oversample control
impl W<u32, Reg<u32, _SAMPLERATE>>
[src]
pub fn cc(&mut self) -> CC_W<'_>
[src]
Bits 0:10 - Capture and compare value. Sample rate is 16 MHz/CC
pub fn mode(&mut self) -> MODE_W<'_>
[src]
Bit 12 - Select mode for sample rate control
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
[src]
Bit 0 - Shortcut between COMPARE[0] event and CLEAR task
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
[src]
Bit 1 - Shortcut between COMPARE[1] event and CLEAR task
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
[src]
Bit 2 - Shortcut between COMPARE[2] event and CLEAR task
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
[src]
Bit 3 - Shortcut between COMPARE[3] event and CLEAR task
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
[src]
Bit 8 - Shortcut between COMPARE[0] event and STOP task
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
[src]
Bit 9 - Shortcut between COMPARE[1] event and STOP task
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
[src]
Bit 10 - Shortcut between COMPARE[2] event and STOP task
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
[src]
Bit 11 - Shortcut between COMPARE[3] event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Enable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Enable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Disable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Disable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _MODE>>
[src]
impl W<u32, Reg<u32, _BITMODE>>
[src]
impl W<u32, Reg<u32, _PRESCALER>>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
Bits 0:3 - Prescaler value
impl W<u32, Reg<u32, _CC>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn tick(&mut self) -> TICK_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for TICK event
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Enable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Enable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn tick(&mut self) -> TICK_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for TICK event
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Disable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Disable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for COMPARE[3] event
impl W<u32, Reg<u32, _EVTEN>>
[src]
pub fn tick(&mut self) -> TICK_W<'_>
[src]
Bit 0 - Enable or disable event routing for TICK event
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
Bit 1 - Enable or disable event routing for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Enable or disable event routing for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Enable or disable event routing for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Enable or disable event routing for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Enable or disable event routing for COMPARE[3] event
impl W<u32, Reg<u32, _EVTENSET>>
[src]
pub fn tick(&mut self) -> TICK_W<'_>
[src]
Bit 0 - Write '1' to Enable event routing for TICK event
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
Bit 1 - Write '1' to Enable event routing for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Enable event routing for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Enable event routing for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Enable event routing for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Enable event routing for COMPARE[3] event
impl W<u32, Reg<u32, _EVTENCLR>>
[src]
pub fn tick(&mut self) -> TICK_W<'_>
[src]
Bit 0 - Write '1' to Disable event routing for TICK event
pub fn ovrflw(&mut self) -> OVRFLW_W<'_>
[src]
Bit 1 - Write '1' to Disable event routing for OVRFLW event
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Disable event routing for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Disable event routing for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Disable event routing for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Disable event routing for COMPARE[3] event
impl W<u32, Reg<u32, _PRESCALER>>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
Bits 0:11 - Prescaler value
impl W<u32, Reg<u32, _CC>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn datardy(&mut self) -> DATARDY_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for DATARDY event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn datardy(&mut self) -> DATARDY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for DATARDY event
impl W<u32, Reg<u32, _A0>>
[src]
impl W<u32, Reg<u32, _A1>>
[src]
impl W<u32, Reg<u32, _A2>>
[src]
impl W<u32, Reg<u32, _A3>>
[src]
impl W<u32, Reg<u32, _A4>>
[src]
impl W<u32, Reg<u32, _A5>>
[src]
impl W<u32, Reg<u32, _B0>>
[src]
impl W<u32, Reg<u32, _B1>>
[src]
impl W<u32, Reg<u32, _B2>>
[src]
impl W<u32, Reg<u32, _B3>>
[src]
impl W<u32, Reg<u32, _B4>>
[src]
impl W<u32, Reg<u32, _B5>>
[src]
impl W<u32, Reg<u32, _T0>>
[src]
impl W<u32, Reg<u32, _T1>>
[src]
impl W<u32, Reg<u32, _T2>>
[src]
impl W<u32, Reg<u32, _T3>>
[src]
impl W<u32, Reg<u32, _T4>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn valrdy_stop(&mut self) -> VALRDY_STOP_W<'_>
[src]
Bit 0 - Shortcut between VALRDY event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn valrdy(&mut self) -> VALRDY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for VALRDY event
impl W<u32, Reg<u32, _CONFIG>>
[src]
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn endecb(&mut self) -> ENDECB_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for ENDECB event
pub fn errorecb(&mut self) -> ERRORECB_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for ERRORECB event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn endecb(&mut self) -> ENDECB_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for ENDECB event
pub fn errorecb(&mut self) -> ERRORECB_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for ERRORECB event
impl W<u32, Reg<u32, _ECBDATAPTR>>
[src]
pub fn ecbdataptr(&mut self) -> ECBDATAPTR_W<'_>
[src]
Bits 0:31 - Pointer to the ECB data structure (see Table 1 ECB data structure overview)
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn endksgen_crypt(&mut self) -> ENDKSGEN_CRYPT_W<'_>
[src]
Bit 0 - Shortcut between ENDKSGEN event and CRYPT task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for ENDKSGEN event
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for ENDCRYPT event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for ERROR event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn endksgen(&mut self) -> ENDKSGEN_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for ENDKSGEN event
pub fn endcrypt(&mut self) -> ENDCRYPT_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for ENDCRYPT event
pub fn error(&mut self) -> ERROR_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for ERROR event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _MODE>>
[src]
pub fn mode(&mut self) -> MODE_W<'_>
[src]
Bit 0 - The mode of operation to be used
pub fn datarate(&mut self) -> DATARATE_W<'_>
[src]
Bit 16 - Data rate that the CCM shall run in synch with
pub fn length(&mut self) -> LENGTH_W<'_>
[src]
Bit 24 - Packet length configuration
impl W<u32, Reg<u32, _CNFPTR>>
[src]
pub fn cnfptr(&mut self) -> CNFPTR_W<'_>
[src]
Bits 0:31 - Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
impl W<u32, Reg<u32, _INPTR>>
[src]
impl W<u32, Reg<u32, _OUTPTR>>
[src]
impl W<u32, Reg<u32, _SCRATCHPTR>>
[src]
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
[src]
Bits 0:31 - Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for END event
pub fn resolved(&mut self) -> RESOLVED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for RESOLVED event
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for NOTRESOLVED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for END event
pub fn resolved(&mut self) -> RESOLVED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for RESOLVED event
pub fn notresolved(&mut self) -> NOTRESOLVED_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for NOTRESOLVED event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _NIRK>>
[src]
pub fn nirk(&mut self) -> NIRK_W<'_>
[src]
Bits 0:4 - Number of Identity root keys available in the IRK data structure
impl W<u32, Reg<u32, _IRKPTR>>
[src]
impl W<u32, Reg<u32, _ADDRPTR>>
[src]
pub fn addrptr(&mut self) -> ADDRPTR_W<'_>
[src]
Bits 0:31 - Pointer to the resolvable address (6-bytes)
impl W<u32, Reg<u32, _SCRATCHPTR>>
[src]
pub fn scratchptr(&mut self) -> SCRATCHPTR_W<'_>
[src]
Bits 0:31 - Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn timeout(&mut self) -> TIMEOUT_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for TIMEOUT event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn timeout(&mut self) -> TIMEOUT_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for TIMEOUT event
impl W<u32, Reg<u32, _CRV>>
[src]
pub fn crv(&mut self) -> CRV_W<'_>
[src]
Bits 0:31 - Counter reload value in number of cycles of the 32.768 kHz clock
impl W<u32, Reg<u32, _RREN>>
[src]
pub fn rr0(&mut self) -> RR0_W<'_>
[src]
Bit 0 - Enable or disable RR[0] register
pub fn rr1(&mut self) -> RR1_W<'_>
[src]
Bit 1 - Enable or disable RR[1] register
pub fn rr2(&mut self) -> RR2_W<'_>
[src]
Bit 2 - Enable or disable RR[2] register
pub fn rr3(&mut self) -> RR3_W<'_>
[src]
Bit 3 - Enable or disable RR[3] register
pub fn rr4(&mut self) -> RR4_W<'_>
[src]
Bit 4 - Enable or disable RR[4] register
pub fn rr5(&mut self) -> RR5_W<'_>
[src]
Bit 5 - Enable or disable RR[5] register
pub fn rr6(&mut self) -> RR6_W<'_>
[src]
Bit 6 - Enable or disable RR[6] register
pub fn rr7(&mut self) -> RR7_W<'_>
[src]
Bit 7 - Enable or disable RR[7] register
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn sleep(&mut self) -> SLEEP_W<'_>
[src]
Bit 0 - Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
pub fn halt(&mut self) -> HALT_W<'_>
[src]
Bit 3 - Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
impl W<u32, Reg<u32, _RR>>
[src]
impl W<u32, Reg<u32, _LED>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _A>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _B>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn reportrdy_readclracc(&mut self) -> REPORTRDY_READCLRACC_W<'_>
[src]
Bit 0 - Shortcut between REPORTRDY event and READCLRACC task
pub fn samplerdy_stop(&mut self) -> SAMPLERDY_STOP_W<'_>
[src]
Bit 1 - Shortcut between SAMPLERDY event and STOP task
pub fn reportrdy_rdclracc(&mut self) -> REPORTRDY_RDCLRACC_W<'_>
[src]
Bit 2 - Shortcut between REPORTRDY event and RDCLRACC task
pub fn reportrdy_stop(&mut self) -> REPORTRDY_STOP_W<'_>
[src]
Bit 3 - Shortcut between REPORTRDY event and STOP task
pub fn dblrdy_rdclrdbl(&mut self) -> DBLRDY_RDCLRDBL_W<'_>
[src]
Bit 4 - Shortcut between DBLRDY event and RDCLRDBL task
pub fn dblrdy_stop(&mut self) -> DBLRDY_STOP_W<'_>
[src]
Bit 5 - Shortcut between DBLRDY event and STOP task
pub fn samplerdy_readclracc(&mut self) -> SAMPLERDY_READCLRACC_W<'_>
[src]
Bit 6 - Shortcut between SAMPLERDY event and READCLRACC task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for SAMPLERDY event
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for REPORTRDY event
pub fn accof(&mut self) -> ACCOF_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for ACCOF event
pub fn dblrdy(&mut self) -> DBLRDY_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for DBLRDY event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for STOPPED event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn samplerdy(&mut self) -> SAMPLERDY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for SAMPLERDY event
pub fn reportrdy(&mut self) -> REPORTRDY_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for REPORTRDY event
pub fn accof(&mut self) -> ACCOF_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for ACCOF event
pub fn dblrdy(&mut self) -> DBLRDY_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for DBLRDY event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for STOPPED event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _LEDPOL>>
[src]
impl W<u32, Reg<u32, _SAMPLEPER>>
[src]
pub fn sampleper(&mut self) -> SAMPLEPER_W<'_>
[src]
Bits 0:3 - Sample period. The SAMPLE register will be updated for every new sample
impl W<u32, Reg<u32, _REPORTPER>>
[src]
pub fn reportper(&mut self) -> REPORTPER_W<'_>
[src]
Bits 0:3 - Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
impl W<u32, Reg<u32, _DBFEN>>
[src]
impl W<u32, Reg<u32, _LEDPRE>>
[src]
pub fn ledpre(&mut self) -> LEDPRE_W<'_>
[src]
Bits 0:8 - Period in us the LED is switched on prior to sampling
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
[src]
Bit 0 - Shortcut between READY event and SAMPLE task
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
[src]
Bit 1 - Shortcut between READY event and STOP task
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
[src]
Bit 2 - Shortcut between DOWN event and STOP task
pub fn up_stop(&mut self) -> UP_STOP_W<'_>
[src]
Bit 3 - Shortcut between UP event and STOP task
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
[src]
Bit 4 - Shortcut between CROSS event and STOP task
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Enable or disable interrupt for READY event
pub fn down(&mut self) -> DOWN_W<'_>
[src]
Bit 1 - Enable or disable interrupt for DOWN event
pub fn up(&mut self) -> UP_W<'_>
[src]
Bit 2 - Enable or disable interrupt for UP event
pub fn cross(&mut self) -> CROSS_W<'_>
[src]
Bit 3 - Enable or disable interrupt for CROSS event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for READY event
pub fn down(&mut self) -> DOWN_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for DOWN event
pub fn up(&mut self) -> UP_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for UP event
pub fn cross(&mut self) -> CROSS_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for CROSS event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for READY event
pub fn down(&mut self) -> DOWN_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for DOWN event
pub fn up(&mut self) -> UP_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for UP event
pub fn cross(&mut self) -> CROSS_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for CROSS event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _PSEL>>
[src]
impl W<u32, Reg<u32, _REFSEL>>
[src]
impl W<u32, Reg<u32, _EXTREFSEL>>
[src]
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
[src]
Bits 0:2 - External analog reference select
impl W<u32, Reg<u32, _TH>>
[src]
pub fn thdown(&mut self) -> THDOWN_W<'_>
[src]
Bits 0:5 - VDOWN = (THDOWN+1)/64*VREF
pub fn thup(&mut self) -> THUP_W<'_>
[src]
Bits 8:13 - VUP = (THUP+1)/64*VREF
impl W<u32, Reg<u32, _MODE>>
[src]
pub fn sp(&mut self) -> SP_W<'_>
[src]
Bits 0:1 - Speed and power modes
pub fn main(&mut self) -> MAIN_W<'_>
[src]
Bit 8 - Main operation modes
impl W<u32, Reg<u32, _HYST>>
[src]
impl W<u32, Reg<u32, _ISOURCE>>
[src]
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn ready_sample(&mut self) -> READY_SAMPLE_W<'_>
[src]
Bit 0 - Shortcut between READY event and SAMPLE task
pub fn ready_stop(&mut self) -> READY_STOP_W<'_>
[src]
Bit 1 - Shortcut between READY event and STOP task
pub fn down_stop(&mut self) -> DOWN_STOP_W<'_>
[src]
Bit 2 - Shortcut between DOWN event and STOP task
pub fn up_stop(&mut self) -> UP_STOP_W<'_>
[src]
Bit 3 - Shortcut between UP event and STOP task
pub fn cross_stop(&mut self) -> CROSS_STOP_W<'_>
[src]
Bit 4 - Shortcut between CROSS event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for READY event
pub fn down(&mut self) -> DOWN_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for DOWN event
pub fn up(&mut self) -> UP_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for UP event
pub fn cross(&mut self) -> CROSS_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for CROSS event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn ready(&mut self) -> READY_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for READY event
pub fn down(&mut self) -> DOWN_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for DOWN event
pub fn up(&mut self) -> UP_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for UP event
pub fn cross(&mut self) -> CROSS_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for CROSS event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _PSEL>>
[src]
impl W<u32, Reg<u32, _REFSEL>>
[src]
impl W<u32, Reg<u32, _EXTREFSEL>>
[src]
pub fn extrefsel(&mut self) -> EXTREFSEL_W<'_>
[src]
Bit 0 - External analog reference select
impl W<u32, Reg<u32, _ANADETECT>>
[src]
pub fn anadetect(&mut self) -> ANADETECT_W<'_>
[src]
Bits 0:1 - Analog detect configuration
impl W<u32, Reg<u32, _HYST>>
[src]
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]
Bit 0 - Enable or disable interrupt for TRIGGERED[0] event
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]
Bit 1 - Enable or disable interrupt for TRIGGERED[1] event
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]
Bit 2 - Enable or disable interrupt for TRIGGERED[2] event
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]
Bit 3 - Enable or disable interrupt for TRIGGERED[3] event
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]
Bit 4 - Enable or disable interrupt for TRIGGERED[4] event
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]
Bit 5 - Enable or disable interrupt for TRIGGERED[5] event
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]
Bit 6 - Enable or disable interrupt for TRIGGERED[6] event
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]
Bit 7 - Enable or disable interrupt for TRIGGERED[7] event
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]
Bit 8 - Enable or disable interrupt for TRIGGERED[8] event
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]
Bit 9 - Enable or disable interrupt for TRIGGERED[9] event
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]
Bit 10 - Enable or disable interrupt for TRIGGERED[10] event
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]
Bit 11 - Enable or disable interrupt for TRIGGERED[11] event
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]
Bit 12 - Enable or disable interrupt for TRIGGERED[12] event
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]
Bit 13 - Enable or disable interrupt for TRIGGERED[13] event
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]
Bit 14 - Enable or disable interrupt for TRIGGERED[14] event
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]
Bit 15 - Enable or disable interrupt for TRIGGERED[15] event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for TRIGGERED[0] event
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for TRIGGERED[1] event
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for TRIGGERED[2] event
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for TRIGGERED[3] event
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for TRIGGERED[4] event
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for TRIGGERED[5] event
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for TRIGGERED[6] event
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for TRIGGERED[7] event
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]
Bit 8 - Write '1' to Enable interrupt for TRIGGERED[8] event
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]
Bit 9 - Write '1' to Enable interrupt for TRIGGERED[9] event
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]
Bit 10 - Write '1' to Enable interrupt for TRIGGERED[10] event
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]
Bit 11 - Write '1' to Enable interrupt for TRIGGERED[11] event
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]
Bit 12 - Write '1' to Enable interrupt for TRIGGERED[12] event
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]
Bit 13 - Write '1' to Enable interrupt for TRIGGERED[13] event
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]
Bit 14 - Write '1' to Enable interrupt for TRIGGERED[14] event
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]
Bit 15 - Write '1' to Enable interrupt for TRIGGERED[15] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn triggered0(&mut self) -> TRIGGERED0_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for TRIGGERED[0] event
pub fn triggered1(&mut self) -> TRIGGERED1_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for TRIGGERED[1] event
pub fn triggered2(&mut self) -> TRIGGERED2_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for TRIGGERED[2] event
pub fn triggered3(&mut self) -> TRIGGERED3_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for TRIGGERED[3] event
pub fn triggered4(&mut self) -> TRIGGERED4_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for TRIGGERED[4] event
pub fn triggered5(&mut self) -> TRIGGERED5_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for TRIGGERED[5] event
pub fn triggered6(&mut self) -> TRIGGERED6_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for TRIGGERED[6] event
pub fn triggered7(&mut self) -> TRIGGERED7_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for TRIGGERED[7] event
pub fn triggered8(&mut self) -> TRIGGERED8_W<'_>
[src]
Bit 8 - Write '1' to Disable interrupt for TRIGGERED[8] event
pub fn triggered9(&mut self) -> TRIGGERED9_W<'_>
[src]
Bit 9 - Write '1' to Disable interrupt for TRIGGERED[9] event
pub fn triggered10(&mut self) -> TRIGGERED10_W<'_>
[src]
Bit 10 - Write '1' to Disable interrupt for TRIGGERED[10] event
pub fn triggered11(&mut self) -> TRIGGERED11_W<'_>
[src]
Bit 11 - Write '1' to Disable interrupt for TRIGGERED[11] event
pub fn triggered12(&mut self) -> TRIGGERED12_W<'_>
[src]
Bit 12 - Write '1' to Disable interrupt for TRIGGERED[12] event
pub fn triggered13(&mut self) -> TRIGGERED13_W<'_>
[src]
Bit 13 - Write '1' to Disable interrupt for TRIGGERED[13] event
pub fn triggered14(&mut self) -> TRIGGERED14_W<'_>
[src]
Bit 14 - Write '1' to Disable interrupt for TRIGGERED[14] event
pub fn triggered15(&mut self) -> TRIGGERED15_W<'_>
[src]
Bit 15 - Write '1' to Disable interrupt for TRIGGERED[15] event
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn compare0_clear(&mut self) -> COMPARE0_CLEAR_W<'_>
[src]
Bit 0 - Shortcut between COMPARE[0] event and CLEAR task
pub fn compare1_clear(&mut self) -> COMPARE1_CLEAR_W<'_>
[src]
Bit 1 - Shortcut between COMPARE[1] event and CLEAR task
pub fn compare2_clear(&mut self) -> COMPARE2_CLEAR_W<'_>
[src]
Bit 2 - Shortcut between COMPARE[2] event and CLEAR task
pub fn compare3_clear(&mut self) -> COMPARE3_CLEAR_W<'_>
[src]
Bit 3 - Shortcut between COMPARE[3] event and CLEAR task
pub fn compare4_clear(&mut self) -> COMPARE4_CLEAR_W<'_>
[src]
Bit 4 - Shortcut between COMPARE[4] event and CLEAR task
pub fn compare5_clear(&mut self) -> COMPARE5_CLEAR_W<'_>
[src]
Bit 5 - Shortcut between COMPARE[5] event and CLEAR task
pub fn compare0_stop(&mut self) -> COMPARE0_STOP_W<'_>
[src]
Bit 8 - Shortcut between COMPARE[0] event and STOP task
pub fn compare1_stop(&mut self) -> COMPARE1_STOP_W<'_>
[src]
Bit 9 - Shortcut between COMPARE[1] event and STOP task
pub fn compare2_stop(&mut self) -> COMPARE2_STOP_W<'_>
[src]
Bit 10 - Shortcut between COMPARE[2] event and STOP task
pub fn compare3_stop(&mut self) -> COMPARE3_STOP_W<'_>
[src]
Bit 11 - Shortcut between COMPARE[3] event and STOP task
pub fn compare4_stop(&mut self) -> COMPARE4_STOP_W<'_>
[src]
Bit 12 - Shortcut between COMPARE[4] event and STOP task
pub fn compare5_stop(&mut self) -> COMPARE5_STOP_W<'_>
[src]
Bit 13 - Shortcut between COMPARE[5] event and STOP task
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Enable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Enable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Enable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Enable interrupt for COMPARE[3] event
pub fn compare4(&mut self) -> COMPARE4_W<'_>
[src]
Bit 20 - Write '1' to Enable interrupt for COMPARE[4] event
pub fn compare5(&mut self) -> COMPARE5_W<'_>
[src]
Bit 21 - Write '1' to Enable interrupt for COMPARE[5] event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn compare0(&mut self) -> COMPARE0_W<'_>
[src]
Bit 16 - Write '1' to Disable interrupt for COMPARE[0] event
pub fn compare1(&mut self) -> COMPARE1_W<'_>
[src]
Bit 17 - Write '1' to Disable interrupt for COMPARE[1] event
pub fn compare2(&mut self) -> COMPARE2_W<'_>
[src]
Bit 18 - Write '1' to Disable interrupt for COMPARE[2] event
pub fn compare3(&mut self) -> COMPARE3_W<'_>
[src]
Bit 19 - Write '1' to Disable interrupt for COMPARE[3] event
pub fn compare4(&mut self) -> COMPARE4_W<'_>
[src]
Bit 20 - Write '1' to Disable interrupt for COMPARE[4] event
pub fn compare5(&mut self) -> COMPARE5_W<'_>
[src]
Bit 21 - Write '1' to Disable interrupt for COMPARE[5] event
impl W<u32, Reg<u32, _MODE>>
[src]
impl W<u32, Reg<u32, _BITMODE>>
[src]
impl W<u32, Reg<u32, _PRESCALER>>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
Bits 0:3 - Prescaler value
impl W<u32, Reg<u32, _CC>>
[src]
impl W<u32, Reg<u32, _PTR>>
[src]
impl W<u32, Reg<u32, _CNT>>
[src]
impl W<u32, Reg<u32, _REFRESH>>
[src]
pub fn cnt(&mut self) -> CNT_W<'_>
[src]
Bits 0:23 - Amount of additional PWM periods between samples loaded into compare register (load every REFRESH.CNT+1 PWM periods)
impl W<u32, Reg<u32, _ENDDELAY>>
[src]
impl W<u32, Reg<u32, _OUT>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SHORTS>>
[src]
pub fn seqend0_stop(&mut self) -> SEQEND0_STOP_W<'_>
[src]
Bit 0 - Shortcut between SEQEND[0] event and STOP task
pub fn seqend1_stop(&mut self) -> SEQEND1_STOP_W<'_>
[src]
Bit 1 - Shortcut between SEQEND[1] event and STOP task
pub fn loopsdone_seqstart0(&mut self) -> LOOPSDONE_SEQSTART0_W<'_>
[src]
Bit 2 - Shortcut between LOOPSDONE event and SEQSTART[0] task
pub fn loopsdone_seqstart1(&mut self) -> LOOPSDONE_SEQSTART1_W<'_>
[src]
Bit 3 - Shortcut between LOOPSDONE event and SEQSTART[1] task
pub fn loopsdone_stop(&mut self) -> LOOPSDONE_STOP_W<'_>
[src]
Bit 4 - Shortcut between LOOPSDONE event and STOP task
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Enable or disable interrupt for STOPPED event
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]
Bit 2 - Enable or disable interrupt for SEQSTARTED[0] event
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]
Bit 3 - Enable or disable interrupt for SEQSTARTED[1] event
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]
Bit 4 - Enable or disable interrupt for SEQEND[0] event
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]
Bit 5 - Enable or disable interrupt for SEQEND[1] event
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]
Bit 6 - Enable or disable interrupt for PWMPERIODEND event
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]
Bit 7 - Enable or disable interrupt for LOOPSDONE event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for STOPPED event
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for SEQSTARTED[0] event
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for SEQSTARTED[1] event
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for SEQEND[0] event
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for SEQEND[1] event
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for PWMPERIODEND event
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for LOOPSDONE event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for STOPPED event
pub fn seqstarted0(&mut self) -> SEQSTARTED0_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for SEQSTARTED[0] event
pub fn seqstarted1(&mut self) -> SEQSTARTED1_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for SEQSTARTED[1] event
pub fn seqend0(&mut self) -> SEQEND0_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for SEQEND[0] event
pub fn seqend1(&mut self) -> SEQEND1_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for SEQEND[1] event
pub fn pwmperiodend(&mut self) -> PWMPERIODEND_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for PWMPERIODEND event
pub fn loopsdone(&mut self) -> LOOPSDONE_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for LOOPSDONE event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _MODE>>
[src]
impl W<u32, Reg<u32, _COUNTERTOP>>
[src]
pub fn countertop(&mut self) -> COUNTERTOP_W<'_>
[src]
Bits 0:14 - Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.
impl W<u32, Reg<u32, _PRESCALER>>
[src]
pub fn prescaler(&mut self) -> PRESCALER_W<'_>
[src]
Bits 0:2 - Pre-scaler of PWM_CLK
impl W<u32, Reg<u32, _DECODER>>
[src]
pub fn load(&mut self) -> LOAD_W<'_>
[src]
Bits 0:1 - How a sequence is read from RAM and spread to the compare register
pub fn mode(&mut self) -> MODE_W<'_>
[src]
Bit 8 - Selects source for advancing the active sequence
impl W<u32, Reg<u32, _LOOP>>
[src]
impl W<u32, Reg<u32, _CLK>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _DIN>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _PTR>>
[src]
pub fn sampleptr(&mut self) -> SAMPLEPTR_W<'_>
[src]
Bits 0:31 - Address to write PDM samples to over DMA
impl W<u32, Reg<u32, _MAXCNT>>
[src]
pub fn buffsize(&mut self) -> BUFFSIZE_W<'_>
[src]
Bits 0:14 - Length of DMA RAM allocation in number of samples
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 0 - Enable or disable interrupt for STARTED event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Enable or disable interrupt for STOPPED event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 2 - Enable or disable interrupt for END event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for STARTED event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for STOPPED event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for END event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn started(&mut self) -> STARTED_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for STARTED event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for STOPPED event
pub fn end(&mut self) -> END_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for END event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _PDMCLKCTRL>>
[src]
impl W<u32, Reg<u32, _MODE>>
[src]
pub fn operation(&mut self) -> OPERATION_W<'_>
[src]
Bit 0 - Mono or stereo operation
pub fn edge(&mut self) -> EDGE_W<'_>
[src]
Bit 1 - Defines on which PDM_CLK edge Left (or mono) is sampled
impl W<u32, Reg<u32, _GAINL>>
[src]
pub fn gainl(&mut self) -> GAINL_W<'_>
[src]
Bits 0:6 - Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
impl W<u32, Reg<u32, _GAINR>>
[src]
pub fn gainr(&mut self) -> GAINR_W<'_>
[src]
Bits 0:7 - Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
impl W<u32, Reg<u32, _CONFIG>>
[src]
pub fn wen(&mut self) -> WEN_W<'_>
[src]
Bits 0:1 - Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
impl W<u32, Reg<u32, _ERASEPAGE>>
[src]
pub fn erasepage(&mut self) -> ERASEPAGE_W<'_>
[src]
Bits 0:31 - Register for starting erase of a page in Code area
impl W<u32, Reg<u32, _ERASEPCR1>>
[src]
pub fn erasepcr1(&mut self) -> ERASEPCR1_W<'_>
[src]
Bits 0:31 - Register for erasing a page in Code area. Equivalent to ERASEPAGE.
impl W<u32, Reg<u32, _ERASEALL>>
[src]
pub fn eraseall(&mut self) -> ERASEALL_W<'_>
[src]
Bit 0 - Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
impl W<u32, Reg<u32, _ERASEPCR0>>
[src]
pub fn erasepcr0(&mut self) -> ERASEPCR0_W<'_>
[src]
Bits 0:31 - Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.
impl W<u32, Reg<u32, _ERASEUICR>>
[src]
pub fn eraseuicr(&mut self) -> ERASEUICR_W<'_>
[src]
Bit 0 - Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
impl W<u32, Reg<u32, _ICACHECNF>>
[src]
pub fn cacheen(&mut self) -> CACHEEN_W<'_>
[src]
Bit 0 - Cache enable
pub fn cacheprofen(&mut self) -> CACHEPROFEN_W<'_>
[src]
Bit 8 - Cache profiling enable
impl W<u32, Reg<u32, _IHIT>>
[src]
impl W<u32, Reg<u32, _IMISS>>
[src]
impl W<u32, Reg<u32, _EEP>>
[src]
pub fn eep(&mut self) -> EEP_W<'_>
[src]
Bits 0:31 - Pointer to event register. Accepts only addresses to registers from the Event group.
impl W<u32, Reg<u32, _TEP>>
[src]
pub fn tep(&mut self) -> TEP_W<'_>
[src]
Bits 0:31 - Pointer to task register. Accepts only addresses to registers from the Task group.
impl W<u32, Reg<u32, _TEP>>
[src]
impl W<u32, Reg<u32, _CHEN>>
[src]
pub fn ch0(&mut self) -> CH0_W<'_>
[src]
Bit 0 - Enable or disable channel 0
pub fn ch1(&mut self) -> CH1_W<'_>
[src]
Bit 1 - Enable or disable channel 1
pub fn ch2(&mut self) -> CH2_W<'_>
[src]
Bit 2 - Enable or disable channel 2
pub fn ch3(&mut self) -> CH3_W<'_>
[src]
Bit 3 - Enable or disable channel 3
pub fn ch4(&mut self) -> CH4_W<'_>
[src]
Bit 4 - Enable or disable channel 4
pub fn ch5(&mut self) -> CH5_W<'_>
[src]
Bit 5 - Enable or disable channel 5
pub fn ch6(&mut self) -> CH6_W<'_>
[src]
Bit 6 - Enable or disable channel 6
pub fn ch7(&mut self) -> CH7_W<'_>
[src]
Bit 7 - Enable or disable channel 7
pub fn ch8(&mut self) -> CH8_W<'_>
[src]
Bit 8 - Enable or disable channel 8
pub fn ch9(&mut self) -> CH9_W<'_>
[src]
Bit 9 - Enable or disable channel 9
pub fn ch10(&mut self) -> CH10_W<'_>
[src]
Bit 10 - Enable or disable channel 10
pub fn ch11(&mut self) -> CH11_W<'_>
[src]
Bit 11 - Enable or disable channel 11
pub fn ch12(&mut self) -> CH12_W<'_>
[src]
Bit 12 - Enable or disable channel 12
pub fn ch13(&mut self) -> CH13_W<'_>
[src]
Bit 13 - Enable or disable channel 13
pub fn ch14(&mut self) -> CH14_W<'_>
[src]
Bit 14 - Enable or disable channel 14
pub fn ch15(&mut self) -> CH15_W<'_>
[src]
Bit 15 - Enable or disable channel 15
pub fn ch16(&mut self) -> CH16_W<'_>
[src]
Bit 16 - Enable or disable channel 16
pub fn ch17(&mut self) -> CH17_W<'_>
[src]
Bit 17 - Enable or disable channel 17
pub fn ch18(&mut self) -> CH18_W<'_>
[src]
Bit 18 - Enable or disable channel 18
pub fn ch19(&mut self) -> CH19_W<'_>
[src]
Bit 19 - Enable or disable channel 19
pub fn ch20(&mut self) -> CH20_W<'_>
[src]
Bit 20 - Enable or disable channel 20
pub fn ch21(&mut self) -> CH21_W<'_>
[src]
Bit 21 - Enable or disable channel 21
pub fn ch22(&mut self) -> CH22_W<'_>
[src]
Bit 22 - Enable or disable channel 22
pub fn ch23(&mut self) -> CH23_W<'_>
[src]
Bit 23 - Enable or disable channel 23
pub fn ch24(&mut self) -> CH24_W<'_>
[src]
Bit 24 - Enable or disable channel 24
pub fn ch25(&mut self) -> CH25_W<'_>
[src]
Bit 25 - Enable or disable channel 25
pub fn ch26(&mut self) -> CH26_W<'_>
[src]
Bit 26 - Enable or disable channel 26
pub fn ch27(&mut self) -> CH27_W<'_>
[src]
Bit 27 - Enable or disable channel 27
pub fn ch28(&mut self) -> CH28_W<'_>
[src]
Bit 28 - Enable or disable channel 28
pub fn ch29(&mut self) -> CH29_W<'_>
[src]
Bit 29 - Enable or disable channel 29
pub fn ch30(&mut self) -> CH30_W<'_>
[src]
Bit 30 - Enable or disable channel 30
pub fn ch31(&mut self) -> CH31_W<'_>
[src]
Bit 31 - Enable or disable channel 31
impl W<u32, Reg<u32, _CHENSET>>
[src]
pub fn ch0(&mut self) -> CH0_W<'_>
[src]
Bit 0 - Channel 0 enable set register. Writing '0' has no effect
pub fn ch1(&mut self) -> CH1_W<'_>
[src]
Bit 1 - Channel 1 enable set register. Writing '0' has no effect
pub fn ch2(&mut self) -> CH2_W<'_>
[src]
Bit 2 - Channel 2 enable set register. Writing '0' has no effect
pub fn ch3(&mut self) -> CH3_W<'_>
[src]
Bit 3 - Channel 3 enable set register. Writing '0' has no effect
pub fn ch4(&mut self) -> CH4_W<'_>
[src]
Bit 4 - Channel 4 enable set register. Writing '0' has no effect
pub fn ch5(&mut self) -> CH5_W<'_>
[src]
Bit 5 - Channel 5 enable set register. Writing '0' has no effect
pub fn ch6(&mut self) -> CH6_W<'_>
[src]
Bit 6 - Channel 6 enable set register. Writing '0' has no effect
pub fn ch7(&mut self) -> CH7_W<'_>
[src]
Bit 7 - Channel 7 enable set register. Writing '0' has no effect
pub fn ch8(&mut self) -> CH8_W<'_>
[src]
Bit 8 - Channel 8 enable set register. Writing '0' has no effect
pub fn ch9(&mut self) -> CH9_W<'_>
[src]
Bit 9 - Channel 9 enable set register. Writing '0' has no effect
pub fn ch10(&mut self) -> CH10_W<'_>
[src]
Bit 10 - Channel 10 enable set register. Writing '0' has no effect
pub fn ch11(&mut self) -> CH11_W<'_>
[src]
Bit 11 - Channel 11 enable set register. Writing '0' has no effect
pub fn ch12(&mut self) -> CH12_W<'_>
[src]
Bit 12 - Channel 12 enable set register. Writing '0' has no effect
pub fn ch13(&mut self) -> CH13_W<'_>
[src]
Bit 13 - Channel 13 enable set register. Writing '0' has no effect
pub fn ch14(&mut self) -> CH14_W<'_>
[src]
Bit 14 - Channel 14 enable set register. Writing '0' has no effect
pub fn ch15(&mut self) -> CH15_W<'_>
[src]
Bit 15 - Channel 15 enable set register. Writing '0' has no effect
pub fn ch16(&mut self) -> CH16_W<'_>
[src]
Bit 16 - Channel 16 enable set register. Writing '0' has no effect
pub fn ch17(&mut self) -> CH17_W<'_>
[src]
Bit 17 - Channel 17 enable set register. Writing '0' has no effect
pub fn ch18(&mut self) -> CH18_W<'_>
[src]
Bit 18 - Channel 18 enable set register. Writing '0' has no effect
pub fn ch19(&mut self) -> CH19_W<'_>
[src]
Bit 19 - Channel 19 enable set register. Writing '0' has no effect
pub fn ch20(&mut self) -> CH20_W<'_>
[src]
Bit 20 - Channel 20 enable set register. Writing '0' has no effect
pub fn ch21(&mut self) -> CH21_W<'_>
[src]
Bit 21 - Channel 21 enable set register. Writing '0' has no effect
pub fn ch22(&mut self) -> CH22_W<'_>
[src]
Bit 22 - Channel 22 enable set register. Writing '0' has no effect
pub fn ch23(&mut self) -> CH23_W<'_>
[src]
Bit 23 - Channel 23 enable set register. Writing '0' has no effect
pub fn ch24(&mut self) -> CH24_W<'_>
[src]
Bit 24 - Channel 24 enable set register. Writing '0' has no effect
pub fn ch25(&mut self) -> CH25_W<'_>
[src]
Bit 25 - Channel 25 enable set register. Writing '0' has no effect
pub fn ch26(&mut self) -> CH26_W<'_>
[src]
Bit 26 - Channel 26 enable set register. Writing '0' has no effect
pub fn ch27(&mut self) -> CH27_W<'_>
[src]
Bit 27 - Channel 27 enable set register. Writing '0' has no effect
pub fn ch28(&mut self) -> CH28_W<'_>
[src]
Bit 28 - Channel 28 enable set register. Writing '0' has no effect
pub fn ch29(&mut self) -> CH29_W<'_>
[src]
Bit 29 - Channel 29 enable set register. Writing '0' has no effect
pub fn ch30(&mut self) -> CH30_W<'_>
[src]
Bit 30 - Channel 30 enable set register. Writing '0' has no effect
pub fn ch31(&mut self) -> CH31_W<'_>
[src]
Bit 31 - Channel 31 enable set register. Writing '0' has no effect
impl W<u32, Reg<u32, _CHENCLR>>
[src]
pub fn ch0(&mut self) -> CH0_W<'_>
[src]
Bit 0 - Channel 0 enable clear register. Writing '0' has no effect
pub fn ch1(&mut self) -> CH1_W<'_>
[src]
Bit 1 - Channel 1 enable clear register. Writing '0' has no effect
pub fn ch2(&mut self) -> CH2_W<'_>
[src]
Bit 2 - Channel 2 enable clear register. Writing '0' has no effect
pub fn ch3(&mut self) -> CH3_W<'_>
[src]
Bit 3 - Channel 3 enable clear register. Writing '0' has no effect
pub fn ch4(&mut self) -> CH4_W<'_>
[src]
Bit 4 - Channel 4 enable clear register. Writing '0' has no effect
pub fn ch5(&mut self) -> CH5_W<'_>
[src]
Bit 5 - Channel 5 enable clear register. Writing '0' has no effect
pub fn ch6(&mut self) -> CH6_W<'_>
[src]
Bit 6 - Channel 6 enable clear register. Writing '0' has no effect
pub fn ch7(&mut self) -> CH7_W<'_>
[src]
Bit 7 - Channel 7 enable clear register. Writing '0' has no effect
pub fn ch8(&mut self) -> CH8_W<'_>
[src]
Bit 8 - Channel 8 enable clear register. Writing '0' has no effect
pub fn ch9(&mut self) -> CH9_W<'_>
[src]
Bit 9 - Channel 9 enable clear register. Writing '0' has no effect
pub fn ch10(&mut self) -> CH10_W<'_>
[src]
Bit 10 - Channel 10 enable clear register. Writing '0' has no effect
pub fn ch11(&mut self) -> CH11_W<'_>
[src]
Bit 11 - Channel 11 enable clear register. Writing '0' has no effect
pub fn ch12(&mut self) -> CH12_W<'_>
[src]
Bit 12 - Channel 12 enable clear register. Writing '0' has no effect
pub fn ch13(&mut self) -> CH13_W<'_>
[src]
Bit 13 - Channel 13 enable clear register. Writing '0' has no effect
pub fn ch14(&mut self) -> CH14_W<'_>
[src]
Bit 14 - Channel 14 enable clear register. Writing '0' has no effect
pub fn ch15(&mut self) -> CH15_W<'_>
[src]
Bit 15 - Channel 15 enable clear register. Writing '0' has no effect
pub fn ch16(&mut self) -> CH16_W<'_>
[src]
Bit 16 - Channel 16 enable clear register. Writing '0' has no effect
pub fn ch17(&mut self) -> CH17_W<'_>
[src]
Bit 17 - Channel 17 enable clear register. Writing '0' has no effect
pub fn ch18(&mut self) -> CH18_W<'_>
[src]
Bit 18 - Channel 18 enable clear register. Writing '0' has no effect
pub fn ch19(&mut self) -> CH19_W<'_>
[src]
Bit 19 - Channel 19 enable clear register. Writing '0' has no effect
pub fn ch20(&mut self) -> CH20_W<'_>
[src]
Bit 20 - Channel 20 enable clear register. Writing '0' has no effect
pub fn ch21(&mut self) -> CH21_W<'_>
[src]
Bit 21 - Channel 21 enable clear register. Writing '0' has no effect
pub fn ch22(&mut self) -> CH22_W<'_>
[src]
Bit 22 - Channel 22 enable clear register. Writing '0' has no effect
pub fn ch23(&mut self) -> CH23_W<'_>
[src]
Bit 23 - Channel 23 enable clear register. Writing '0' has no effect
pub fn ch24(&mut self) -> CH24_W<'_>
[src]
Bit 24 - Channel 24 enable clear register. Writing '0' has no effect
pub fn ch25(&mut self) -> CH25_W<'_>
[src]
Bit 25 - Channel 25 enable clear register. Writing '0' has no effect
pub fn ch26(&mut self) -> CH26_W<'_>
[src]
Bit 26 - Channel 26 enable clear register. Writing '0' has no effect
pub fn ch27(&mut self) -> CH27_W<'_>
[src]
Bit 27 - Channel 27 enable clear register. Writing '0' has no effect
pub fn ch28(&mut self) -> CH28_W<'_>
[src]
Bit 28 - Channel 28 enable clear register. Writing '0' has no effect
pub fn ch29(&mut self) -> CH29_W<'_>
[src]
Bit 29 - Channel 29 enable clear register. Writing '0' has no effect
pub fn ch30(&mut self) -> CH30_W<'_>
[src]
Bit 30 - Channel 30 enable clear register. Writing '0' has no effect
pub fn ch31(&mut self) -> CH31_W<'_>
[src]
Bit 31 - Channel 31 enable clear register. Writing '0' has no effect
impl W<u32, Reg<u32, _CHG>>
[src]
pub fn ch0(&mut self) -> CH0_W<'_>
[src]
Bit 0 - Include or exclude channel 0
pub fn ch1(&mut self) -> CH1_W<'_>
[src]
Bit 1 - Include or exclude channel 1
pub fn ch2(&mut self) -> CH2_W<'_>
[src]
Bit 2 - Include or exclude channel 2
pub fn ch3(&mut self) -> CH3_W<'_>
[src]
Bit 3 - Include or exclude channel 3
pub fn ch4(&mut self) -> CH4_W<'_>
[src]
Bit 4 - Include or exclude channel 4
pub fn ch5(&mut self) -> CH5_W<'_>
[src]
Bit 5 - Include or exclude channel 5
pub fn ch6(&mut self) -> CH6_W<'_>
[src]
Bit 6 - Include or exclude channel 6
pub fn ch7(&mut self) -> CH7_W<'_>
[src]
Bit 7 - Include or exclude channel 7
pub fn ch8(&mut self) -> CH8_W<'_>
[src]
Bit 8 - Include or exclude channel 8
pub fn ch9(&mut self) -> CH9_W<'_>
[src]
Bit 9 - Include or exclude channel 9
pub fn ch10(&mut self) -> CH10_W<'_>
[src]
Bit 10 - Include or exclude channel 10
pub fn ch11(&mut self) -> CH11_W<'_>
[src]
Bit 11 - Include or exclude channel 11
pub fn ch12(&mut self) -> CH12_W<'_>
[src]
Bit 12 - Include or exclude channel 12
pub fn ch13(&mut self) -> CH13_W<'_>
[src]
Bit 13 - Include or exclude channel 13
pub fn ch14(&mut self) -> CH14_W<'_>
[src]
Bit 14 - Include or exclude channel 14
pub fn ch15(&mut self) -> CH15_W<'_>
[src]
Bit 15 - Include or exclude channel 15
pub fn ch16(&mut self) -> CH16_W<'_>
[src]
Bit 16 - Include or exclude channel 16
pub fn ch17(&mut self) -> CH17_W<'_>
[src]
Bit 17 - Include or exclude channel 17
pub fn ch18(&mut self) -> CH18_W<'_>
[src]
Bit 18 - Include or exclude channel 18
pub fn ch19(&mut self) -> CH19_W<'_>
[src]
Bit 19 - Include or exclude channel 19
pub fn ch20(&mut self) -> CH20_W<'_>
[src]
Bit 20 - Include or exclude channel 20
pub fn ch21(&mut self) -> CH21_W<'_>
[src]
Bit 21 - Include or exclude channel 21
pub fn ch22(&mut self) -> CH22_W<'_>
[src]
Bit 22 - Include or exclude channel 22
pub fn ch23(&mut self) -> CH23_W<'_>
[src]
Bit 23 - Include or exclude channel 23
pub fn ch24(&mut self) -> CH24_W<'_>
[src]
Bit 24 - Include or exclude channel 24
pub fn ch25(&mut self) -> CH25_W<'_>
[src]
Bit 25 - Include or exclude channel 25
pub fn ch26(&mut self) -> CH26_W<'_>
[src]
Bit 26 - Include or exclude channel 26
pub fn ch27(&mut self) -> CH27_W<'_>
[src]
Bit 27 - Include or exclude channel 27
pub fn ch28(&mut self) -> CH28_W<'_>
[src]
Bit 28 - Include or exclude channel 28
pub fn ch29(&mut self) -> CH29_W<'_>
[src]
Bit 29 - Include or exclude channel 29
pub fn ch30(&mut self) -> CH30_W<'_>
[src]
Bit 30 - Include or exclude channel 30
pub fn ch31(&mut self) -> CH31_W<'_>
[src]
Bit 31 - Include or exclude channel 31
impl W<u32, Reg<u32, _SUBSTATWA>>
[src]
pub fn sr0(&mut self) -> SR0_W<'_>
[src]
Bit 0 - Subregion 0 in region 0 (write '1' to clear)
pub fn sr1(&mut self) -> SR1_W<'_>
[src]
Bit 1 - Subregion 1 in region 0 (write '1' to clear)
pub fn sr2(&mut self) -> SR2_W<'_>
[src]
Bit 2 - Subregion 2 in region 0 (write '1' to clear)
pub fn sr3(&mut self) -> SR3_W<'_>
[src]
Bit 3 - Subregion 3 in region 0 (write '1' to clear)
pub fn sr4(&mut self) -> SR4_W<'_>
[src]
Bit 4 - Subregion 4 in region 0 (write '1' to clear)
pub fn sr5(&mut self) -> SR5_W<'_>
[src]
Bit 5 - Subregion 5 in region 0 (write '1' to clear)
pub fn sr6(&mut self) -> SR6_W<'_>
[src]
Bit 6 - Subregion 6 in region 0 (write '1' to clear)
pub fn sr7(&mut self) -> SR7_W<'_>
[src]
Bit 7 - Subregion 7 in region 0 (write '1' to clear)
pub fn sr8(&mut self) -> SR8_W<'_>
[src]
Bit 8 - Subregion 8 in region 0 (write '1' to clear)
pub fn sr9(&mut self) -> SR9_W<'_>
[src]
Bit 9 - Subregion 9 in region 0 (write '1' to clear)
pub fn sr10(&mut self) -> SR10_W<'_>
[src]
Bit 10 - Subregion 10 in region 0 (write '1' to clear)
pub fn sr11(&mut self) -> SR11_W<'_>
[src]
Bit 11 - Subregion 11 in region 0 (write '1' to clear)
pub fn sr12(&mut self) -> SR12_W<'_>
[src]
Bit 12 - Subregion 12 in region 0 (write '1' to clear)
pub fn sr13(&mut self) -> SR13_W<'_>
[src]
Bit 13 - Subregion 13 in region 0 (write '1' to clear)
pub fn sr14(&mut self) -> SR14_W<'_>
[src]
Bit 14 - Subregion 14 in region 0 (write '1' to clear)
pub fn sr15(&mut self) -> SR15_W<'_>
[src]
Bit 15 - Subregion 15 in region 0 (write '1' to clear)
pub fn sr16(&mut self) -> SR16_W<'_>
[src]
Bit 16 - Subregion 16 in region 0 (write '1' to clear)
pub fn sr17(&mut self) -> SR17_W<'_>
[src]
Bit 17 - Subregion 17 in region 0 (write '1' to clear)
pub fn sr18(&mut self) -> SR18_W<'_>
[src]
Bit 18 - Subregion 18 in region 0 (write '1' to clear)
pub fn sr19(&mut self) -> SR19_W<'_>
[src]
Bit 19 - Subregion 19 in region 0 (write '1' to clear)
pub fn sr20(&mut self) -> SR20_W<'_>
[src]
Bit 20 - Subregion 20 in region 0 (write '1' to clear)
pub fn sr21(&mut self) -> SR21_W<'_>
[src]
Bit 21 - Subregion 21 in region 0 (write '1' to clear)
pub fn sr22(&mut self) -> SR22_W<'_>
[src]
Bit 22 - Subregion 22 in region 0 (write '1' to clear)
pub fn sr23(&mut self) -> SR23_W<'_>
[src]
Bit 23 - Subregion 23 in region 0 (write '1' to clear)
pub fn sr24(&mut self) -> SR24_W<'_>
[src]
Bit 24 - Subregion 24 in region 0 (write '1' to clear)
pub fn sr25(&mut self) -> SR25_W<'_>
[src]
Bit 25 - Subregion 25 in region 0 (write '1' to clear)
pub fn sr26(&mut self) -> SR26_W<'_>
[src]
Bit 26 - Subregion 26 in region 0 (write '1' to clear)
pub fn sr27(&mut self) -> SR27_W<'_>
[src]
Bit 27 - Subregion 27 in region 0 (write '1' to clear)
pub fn sr28(&mut self) -> SR28_W<'_>
[src]
Bit 28 - Subregion 28 in region 0 (write '1' to clear)
pub fn sr29(&mut self) -> SR29_W<'_>
[src]
Bit 29 - Subregion 29 in region 0 (write '1' to clear)
pub fn sr30(&mut self) -> SR30_W<'_>
[src]
Bit 30 - Subregion 30 in region 0 (write '1' to clear)
pub fn sr31(&mut self) -> SR31_W<'_>
[src]
Bit 31 - Subregion 31 in region 0 (write '1' to clear)
impl W<u32, Reg<u32, _SUBSTATRA>>
[src]
pub fn sr0(&mut self) -> SR0_W<'_>
[src]
Bit 0 - Subregion 0 in region 0 (write '1' to clear)
pub fn sr1(&mut self) -> SR1_W<'_>
[src]
Bit 1 - Subregion 1 in region 0 (write '1' to clear)
pub fn sr2(&mut self) -> SR2_W<'_>
[src]
Bit 2 - Subregion 2 in region 0 (write '1' to clear)
pub fn sr3(&mut self) -> SR3_W<'_>
[src]
Bit 3 - Subregion 3 in region 0 (write '1' to clear)
pub fn sr4(&mut self) -> SR4_W<'_>
[src]
Bit 4 - Subregion 4 in region 0 (write '1' to clear)
pub fn sr5(&mut self) -> SR5_W<'_>
[src]
Bit 5 - Subregion 5 in region 0 (write '1' to clear)
pub fn sr6(&mut self) -> SR6_W<'_>
[src]
Bit 6 - Subregion 6 in region 0 (write '1' to clear)
pub fn sr7(&mut self) -> SR7_W<'_>
[src]
Bit 7 - Subregion 7 in region 0 (write '1' to clear)
pub fn sr8(&mut self) -> SR8_W<'_>
[src]
Bit 8 - Subregion 8 in region 0 (write '1' to clear)
pub fn sr9(&mut self) -> SR9_W<'_>
[src]
Bit 9 - Subregion 9 in region 0 (write '1' to clear)
pub fn sr10(&mut self) -> SR10_W<'_>
[src]
Bit 10 - Subregion 10 in region 0 (write '1' to clear)
pub fn sr11(&mut self) -> SR11_W<'_>
[src]
Bit 11 - Subregion 11 in region 0 (write '1' to clear)
pub fn sr12(&mut self) -> SR12_W<'_>
[src]
Bit 12 - Subregion 12 in region 0 (write '1' to clear)
pub fn sr13(&mut self) -> SR13_W<'_>
[src]
Bit 13 - Subregion 13 in region 0 (write '1' to clear)
pub fn sr14(&mut self) -> SR14_W<'_>
[src]
Bit 14 - Subregion 14 in region 0 (write '1' to clear)
pub fn sr15(&mut self) -> SR15_W<'_>
[src]
Bit 15 - Subregion 15 in region 0 (write '1' to clear)
pub fn sr16(&mut self) -> SR16_W<'_>
[src]
Bit 16 - Subregion 16 in region 0 (write '1' to clear)
pub fn sr17(&mut self) -> SR17_W<'_>
[src]
Bit 17 - Subregion 17 in region 0 (write '1' to clear)
pub fn sr18(&mut self) -> SR18_W<'_>
[src]
Bit 18 - Subregion 18 in region 0 (write '1' to clear)
pub fn sr19(&mut self) -> SR19_W<'_>
[src]
Bit 19 - Subregion 19 in region 0 (write '1' to clear)
pub fn sr20(&mut self) -> SR20_W<'_>
[src]
Bit 20 - Subregion 20 in region 0 (write '1' to clear)
pub fn sr21(&mut self) -> SR21_W<'_>
[src]
Bit 21 - Subregion 21 in region 0 (write '1' to clear)
pub fn sr22(&mut self) -> SR22_W<'_>
[src]
Bit 22 - Subregion 22 in region 0 (write '1' to clear)
pub fn sr23(&mut self) -> SR23_W<'_>
[src]
Bit 23 - Subregion 23 in region 0 (write '1' to clear)
pub fn sr24(&mut self) -> SR24_W<'_>
[src]
Bit 24 - Subregion 24 in region 0 (write '1' to clear)
pub fn sr25(&mut self) -> SR25_W<'_>
[src]
Bit 25 - Subregion 25 in region 0 (write '1' to clear)
pub fn sr26(&mut self) -> SR26_W<'_>
[src]
Bit 26 - Subregion 26 in region 0 (write '1' to clear)
pub fn sr27(&mut self) -> SR27_W<'_>
[src]
Bit 27 - Subregion 27 in region 0 (write '1' to clear)
pub fn sr28(&mut self) -> SR28_W<'_>
[src]
Bit 28 - Subregion 28 in region 0 (write '1' to clear)
pub fn sr29(&mut self) -> SR29_W<'_>
[src]
Bit 29 - Subregion 29 in region 0 (write '1' to clear)
pub fn sr30(&mut self) -> SR30_W<'_>
[src]
Bit 30 - Subregion 30 in region 0 (write '1' to clear)
pub fn sr31(&mut self) -> SR31_W<'_>
[src]
Bit 31 - Subregion 31 in region 0 (write '1' to clear)
impl W<u32, Reg<u32, _START>>
[src]
impl W<u32, Reg<u32, _END>>
[src]
impl W<u32, Reg<u32, _SUBS>>
[src]
pub fn sr0(&mut self) -> SR0_W<'_>
[src]
Bit 0 - Include or exclude subregion 0 in region
pub fn sr1(&mut self) -> SR1_W<'_>
[src]
Bit 1 - Include or exclude subregion 1 in region
pub fn sr2(&mut self) -> SR2_W<'_>
[src]
Bit 2 - Include or exclude subregion 2 in region
pub fn sr3(&mut self) -> SR3_W<'_>
[src]
Bit 3 - Include or exclude subregion 3 in region
pub fn sr4(&mut self) -> SR4_W<'_>
[src]
Bit 4 - Include or exclude subregion 4 in region
pub fn sr5(&mut self) -> SR5_W<'_>
[src]
Bit 5 - Include or exclude subregion 5 in region
pub fn sr6(&mut self) -> SR6_W<'_>
[src]
Bit 6 - Include or exclude subregion 6 in region
pub fn sr7(&mut self) -> SR7_W<'_>
[src]
Bit 7 - Include or exclude subregion 7 in region
pub fn sr8(&mut self) -> SR8_W<'_>
[src]
Bit 8 - Include or exclude subregion 8 in region
pub fn sr9(&mut self) -> SR9_W<'_>
[src]
Bit 9 - Include or exclude subregion 9 in region
pub fn sr10(&mut self) -> SR10_W<'_>
[src]
Bit 10 - Include or exclude subregion 10 in region
pub fn sr11(&mut self) -> SR11_W<'_>
[src]
Bit 11 - Include or exclude subregion 11 in region
pub fn sr12(&mut self) -> SR12_W<'_>
[src]
Bit 12 - Include or exclude subregion 12 in region
pub fn sr13(&mut self) -> SR13_W<'_>
[src]
Bit 13 - Include or exclude subregion 13 in region
pub fn sr14(&mut self) -> SR14_W<'_>
[src]
Bit 14 - Include or exclude subregion 14 in region
pub fn sr15(&mut self) -> SR15_W<'_>
[src]
Bit 15 - Include or exclude subregion 15 in region
pub fn sr16(&mut self) -> SR16_W<'_>
[src]
Bit 16 - Include or exclude subregion 16 in region
pub fn sr17(&mut self) -> SR17_W<'_>
[src]
Bit 17 - Include or exclude subregion 17 in region
pub fn sr18(&mut self) -> SR18_W<'_>
[src]
Bit 18 - Include or exclude subregion 18 in region
pub fn sr19(&mut self) -> SR19_W<'_>
[src]
Bit 19 - Include or exclude subregion 19 in region
pub fn sr20(&mut self) -> SR20_W<'_>
[src]
Bit 20 - Include or exclude subregion 20 in region
pub fn sr21(&mut self) -> SR21_W<'_>
[src]
Bit 21 - Include or exclude subregion 21 in region
pub fn sr22(&mut self) -> SR22_W<'_>
[src]
Bit 22 - Include or exclude subregion 22 in region
pub fn sr23(&mut self) -> SR23_W<'_>
[src]
Bit 23 - Include or exclude subregion 23 in region
pub fn sr24(&mut self) -> SR24_W<'_>
[src]
Bit 24 - Include or exclude subregion 24 in region
pub fn sr25(&mut self) -> SR25_W<'_>
[src]
Bit 25 - Include or exclude subregion 25 in region
pub fn sr26(&mut self) -> SR26_W<'_>
[src]
Bit 26 - Include or exclude subregion 26 in region
pub fn sr27(&mut self) -> SR27_W<'_>
[src]
Bit 27 - Include or exclude subregion 27 in region
pub fn sr28(&mut self) -> SR28_W<'_>
[src]
Bit 28 - Include or exclude subregion 28 in region
pub fn sr29(&mut self) -> SR29_W<'_>
[src]
Bit 29 - Include or exclude subregion 29 in region
pub fn sr30(&mut self) -> SR30_W<'_>
[src]
Bit 30 - Include or exclude subregion 30 in region
pub fn sr31(&mut self) -> SR31_W<'_>
[src]
Bit 31 - Include or exclude subregion 31 in region
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
Bit 0 - Enable or disable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
Bit 1 - Enable or disable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
Bit 2 - Enable or disable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
Bit 3 - Enable or disable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
Bit 4 - Enable or disable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
Bit 5 - Enable or disable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
Bit 6 - Enable or disable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
Bit 7 - Enable or disable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
Bit 24 - Enable or disable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
Bit 25 - Enable or disable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
Bit 26 - Enable or disable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
Bit 27 - Enable or disable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
Bit 0 - Write '1' to Enable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
Bit 3 - Write '1' to Enable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
Bit 4 - Write '1' to Enable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
Bit 6 - Write '1' to Enable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
Bit 7 - Write '1' to Enable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
Bit 24 - Write '1' to Enable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
Bit 25 - Write '1' to Enable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
Bit 26 - Write '1' to Enable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
Bit 27 - Write '1' to Enable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
Bit 0 - Write '1' to Disable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
Bit 3 - Write '1' to Disable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
Bit 4 - Write '1' to Disable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
Bit 6 - Write '1' to Disable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
Bit 7 - Write '1' to Disable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
Bit 24 - Write '1' to Disable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
Bit 25 - Write '1' to Disable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
Bit 26 - Write '1' to Disable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
Bit 27 - Write '1' to Disable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _NMIEN>>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
Bit 0 - Enable or disable non-maskable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
Bit 1 - Enable or disable non-maskable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
Bit 2 - Enable or disable non-maskable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
Bit 3 - Enable or disable non-maskable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
Bit 4 - Enable or disable non-maskable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
Bit 5 - Enable or disable non-maskable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
Bit 6 - Enable or disable non-maskable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
Bit 7 - Enable or disable non-maskable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
Bit 24 - Enable or disable non-maskable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
Bit 25 - Enable or disable non-maskable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
Bit 26 - Enable or disable non-maskable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
Bit 27 - Enable or disable non-maskable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _NMIENSET>>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
Bit 0 - Write '1' to Enable non-maskable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
Bit 1 - Write '1' to Enable non-maskable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
Bit 2 - Write '1' to Enable non-maskable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
Bit 3 - Write '1' to Enable non-maskable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
Bit 4 - Write '1' to Enable non-maskable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
Bit 5 - Write '1' to Enable non-maskable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
Bit 6 - Write '1' to Enable non-maskable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
Bit 7 - Write '1' to Enable non-maskable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
Bit 24 - Write '1' to Enable non-maskable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
Bit 25 - Write '1' to Enable non-maskable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
Bit 26 - Write '1' to Enable non-maskable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
Bit 27 - Write '1' to Enable non-maskable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _NMIENCLR>>
[src]
pub fn region0wa(&mut self) -> REGION0WA_W<'_>
[src]
Bit 0 - Write '1' to Disable non-maskable interrupt for REGION[0].WA event
pub fn region0ra(&mut self) -> REGION0RA_W<'_>
[src]
Bit 1 - Write '1' to Disable non-maskable interrupt for REGION[0].RA event
pub fn region1wa(&mut self) -> REGION1WA_W<'_>
[src]
Bit 2 - Write '1' to Disable non-maskable interrupt for REGION[1].WA event
pub fn region1ra(&mut self) -> REGION1RA_W<'_>
[src]
Bit 3 - Write '1' to Disable non-maskable interrupt for REGION[1].RA event
pub fn region2wa(&mut self) -> REGION2WA_W<'_>
[src]
Bit 4 - Write '1' to Disable non-maskable interrupt for REGION[2].WA event
pub fn region2ra(&mut self) -> REGION2RA_W<'_>
[src]
Bit 5 - Write '1' to Disable non-maskable interrupt for REGION[2].RA event
pub fn region3wa(&mut self) -> REGION3WA_W<'_>
[src]
Bit 6 - Write '1' to Disable non-maskable interrupt for REGION[3].WA event
pub fn region3ra(&mut self) -> REGION3RA_W<'_>
[src]
Bit 7 - Write '1' to Disable non-maskable interrupt for REGION[3].RA event
pub fn pregion0wa(&mut self) -> PREGION0WA_W<'_>
[src]
Bit 24 - Write '1' to Disable non-maskable interrupt for PREGION[0].WA event
pub fn pregion0ra(&mut self) -> PREGION0RA_W<'_>
[src]
Bit 25 - Write '1' to Disable non-maskable interrupt for PREGION[0].RA event
pub fn pregion1wa(&mut self) -> PREGION1WA_W<'_>
[src]
Bit 26 - Write '1' to Disable non-maskable interrupt for PREGION[1].WA event
pub fn pregion1ra(&mut self) -> PREGION1RA_W<'_>
[src]
Bit 27 - Write '1' to Disable non-maskable interrupt for PREGION[1].RA event
impl W<u32, Reg<u32, _REGIONEN>>
[src]
pub fn rgn0wa(&mut self) -> RGN0WA_W<'_>
[src]
Bit 0 - Enable/disable write access watch in region[0]
pub fn rgn0ra(&mut self) -> RGN0RA_W<'_>
[src]
Bit 1 - Enable/disable read access watch in region[0]
pub fn rgn1wa(&mut self) -> RGN1WA_W<'_>
[src]
Bit 2 - Enable/disable write access watch in region[1]
pub fn rgn1ra(&mut self) -> RGN1RA_W<'_>
[src]
Bit 3 - Enable/disable read access watch in region[1]
pub fn rgn2wa(&mut self) -> RGN2WA_W<'_>
[src]
Bit 4 - Enable/disable write access watch in region[2]
pub fn rgn2ra(&mut self) -> RGN2RA_W<'_>
[src]
Bit 5 - Enable/disable read access watch in region[2]
pub fn rgn3wa(&mut self) -> RGN3WA_W<'_>
[src]
Bit 6 - Enable/disable write access watch in region[3]
pub fn rgn3ra(&mut self) -> RGN3RA_W<'_>
[src]
Bit 7 - Enable/disable read access watch in region[3]
pub fn prgn0wa(&mut self) -> PRGN0WA_W<'_>
[src]
Bit 24 - Enable/disable write access watch in PREGION[0]
pub fn prgn0ra(&mut self) -> PRGN0RA_W<'_>
[src]
Bit 25 - Enable/disable read access watch in PREGION[0]
pub fn prgn1wa(&mut self) -> PRGN1WA_W<'_>
[src]
Bit 26 - Enable/disable write access watch in PREGION[1]
pub fn prgn1ra(&mut self) -> PRGN1RA_W<'_>
[src]
Bit 27 - Enable/disable read access watch in PREGION[1]
impl W<u32, Reg<u32, _REGIONENSET>>
[src]
pub fn rgn0wa(&mut self) -> RGN0WA_W<'_>
[src]
Bit 0 - Enable write access watch in region[0]
pub fn rgn0ra(&mut self) -> RGN0RA_W<'_>
[src]
Bit 1 - Enable read access watch in region[0]
pub fn rgn1wa(&mut self) -> RGN1WA_W<'_>
[src]
Bit 2 - Enable write access watch in region[1]
pub fn rgn1ra(&mut self) -> RGN1RA_W<'_>
[src]
Bit 3 - Enable read access watch in region[1]
pub fn rgn2wa(&mut self) -> RGN2WA_W<'_>
[src]
Bit 4 - Enable write access watch in region[2]
pub fn rgn2ra(&mut self) -> RGN2RA_W<'_>
[src]
Bit 5 - Enable read access watch in region[2]
pub fn rgn3wa(&mut self) -> RGN3WA_W<'_>
[src]
Bit 6 - Enable write access watch in region[3]
pub fn rgn3ra(&mut self) -> RGN3RA_W<'_>
[src]
Bit 7 - Enable read access watch in region[3]
pub fn prgn0wa(&mut self) -> PRGN0WA_W<'_>
[src]
Bit 24 - Enable write access watch in PREGION[0]
pub fn prgn0ra(&mut self) -> PRGN0RA_W<'_>
[src]
Bit 25 - Enable read access watch in PREGION[0]
pub fn prgn1wa(&mut self) -> PRGN1WA_W<'_>
[src]
Bit 26 - Enable write access watch in PREGION[1]
pub fn prgn1ra(&mut self) -> PRGN1RA_W<'_>
[src]
Bit 27 - Enable read access watch in PREGION[1]
impl W<u32, Reg<u32, _REGIONENCLR>>
[src]
pub fn rgn0wa(&mut self) -> RGN0WA_W<'_>
[src]
Bit 0 - Disable write access watch in region[0]
pub fn rgn0ra(&mut self) -> RGN0RA_W<'_>
[src]
Bit 1 - Disable read access watch in region[0]
pub fn rgn1wa(&mut self) -> RGN1WA_W<'_>
[src]
Bit 2 - Disable write access watch in region[1]
pub fn rgn1ra(&mut self) -> RGN1RA_W<'_>
[src]
Bit 3 - Disable read access watch in region[1]
pub fn rgn2wa(&mut self) -> RGN2WA_W<'_>
[src]
Bit 4 - Disable write access watch in region[2]
pub fn rgn2ra(&mut self) -> RGN2RA_W<'_>
[src]
Bit 5 - Disable read access watch in region[2]
pub fn rgn3wa(&mut self) -> RGN3WA_W<'_>
[src]
Bit 6 - Disable write access watch in region[3]
pub fn rgn3ra(&mut self) -> RGN3RA_W<'_>
[src]
Bit 7 - Disable read access watch in region[3]
pub fn prgn0wa(&mut self) -> PRGN0WA_W<'_>
[src]
Bit 24 - Disable write access watch in PREGION[0]
pub fn prgn0ra(&mut self) -> PRGN0RA_W<'_>
[src]
Bit 25 - Disable read access watch in PREGION[0]
pub fn prgn1wa(&mut self) -> PRGN1WA_W<'_>
[src]
Bit 26 - Disable write access watch in PREGION[1]
pub fn prgn1ra(&mut self) -> PRGN1RA_W<'_>
[src]
Bit 27 - Disable read access watch in PREGION[1]
impl W<u32, Reg<u32, _MODE>>
[src]
impl W<u32, Reg<u32, _RXEN>>
[src]
impl W<u32, Reg<u32, _TXEN>>
[src]
impl W<u32, Reg<u32, _MCKEN>>
[src]
impl W<u32, Reg<u32, _MCKFREQ>>
[src]
impl W<u32, Reg<u32, _RATIO>>
[src]
impl W<u32, Reg<u32, _SWIDTH>>
[src]
impl W<u32, Reg<u32, _ALIGN>>
[src]
impl W<u32, Reg<u32, _FORMAT>>
[src]
impl W<u32, Reg<u32, _CHANNELS>>
[src]
pub fn channels(&mut self) -> CHANNELS_W<'_>
[src]
Bits 0:1 - Enable channels.
impl W<u32, Reg<u32, _PTR>>
[src]
pub fn ptr(&mut self) -> PTR_W<'_>
[src]
Bits 0:31 - Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address.
impl W<u32, Reg<u32, _PTR>>
[src]
pub fn ptr(&mut self) -> PTR_W<'_>
[src]
Bits 0:31 - Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address.
impl W<u32, Reg<u32, _MAXCNT>>
[src]
pub fn maxcnt(&mut self) -> MAXCNT_W<'_>
[src]
Bits 0:13 - Size of RXD and TXD buffers in number of 32 bit words.
impl W<u32, Reg<u32, _MCK>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SCK>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _LRCK>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SDIN>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _SDOUT>>
[src]
pub fn pin(&mut self) -> PIN_W<'_>
[src]
Bits 0:4 - Pin number
pub fn connect(&mut self) -> CONNECT_W<'_>
[src]
Bit 31 - Connection
impl W<u32, Reg<u32, _INTEN>>
[src]
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]
Bit 1 - Enable or disable interrupt for RXPTRUPD event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 2 - Enable or disable interrupt for STOPPED event
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]
Bit 5 - Enable or disable interrupt for TXPTRUPD event
impl W<u32, Reg<u32, _INTENSET>>
[src]
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]
Bit 1 - Write '1' to Enable interrupt for RXPTRUPD event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 2 - Write '1' to Enable interrupt for STOPPED event
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]
Bit 5 - Write '1' to Enable interrupt for TXPTRUPD event
impl W<u32, Reg<u32, _INTENCLR>>
[src]
pub fn rxptrupd(&mut self) -> RXPTRUPD_W<'_>
[src]
Bit 1 - Write '1' to Disable interrupt for RXPTRUPD event
pub fn stopped(&mut self) -> STOPPED_W<'_>
[src]
Bit 2 - Write '1' to Disable interrupt for STOPPED event
pub fn txptrupd(&mut self) -> TXPTRUPD_W<'_>
[src]
Bit 5 - Write '1' to Disable interrupt for TXPTRUPD event
impl W<u32, Reg<u32, _ENABLE>>
[src]
impl W<u32, Reg<u32, _OUT>>
[src]
pub fn pin0(&mut self) -> PIN0_W<'_>
[src]
Bit 0 - Pin 0
pub fn pin1(&mut self) -> PIN1_W<'_>
[src]
Bit 1 - Pin 1
pub fn pin2(&mut self) -> PIN2_W<'_>
[src]
Bit 2 - Pin 2
pub fn pin3(&mut self) -> PIN3_W<'_>
[src]
Bit 3 - Pin 3
pub fn pin4(&mut self) -> PIN4_W<'_>
[src]
Bit 4 - Pin 4
pub fn pin5(&mut self) -> PIN5_W<'_>
[src]
Bit 5 - Pin 5
pub fn pin6(&mut self) -> PIN6_W<'_>
[src]
Bit 6 - Pin 6
pub fn pin7(&mut self) -> PIN7_W<'_>
[src]
Bit 7 - Pin 7
pub fn pin8(&mut self) -> PIN8_W<'_>
[src]
Bit 8 - Pin 8
pub fn pin9(&mut self) -> PIN9_W<'_>
[src]
Bit 9 - Pin 9
pub fn pin10(&mut self) -> PIN10_W<'_>
[src]
Bit 10 - Pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>
[src]
Bit 11 - Pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>
[src]
Bit 12 - Pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>
[src]
Bit 13 - Pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>
[src]
Bit 14 - Pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>
[src]
Bit 15 - Pin 15
pub fn pin16(&mut self) -> PIN16_W<'_>
[src]
Bit 16 - Pin 16
pub fn pin17(&mut self) -> PIN17_W<'_>
[src]
Bit 17 - Pin 17
pub fn pin18(&mut self) -> PIN18_W<'_>
[src]
Bit 18 - Pin 18
pub fn pin19(&mut self) -> PIN19_W<'_>
[src]
Bit 19 - Pin 19
pub fn pin20(&mut self) -> PIN20_W<'_>
[src]
Bit 20 - Pin 20
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]
Bit 21 - Pin 21
pub fn pin22(&mut self) -> PIN22_W<'_>
[src]
Bit 22 - Pin 22
pub fn pin23(&mut self) -> PIN23_W<'_>
[src]
Bit 23 - Pin 23
pub fn pin24(&mut self) -> PIN24_W<'_>
[src]
Bit 24 - Pin 24
pub fn pin25(&mut self) -> PIN25_W<'_>
[src]
Bit 25 - Pin 25
pub fn pin26(&mut self) -> PIN26_W<'_>
[src]
Bit 26 - Pin 26
pub fn pin27(&mut self) -> PIN27_W<'_>
[src]
Bit 27 - Pin 27
pub fn pin28(&mut self) -> PIN28_W<'_>
[src]
Bit 28 - Pin 28
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]
Bit 29 - Pin 29
pub fn pin30(&mut self) -> PIN30_W<'_>
[src]
Bit 30 - Pin 30
pub fn pin31(&mut self) -> PIN31_W<'_>
[src]
Bit 31 - Pin 31
impl W<u32, Reg<u32, _OUTSET>>
[src]
pub fn pin0(&mut self) -> PIN0_W<'_>
[src]
Bit 0 - Pin 0
pub fn pin1(&mut self) -> PIN1_W<'_>
[src]
Bit 1 - Pin 1
pub fn pin2(&mut self) -> PIN2_W<'_>
[src]
Bit 2 - Pin 2
pub fn pin3(&mut self) -> PIN3_W<'_>
[src]
Bit 3 - Pin 3
pub fn pin4(&mut self) -> PIN4_W<'_>
[src]
Bit 4 - Pin 4
pub fn pin5(&mut self) -> PIN5_W<'_>
[src]
Bit 5 - Pin 5
pub fn pin6(&mut self) -> PIN6_W<'_>
[src]
Bit 6 - Pin 6
pub fn pin7(&mut self) -> PIN7_W<'_>
[src]
Bit 7 - Pin 7
pub fn pin8(&mut self) -> PIN8_W<'_>
[src]
Bit 8 - Pin 8
pub fn pin9(&mut self) -> PIN9_W<'_>
[src]
Bit 9 - Pin 9
pub fn pin10(&mut self) -> PIN10_W<'_>
[src]
Bit 10 - Pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>
[src]
Bit 11 - Pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>
[src]
Bit 12 - Pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>
[src]
Bit 13 - Pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>
[src]
Bit 14 - Pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>
[src]
Bit 15 - Pin 15
pub fn pin16(&mut self) -> PIN16_W<'_>
[src]
Bit 16 - Pin 16
pub fn pin17(&mut self) -> PIN17_W<'_>
[src]
Bit 17 - Pin 17
pub fn pin18(&mut self) -> PIN18_W<'_>
[src]
Bit 18 - Pin 18
pub fn pin19(&mut self) -> PIN19_W<'_>
[src]
Bit 19 - Pin 19
pub fn pin20(&mut self) -> PIN20_W<'_>
[src]
Bit 20 - Pin 20
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]
Bit 21 - Pin 21
pub fn pin22(&mut self) -> PIN22_W<'_>
[src]
Bit 22 - Pin 22
pub fn pin23(&mut self) -> PIN23_W<'_>
[src]
Bit 23 - Pin 23
pub fn pin24(&mut self) -> PIN24_W<'_>
[src]
Bit 24 - Pin 24
pub fn pin25(&mut self) -> PIN25_W<'_>
[src]
Bit 25 - Pin 25
pub fn pin26(&mut self) -> PIN26_W<'_>
[src]
Bit 26 - Pin 26
pub fn pin27(&mut self) -> PIN27_W<'_>
[src]
Bit 27 - Pin 27
pub fn pin28(&mut self) -> PIN28_W<'_>
[src]
Bit 28 - Pin 28
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]
Bit 29 - Pin 29
pub fn pin30(&mut self) -> PIN30_W<'_>
[src]
Bit 30 - Pin 30
pub fn pin31(&mut self) -> PIN31_W<'_>
[src]
Bit 31 - Pin 31
impl W<u32, Reg<u32, _OUTCLR>>
[src]
pub fn pin0(&mut self) -> PIN0_W<'_>
[src]
Bit 0 - Pin 0
pub fn pin1(&mut self) -> PIN1_W<'_>
[src]
Bit 1 - Pin 1
pub fn pin2(&mut self) -> PIN2_W<'_>
[src]
Bit 2 - Pin 2
pub fn pin3(&mut self) -> PIN3_W<'_>
[src]
Bit 3 - Pin 3
pub fn pin4(&mut self) -> PIN4_W<'_>
[src]
Bit 4 - Pin 4
pub fn pin5(&mut self) -> PIN5_W<'_>
[src]
Bit 5 - Pin 5
pub fn pin6(&mut self) -> PIN6_W<'_>
[src]
Bit 6 - Pin 6
pub fn pin7(&mut self) -> PIN7_W<'_>
[src]
Bit 7 - Pin 7
pub fn pin8(&mut self) -> PIN8_W<'_>
[src]
Bit 8 - Pin 8
pub fn pin9(&mut self) -> PIN9_W<'_>
[src]
Bit 9 - Pin 9
pub fn pin10(&mut self) -> PIN10_W<'_>
[src]
Bit 10 - Pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>
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Bit 11 - Pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>
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Bit 12 - Pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>
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Bit 13 - Pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>
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Bit 14 - Pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>
[src]
Bit 15 - Pin 15
pub fn pin16(&mut self) -> PIN16_W<'_>
[src]
Bit 16 - Pin 16
pub fn pin17(&mut self) -> PIN17_W<'_>
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Bit 17 - Pin 17
pub fn pin18(&mut self) -> PIN18_W<'_>
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Bit 18 - Pin 18
pub fn pin19(&mut self) -> PIN19_W<'_>
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Bit 19 - Pin 19
pub fn pin20(&mut self) -> PIN20_W<'_>
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Bit 20 - Pin 20
pub fn pin21(&mut self) -> PIN21_W<'_>
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Bit 21 - Pin 21
pub fn pin22(&mut self) -> PIN22_W<'_>
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Bit 22 - Pin 22
pub fn pin23(&mut self) -> PIN23_W<'_>
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Bit 23 - Pin 23
pub fn pin24(&mut self) -> PIN24_W<'_>
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Bit 24 - Pin 24
pub fn pin25(&mut self) -> PIN25_W<'_>
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Bit 25 - Pin 25
pub fn pin26(&mut self) -> PIN26_W<'_>
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Bit 26 - Pin 26
pub fn pin27(&mut self) -> PIN27_W<'_>
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Bit 27 - Pin 27
pub fn pin28(&mut self) -> PIN28_W<'_>
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Bit 28 - Pin 28
pub fn pin29(&mut self) -> PIN29_W<'_>
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Bit 29 - Pin 29
pub fn pin30(&mut self) -> PIN30_W<'_>
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Bit 30 - Pin 30
pub fn pin31(&mut self) -> PIN31_W<'_>
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Bit 31 - Pin 31
impl W<u32, Reg<u32, _DIR>>
[src]
pub fn pin0(&mut self) -> PIN0_W<'_>
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Bit 0 - Pin 0
pub fn pin1(&mut self) -> PIN1_W<'_>
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Bit 1 - Pin 1
pub fn pin2(&mut self) -> PIN2_W<'_>
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Bit 2 - Pin 2
pub fn pin3(&mut self) -> PIN3_W<'_>
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Bit 3 - Pin 3
pub fn pin4(&mut self) -> PIN4_W<'_>
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Bit 4 - Pin 4
pub fn pin5(&mut self) -> PIN5_W<'_>
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Bit 5 - Pin 5
pub fn pin6(&mut self) -> PIN6_W<'_>
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Bit 6 - Pin 6
pub fn pin7(&mut self) -> PIN7_W<'_>
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Bit 7 - Pin 7
pub fn pin8(&mut self) -> PIN8_W<'_>
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Bit 8 - Pin 8
pub fn pin9(&mut self) -> PIN9_W<'_>
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Bit 9 - Pin 9
pub fn pin10(&mut self) -> PIN10_W<'_>
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Bit 10 - Pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>
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Bit 11 - Pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>
[src]
Bit 12 - Pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>
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Bit 13 - Pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>
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Bit 14 - Pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>
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Bit 15 - Pin 15
pub fn pin16(&mut self) -> PIN16_W<'_>
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Bit 16 - Pin 16
pub fn pin17(&mut self) -> PIN17_W<'_>
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Bit 17 - Pin 17
pub fn pin18(&mut self) -> PIN18_W<'_>
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Bit 18 - Pin 18
pub fn pin19(&mut self) -> PIN19_W<'_>
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Bit 19 - Pin 19
pub fn pin20(&mut self) -> PIN20_W<'_>
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Bit 20 - Pin 20
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]
Bit 21 - Pin 21
pub fn pin22(&mut self) -> PIN22_W<'_>
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Bit 22 - Pin 22
pub fn pin23(&mut self) -> PIN23_W<'_>
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Bit 23 - Pin 23
pub fn pin24(&mut self) -> PIN24_W<'_>
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Bit 24 - Pin 24
pub fn pin25(&mut self) -> PIN25_W<'_>
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Bit 25 - Pin 25
pub fn pin26(&mut self) -> PIN26_W<'_>
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Bit 26 - Pin 26
pub fn pin27(&mut self) -> PIN27_W<'_>
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Bit 27 - Pin 27
pub fn pin28(&mut self) -> PIN28_W<'_>
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Bit 28 - Pin 28
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]
Bit 29 - Pin 29
pub fn pin30(&mut self) -> PIN30_W<'_>
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Bit 30 - Pin 30
pub fn pin31(&mut self) -> PIN31_W<'_>
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Bit 31 - Pin 31
impl W<u32, Reg<u32, _DIRSET>>
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pub fn pin0(&mut self) -> PIN0_W<'_>
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Bit 0 - Set as output pin 0
pub fn pin1(&mut self) -> PIN1_W<'_>
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Bit 1 - Set as output pin 1
pub fn pin2(&mut self) -> PIN2_W<'_>
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Bit 2 - Set as output pin 2
pub fn pin3(&mut self) -> PIN3_W<'_>
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Bit 3 - Set as output pin 3
pub fn pin4(&mut self) -> PIN4_W<'_>
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Bit 4 - Set as output pin 4
pub fn pin5(&mut self) -> PIN5_W<'_>
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Bit 5 - Set as output pin 5
pub fn pin6(&mut self) -> PIN6_W<'_>
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Bit 6 - Set as output pin 6
pub fn pin7(&mut self) -> PIN7_W<'_>
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Bit 7 - Set as output pin 7
pub fn pin8(&mut self) -> PIN8_W<'_>
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Bit 8 - Set as output pin 8
pub fn pin9(&mut self) -> PIN9_W<'_>
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Bit 9 - Set as output pin 9
pub fn pin10(&mut self) -> PIN10_W<'_>
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Bit 10 - Set as output pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>
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Bit 11 - Set as output pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>
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Bit 12 - Set as output pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>
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Bit 13 - Set as output pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>
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Bit 14 - Set as output pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>
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Bit 15 - Set as output pin 15
pub fn pin16(&mut self) -> PIN16_W<'_>
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Bit 16 - Set as output pin 16
pub fn pin17(&mut self) -> PIN17_W<'_>
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Bit 17 - Set as output pin 17
pub fn pin18(&mut self) -> PIN18_W<'_>
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Bit 18 - Set as output pin 18
pub fn pin19(&mut self) -> PIN19_W<'_>
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Bit 19 - Set as output pin 19
pub fn pin20(&mut self) -> PIN20_W<'_>
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Bit 20 - Set as output pin 20
pub fn pin21(&mut self) -> PIN21_W<'_>
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Bit 21 - Set as output pin 21
pub fn pin22(&mut self) -> PIN22_W<'_>
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Bit 22 - Set as output pin 22
pub fn pin23(&mut self) -> PIN23_W<'_>
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Bit 23 - Set as output pin 23
pub fn pin24(&mut self) -> PIN24_W<'_>
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Bit 24 - Set as output pin 24
pub fn pin25(&mut self) -> PIN25_W<'_>
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Bit 25 - Set as output pin 25
pub fn pin26(&mut self) -> PIN26_W<'_>
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Bit 26 - Set as output pin 26
pub fn pin27(&mut self) -> PIN27_W<'_>
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Bit 27 - Set as output pin 27
pub fn pin28(&mut self) -> PIN28_W<'_>
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Bit 28 - Set as output pin 28
pub fn pin29(&mut self) -> PIN29_W<'_>
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Bit 29 - Set as output pin 29
pub fn pin30(&mut self) -> PIN30_W<'_>
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Bit 30 - Set as output pin 30
pub fn pin31(&mut self) -> PIN31_W<'_>
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Bit 31 - Set as output pin 31
impl W<u32, Reg<u32, _DIRCLR>>
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pub fn pin0(&mut self) -> PIN0_W<'_>
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Bit 0 - Set as input pin 0
pub fn pin1(&mut self) -> PIN1_W<'_>
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Bit 1 - Set as input pin 1
pub fn pin2(&mut self) -> PIN2_W<'_>
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Bit 2 - Set as input pin 2
pub fn pin3(&mut self) -> PIN3_W<'_>
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Bit 3 - Set as input pin 3
pub fn pin4(&mut self) -> PIN4_W<'_>
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Bit 4 - Set as input pin 4
pub fn pin5(&mut self) -> PIN5_W<'_>
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Bit 5 - Set as input pin 5
pub fn pin6(&mut self) -> PIN6_W<'_>
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Bit 6 - Set as input pin 6
pub fn pin7(&mut self) -> PIN7_W<'_>
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Bit 7 - Set as input pin 7
pub fn pin8(&mut self) -> PIN8_W<'_>
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Bit 8 - Set as input pin 8
pub fn pin9(&mut self) -> PIN9_W<'_>
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Bit 9 - Set as input pin 9
pub fn pin10(&mut self) -> PIN10_W<'_>
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Bit 10 - Set as input pin 10
pub fn pin11(&mut self) -> PIN11_W<'_>
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Bit 11 - Set as input pin 11
pub fn pin12(&mut self) -> PIN12_W<'_>
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Bit 12 - Set as input pin 12
pub fn pin13(&mut self) -> PIN13_W<'_>
[src]
Bit 13 - Set as input pin 13
pub fn pin14(&mut self) -> PIN14_W<'_>
[src]
Bit 14 - Set as input pin 14
pub fn pin15(&mut self) -> PIN15_W<'_>
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Bit 15 - Set as input pin 15
pub fn pin16(&mut self) -> PIN16_W<'_>
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Bit 16 - Set as input pin 16
pub fn pin17(&mut self) -> PIN17_W<'_>
[src]
Bit 17 - Set as input pin 17
pub fn pin18(&mut self) -> PIN18_W<'_>
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Bit 18 - Set as input pin 18
pub fn pin19(&mut self) -> PIN19_W<'_>
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Bit 19 - Set as input pin 19
pub fn pin20(&mut self) -> PIN20_W<'_>
[src]
Bit 20 - Set as input pin 20
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]
Bit 21 - Set as input pin 21
pub fn pin22(&mut self) -> PIN22_W<'_>
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Bit 22 - Set as input pin 22
pub fn pin23(&mut self) -> PIN23_W<'_>
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Bit 23 - Set as input pin 23
pub fn pin24(&mut self) -> PIN24_W<'_>
[src]
Bit 24 - Set as input pin 24
pub fn pin25(&mut self) -> PIN25_W<'_>
[src]
Bit 25 - Set as input pin 25
pub fn pin26(&mut self) -> PIN26_W<'_>
[src]
Bit 26 - Set as input pin 26
pub fn pin27(&mut self) -> PIN27_W<'_>
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Bit 27 - Set as input pin 27
pub fn pin28(&mut self) -> PIN28_W<'_>
[src]
Bit 28 - Set as input pin 28
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]
Bit 29 - Set as input pin 29
pub fn pin30(&mut self) -> PIN30_W<'_>
[src]
Bit 30 - Set as input pin 30
pub fn pin31(&mut self) -> PIN31_W<'_>
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Bit 31 - Set as input pin 31
impl W<u32, Reg<u32, _LATCH>>
[src]
pub fn pin0(&mut self) -> PIN0_W<'_>
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Bit 0 - Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
pub fn pin1(&mut self) -> PIN1_W<'_>
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Bit 1 - Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
pub fn pin2(&mut self) -> PIN2_W<'_>
[src]
Bit 2 - Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
pub fn pin3(&mut self) -> PIN3_W<'_>
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Bit 3 - Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
pub fn pin4(&mut self) -> PIN4_W<'_>
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Bit 4 - Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
pub fn pin5(&mut self) -> PIN5_W<'_>
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Bit 5 - Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
pub fn pin6(&mut self) -> PIN6_W<'_>
[src]
Bit 6 - Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
pub fn pin7(&mut self) -> PIN7_W<'_>
[src]
Bit 7 - Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
pub fn pin8(&mut self) -> PIN8_W<'_>
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Bit 8 - Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
pub fn pin9(&mut self) -> PIN9_W<'_>
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Bit 9 - Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
pub fn pin10(&mut self) -> PIN10_W<'_>
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Bit 10 - Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
pub fn pin11(&mut self) -> PIN11_W<'_>
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Bit 11 - Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
pub fn pin12(&mut self) -> PIN12_W<'_>
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Bit 12 - Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
pub fn pin13(&mut self) -> PIN13_W<'_>
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Bit 13 - Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
pub fn pin14(&mut self) -> PIN14_W<'_>
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Bit 14 - Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
pub fn pin15(&mut self) -> PIN15_W<'_>
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Bit 15 - Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
pub fn pin16(&mut self) -> PIN16_W<'_>
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Bit 16 - Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
pub fn pin17(&mut self) -> PIN17_W<'_>
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Bit 17 - Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
pub fn pin18(&mut self) -> PIN18_W<'_>
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Bit 18 - Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
pub fn pin19(&mut self) -> PIN19_W<'_>
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Bit 19 - Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
pub fn pin20(&mut self) -> PIN20_W<'_>
[src]
Bit 20 - Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
pub fn pin21(&mut self) -> PIN21_W<'_>
[src]
Bit 21 - Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
pub fn pin22(&mut self) -> PIN22_W<'_>
[src]
Bit 22 - Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
pub fn pin23(&mut self) -> PIN23_W<'_>
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Bit 23 - Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
pub fn pin24(&mut self) -> PIN24_W<'_>
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Bit 24 - Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
pub fn pin25(&mut self) -> PIN25_W<'_>
[src]
Bit 25 - Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
pub fn pin26(&mut self) -> PIN26_W<'_>
[src]
Bit 26 - Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
pub fn pin27(&mut self) -> PIN27_W<'_>
[src]
Bit 27 - Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
pub fn pin28(&mut self) -> PIN28_W<'_>
[src]
Bit 28 - Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
pub fn pin29(&mut self) -> PIN29_W<'_>
[src]
Bit 29 - Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
pub fn pin30(&mut self) -> PIN30_W<'_>
[src]
Bit 30 - Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
pub fn pin31(&mut self) -> PIN31_W<'_>
[src]
Bit 31 - Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
impl W<u32, Reg<u32, _DETECTMODE>>
[src]
pub fn detectmode(&mut self) -> DETECTMODE_W<'_>
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Bit 0 - Select between default DETECT signal behaviour and LDETECT mode
impl W<u32, Reg<u32, _PIN_CNF>>
[src]
pub fn dir(&mut self) -> DIR_W<'_>
[src]
Bit 0 - Pin direction. Same physical register as DIR register
pub fn input(&mut self) -> INPUT_W<'_>
[src]
Bit 1 - Connect or disconnect input buffer
pub fn pull(&mut self) -> PULL_W<'_>
[src]
Bits 2:3 - Pull configuration
pub fn drive(&mut self) -> DRIVE_W<'_>
[src]
Bits 8:10 - Drive configuration
pub fn sense(&mut self) -> SENSE_W<'_>
[src]
Bits 16:17 - Pin sensing mechanism
Auto Trait Implementations
impl<U, REG> Send for W<U, REG> where
REG: Send,
U: Send,
REG: Send,
U: Send,
impl<U, REG> Sync for W<U, REG> where
REG: Sync,
U: Sync,
REG: Sync,
U: Sync,
impl<U, REG> Unpin for W<U, REG> where
REG: Unpin,
U: Unpin,
REG: Unpin,
U: Unpin,
Blanket Implementations
impl<T> Any for T where
T: 'static + ?Sized,
[src]
T: 'static + ?Sized,
impl<T> Borrow<T> for T where
T: ?Sized,
[src]
T: ?Sized,
impl<T> BorrowMut<T> for T where
T: ?Sized,
[src]
T: ?Sized,
pub fn borrow_mut(&mut self) -> &mut T
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impl<T> From<T> for T
[src]
impl<T, U> Into<U> for T where
U: From<T>,
[src]
U: From<T>,
impl<Src, Dst> LosslessTryInto<Dst> for Src where
Dst: LosslessTryFrom<Src>,
[src]
Dst: LosslessTryFrom<Src>,
pub fn lossless_try_into(self) -> Option<Dst>
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impl<Src, Dst> LossyInto<Dst> for Src where
Dst: LossyFrom<Src>,
[src]
Dst: LossyFrom<Src>,
pub fn lossy_into(self) -> Dst
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impl<T> Same<T> for T
type Output = T
Should always be Self
impl<T, U> TryFrom<U> for T where
U: Into<T>,
[src]
U: Into<T>,
type Error = Infallible
The type returned in the event of a conversion error.
pub fn try_from(value: U) -> Result<T, <T as TryFrom<U>>::Error>
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impl<T, U> TryInto<U> for T where
U: TryFrom<T>,
[src]
U: TryFrom<T>,