Struct ReadFifo

pub struct ReadFifo<T: NativeFpgaType> { /* private fields */ }

A FIFO that can be read from.

Implementations

impl<T: NativeFpgaType + 'static> ReadFifo<T>

pub const fn new(address: u32) -> Self

pub fn read( &mut self, session: &impl FifoInterface<T>, timeout: Option<Duration>, data: &mut [T], ) -> Result<usize, FPGAError>

Read from the FIFO into the provided buffer. The size of the read is determined by the size of the data slice.

The timeout can be None to indicate an infinite timeout or a Duration to indicate a timeout.

Returns the number of elements still to be read.

Example

use std::time::Duration;

let session = Session::new("main.lvbitx", "sig", "RIO0").unwrap();
let mut fifo = ReadFifo::<u64>::new(1);
let mut buffer = [0u64; 10];
let remaining = fifo.read(&session, Some(Duration::from_millis(100)), &mut buffer).unwrap();

pub fn get_read_region<'d, 's: 'd>( &'d mut self, session: &'s impl FifoInterface<T>, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'s, 'd, T>, usize), FPGAError>

Provides a mechanism to read from the FIFO without copying the data.

This function returns a read region. This contains a view of the data in the DMA driver. It also returns the number of elements remaining in the buffer.

The timeout can be None to indicate an infinite timeout or a Duration to indicate a timeout.

To write to the FPGA you must overwrite the elements in the region and then drop it.

Example

let session = Session::new("main.lvbitx", "sig", "RIO0").unwrap();
let mut fifo = ReadFifo::<u64>::new(1);
let (read_region, remaining) = fifo.get_read_region(&session, 1000, None).unwrap();
// Do something with the data in the read region.
println!("{:?}", read_region.elements);
// Drop the read region to commit the data back to the DMA driver.
drop(read_region);

pub fn elements_available( &self, session: &impl FifoInterface<T>, ) -> Result<usize, FPGAError>

Returns the number of elements available to read.

Warning: This achieves this by reading zero elements from the FIFO so it will start the FIFO if stopped.

Trait Implementations

impl<T: NativeFpgaType> Fifo for ReadFifo<T>

fn address(&self) -> u32

fn start(&mut self, session: &Session) -> Result<(), FPGAError>

Begins DMA data transfer between the FPGA target and the host computer. This method is optional. This method is optional as the DMA is automatically started when you attempt to read or write.

fn stop(&mut self, session: &Session) -> Result<(), FPGAError>

Stops the DMA data transfer between the FPGA target and the host computer. This method deletes all data from the host memory and FPGA parts of the FIFO.

fn configure( &mut self, session: &Session, requested_depth: usize, ) -> Result<usize, FPGAError>

Specifies the capacity, or depth, in elements of the host FIFO of the DMA channel. The new depth is implemented when the next FIFO Start, FIFO Read, or FIFO Write method executes. Before the new depth is set, the driver empties all data from the host memory and FPGA FIFO.

fn get_peer_to_peer_fifo_endpoint( &self, session: &Session, ) -> Result<u32, FPGAError>