Struct Session

pub struct Session {
    pub handle: u32,
    /* private fields */
}

Fields

handle: u32

Implementations

impl Session

pub fn create_irq_context(&self) -> Result<IrqContext<'_>, FPGAError>

Creates an IRQ Context for the session.

You can create multiple contexts but each context can only be used by one thread at a time.

The context is then used to wait on specific IRQs. See IrqContext.

To minimize jitter when first waiting on IRQs, reserve as many contexts as the application requires.

pub fn acknowledge_irqs(&self, irqs: IrqSelection) -> Result<(), FPGAError>

Acknowledge the specified IRQs. See IrqSelection for details on setting specific IRQs.

impl Session

pub fn configure_fifo( &self, fifo: u32, requested_depth: usize, ) -> Result<usize, FPGAError>

Specify the depth of the host memory part of the FIFO.

Returns the actual size configured which may be larger than the request.

pub fn start_fifo(&self, fifo: u32) -> Result<(), FPGAError>

Start the FIFO.

pub fn stop_fifo(&self, fifo: u32) -> Result<(), FPGAError>

Stop the FIFO.

pub fn release_fifo_elements( &self, fifo: u32, number_of_elements: usize, ) -> Result<(), FPGAError>

Releases previously acquired FIFO elements. The FPGA target cannot read elements acquired by the host. Therefore, the host must release elements after acquiring them.

Always release all acquired elements before closing the session. Do not attempt to access FIFO elements after the elements are released or the session is closed.

pub fn get_peer_to_peer_fifo_endpoint( &self, fifo: u32, ) -> Result<u32, FPGAError>

Gets the endpoint number of a peer-to-peer FIFO.

impl Session

pub fn new( context: &Arc<NiFpgaContext>, bitfile: &str, signature: &str, resource: &str, options: &SessionOptions, ) -> Result<Self, FPGAError>

Create a new session for the specified bitfile and resource.

You must have an open context to construct the session.

The bitfile is the compiled FPGA VI and can be provided as a relative or absolute path.

The session options specify run and reset behaviour for the session. You can use default to run on start and reset on end.

Example

use ni_fpga_interface::session::{NiFpgaContext, Session};

let fpga_context = NiFpgaContext::new().unwrap();
let session = Session::new(
   &fpga_context,
  "./NiFpga_Main.lvbitx",
 "signature",
"RIO0",
&Default::default(),
).unwrap();

pub fn set_options(&mut self, options: &SessionOptions)

Update the session options if you want to change the close behaviour.

Example

use ni_fpga_interface::session::{NiFpgaContext, Session, SessionOptions};


session.set_options(&SessionOptions { reset_on_close: false, ..Default::default() });

pub fn reset(&mut self) -> Result<(), FPGAError>

Reset the FPGA back to it’s initial state.

pub fn run(&mut self, wait_until_done: bool) -> Result<(), FPGAError>

Runs the FPGA on the target. If wait_until_done is true this function will block until the FPGA is done running.

pub fn abort(&mut self) -> Result<(), FPGAError>

Abort the FPGA VI.

pub fn download(&mut self) -> Result<(), FPGAError>

Re-download the bitfile to the FPGA.

pub fn close(self) -> Result<(), FPGAError>

Close the session to the FPGA and resets it if set for the session.

Trait Implementations

impl Drop for Session

fn drop(&mut self)

Executes the destructor for this type.

impl FifoInterface<f32> for Session

fn read_fifo( &self, fifo: u32, data: &mut [f32], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[f32], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, f32>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, f32>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<f64> for Session

fn read_fifo( &self, fifo: u32, data: &mut [f64], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[f64], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, f64>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, f64>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<i16> for Session

fn read_fifo( &self, fifo: u32, data: &mut [i16], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[i16], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, i16>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, i16>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<i32> for Session

fn read_fifo( &self, fifo: u32, data: &mut [i32], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[i32], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, i32>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, i32>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<i64> for Session

fn read_fifo( &self, fifo: u32, data: &mut [i64], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[i64], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, i64>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, i64>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<i8> for Session

fn read_fifo( &self, fifo: u32, data: &mut [i8], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[i8], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, i8>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, i8>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<u16> for Session

fn read_fifo( &self, fifo: u32, data: &mut [u16], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[u16], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, u16>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, u16>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<u32> for Session

fn read_fifo( &self, fifo: u32, data: &mut [u32], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[u32], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, u32>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, u32>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<u64> for Session

fn read_fifo( &self, fifo: u32, data: &mut [u64], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[u64], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, u64>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, u64>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl FifoInterface<u8> for Session

fn read_fifo( &self, fifo: u32, data: &mut [u8], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Reads the elements into the provided buffer up to the size of the buffer.

fn write_fifo( &self, fifo: u32, data: &[u8], timeout: Option<Duration>, ) -> Result<usize, FPGAError>

Writes the elements to the FPGA from the data slice.

fn zero_copy_read( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoReadRegion<'_, '_, u8>, usize), FPGAError>

Provides a region of memory to read from the FIFO.

fn zero_copy_write( &self, fifo: u32, elements: usize, timeout: Option<Duration>, ) -> Result<(FifoWriteRegion<'_, '_, u8>, usize), FPGAError>

Provides a region of memory to write to the FIFO.

impl RegisterInterface<f32> for Session

fn read(&self, address: RegisterAddress) -> Result<f32, FPGAError>

fn write(&self, address: RegisterAddress, value: f32) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [f32; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[f32; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<f64> for Session

fn read(&self, address: RegisterAddress) -> Result<f64, FPGAError>

fn write(&self, address: RegisterAddress, value: f64) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [f64; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[f64; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<i16> for Session

fn read(&self, address: RegisterAddress) -> Result<i16, FPGAError>

fn write(&self, address: RegisterAddress, value: i16) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [i16; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[i16; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<i32> for Session

fn read(&self, address: RegisterAddress) -> Result<i32, FPGAError>

fn write(&self, address: RegisterAddress, value: i32) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [i32; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[i32; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<i64> for Session

fn read(&self, address: RegisterAddress) -> Result<i64, FPGAError>

fn write(&self, address: RegisterAddress, value: i64) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [i64; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[i64; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<i8> for Session

fn read(&self, address: RegisterAddress) -> Result<i8, FPGAError>

fn write(&self, address: RegisterAddress, value: i8) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [i8; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[i8; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<u16> for Session

fn read(&self, address: RegisterAddress) -> Result<u16, FPGAError>

fn write(&self, address: RegisterAddress, value: u16) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [u16; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[u16; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<u32> for Session

fn read(&self, address: RegisterAddress) -> Result<u32, FPGAError>

fn write(&self, address: RegisterAddress, value: u32) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [u32; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[u32; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<u64> for Session

fn read(&self, address: RegisterAddress) -> Result<u64, FPGAError>

fn write(&self, address: RegisterAddress, value: u64) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [u64; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[u64; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>

impl RegisterInterface<u8> for Session

fn read(&self, address: RegisterAddress) -> Result<u8, FPGAError>

fn write(&self, address: RegisterAddress, value: u8) -> Result<(), FPGAError>

fn read_array_mut<const N: usize>( &self, address: RegisterAddress, array: &mut [u8; N], ) -> Result<(), FPGAError>

fn write_array<const N: usize>( &self, address: RegisterAddress, value: &[u8; N], ) -> Result<(), FPGAError>

fn read_array<const N: usize>( &self, address: RegisterAddress, ) -> Result<[T; N], FPGAError>