Struct __mss_mac_cfg_t 

#[repr(C)]
pub struct __mss_mac_cfg_t {

    pub interface_type: u32,
    pub phy_type: u32,
    pub phy_init: mss_mac_phy_init_t,
    pub phy_set_link_speed: mss_mac_phy_set_speed_t,
    pub phy_autonegotiate: mss_mac_phy_autonegotiate_t,
    pub phy_mac_autonegotiate: mss_mac_phy_autonegotiate_t,
    pub phy_get_link_status: mss_mac_phy_get_link_status_t,
    pub phy_extended_read: mss_mac_phy_extended_read_t,
    pub phy_extended_write: mss_mac_phy_extended_write_t,
    pub queue_enable: [u32; 4],
    pub speed_mode: mss_mac_speed_mode_t,
    pub speed_duplex_select: u32,
    pub mac_addr: [u8; 6],
    pub phy_addr: u32,
    pub pcs_phy_addr: u32,
    pub phy_controller: *mut mss_mac_instance,
    pub tx_edc_enable: u32,
    pub rx_edc_enable: u32,
    pub jumbo_frame_enable: u32,
    pub jumbo_frame_default: u32,
    pub length_field_check: u32,
    pub append_CRC: u32,
    pub fullduplex: u32,
    pub loopback: u32,
    pub rx_flow_ctrl: u32,
    pub tx_flow_ctrl: u32,
    pub ipg_multiplier: u32,
    pub ipg_divisor: u32,
    pub phyclk: u32,
    pub max_frame_length: u32,
    pub use_hi_address: u32,
    pub use_local_ints: u32,
    pub queue0_int_priority: u32,
    pub queue1_int_priority: u32,
    pub queue2_int_priority: u32,
    pub queue3_int_priority: u32,
    pub mmsl_int_priority: u32,
    pub tsu_clock_select: u32,
    pub amba_burst_length: u32,
}

//** PolarFire SoC MSS Ethernet MAC Configuration Structure.

The mss_mac_cfg_t type contains the initial configuration values for the MPFS Ethernet MAC. You need to create a record of this type to hold the configuration of the MAC. MSS_MAC_cfg_struct_def_init() is used to initialize the configuration record to default values. Later, the configuration elements in the record can be changed to desired values before passing them to MSS_MAC_init().

Note: Even though most of these values are small, we use uint32_t for most values here as they will be used in calculations that are based on uint32_t values and this avoids having to put casts everywhere…

interface_type: This indicates the type of interface between the MAC and the PHY. The currently supported values are:

• NULL_PHY – No PHY involved, usually for direct connection via the fabric.
• GMII – Connection via GMII routed through the fabric to external PHY device.
• TBI – Connection via SGMII block to external PHY device.
• GMII_SGMII – Emulation platform specific option using SGMII to GMII bridge.

phy_type: This indicates the type of PHY device connected to the MAC. The currently supported values are:

• MSS_MAC_DEV_PHY_NULL – No PHY device.
• MSS_MAC_DEV_PHY_VSC8575 – VSC8575 with full VTSS API.
• MSS_MAC_DEV_PHY_VSC8575_LITE – VSC8757 with Lite VTSS API.
• MSS_MAC_DEV_PHY_VSC8541 – VSC8541 without VTSS API.
• MSS_MAC_DEV_PHY_VSC8662 – VSC88662 without VTSS API.
• MSS_MAC_DEV_PHY_DP83867 – TI DP83867.

phy_init phy_set_link_speed phy_autonegotiate phy_autonegotiate_mac phy_get_link_status phy_extended_read phy_init_extended_write: These are callback functions for the PHY support within the driver. These should be set to the appropriate PHY driver functions for the attached PHY device. See mss_mac_phy_init_t, mss_mac_phy_set_speed_t, mss_mac_phy_autonegotiate_t, mss_mac_phy_get_link_status_t, mss_mac_phy_extended_read_t and mss_mac_phy_extended_write_t for details.

queue_enable: This array of values of length MSS_MAC_QUEUE_COUNT, indicates which queues are to be enabled. 0 in an entry indicates disabled and 1 indicates enabled.

speed_mode: This parameter specifies the mode of operation for the Ethernet interface. The following values are supported:

• MSS_MAC_SPEED_AN
• MSS_MAC_10_HDX
• MSS_MAC_10_FDX
• MSS_MAC_100_HDX
• MSS_MAC_100_FDX
• MSS_MAC_1000_HDX
• MSS_MAC_1000_FDX

If MSS_MAC_SPEED_AN is selected then the speed_duplex_select configuration parameter indicates the allowed speed combinations. For all other modes, the link autonegotiation is disabled.

speed_duplex_select: This configuration parameter specifies the allowed link speeds when autonegotiation is enabled. It is a bit-mask of the various link speed and duplex modes. The speed_duplex_select configuration can be set to a bitmask of the following defines to specify the allowed link speed and duplex mode:

• MSS_MAC_ANEG_10M_FD
• MSS_MAC_ANEG_10M_HD
• MSS_MAC_ANEG_100M_FD
• MSS_MAC_ANEG_100M_HD
• MSS_MAC_ANEG_1000M_FD
• MSS_MAC_ANEG_1000M_HD

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_ANEG_ALL_SPEEDS indicating that a link will be setup for best available speed and duplex combination.

mac_addr: This configuration parameter is a 6-byte array containing the local MAC address of the Ethernet MAC. For correct operation, this value should be unique for each of the 4 MAC elements within the MSS and if more than one system containing an MPFS device is present on a LAN then the MAC addresses must all be unique. Tha management and allocation of the MAC addresses is left up to the user.

phy_address: This parameter specifies the address of the PHY device, usually set in hardware by the address pins of the PHY device.

pcs_phy_address: This parameter specifies the address of the control device for hidden SGMII type interfaces such as that in the G5 SoC emulation platform.

phy_soft_reset_gpio: Identifies the MSS GPIO device that the PHY soft reset pin is connected to. A Value of NULL indicates the soft reset signal is not available for control via an MSS GPIO pin.

phy_soft_reset_pin: Identifies the MSS GPIO pin that the PHY soft reset pin is connected to.

phy_hard_reset_gpio: Identifies the MSS GPIO device that the PHY hard reset pin is connected to. A Value of NULL indicates the hard reset signal is not available for control via an MSS GPIO pin.

phy_hard_reset_pin: Identifies the MSS GPIO pin that the PHY hard reset pin is connected to.

phy_controller: Pointer to the MAC instance structure to which the PHY is connected. This supports the use of multi-port PHY devices which may be connected to a single MAC device or configurations where only a single MDIO interface is exposed to the outside world. If NULL, the current MAC device is used.

In configurations that use this feature, it is important that the MAC device that the PHY is connected to is initialized first.

tx_edc_enable: This parameter specifies enable or disable error detection and correction for tx FIFOs. The allowed values for the tx_edc_enable configuration parameter are:

• MSS_MAC_ERR_DET_CORR_ENABLE
• MSS_MAC_ERR_DET_CORR_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_ERR_DET_CORR_DISABLE.

rx_edc_enable: This parameter specifies enable or disable error detection and correction for rx FIFOs. The allowed values for the rx_edc_enable configuration parameter are:

• MSS_MAC_ERR_DET_CORR_ENABLE
• MSS_MAC_ERR_DET_CORR_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_ERR_DET_CORR_DISABLE.

jumbo_frame_enable: This parameter allows enabling or disabling jumbo frame support. When enabled, it allows frames longer than the standard 1536 byte maximum frame length to be transmitted and received. When disabled, the MAC limits the length of frames at the maximum frame length. The allowed values for the jumbo_frame_enable configuration parameter are:

• MSS_MAC_JUMBO_FRAME_ENABLE
• MSS_MAC_JUMBO_FRAME_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_JUMBO_FRAME_DISABLE.

jumbo_frame_default: This parameter sets the initial maximum jumbo frame length. The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_MAX_PACKET_SIZE.

length_field_check: This parameter specifies enable or disable length field check. When enabled, the MAC checks the frame length field of received frames to ensure it matches the actual data field length. The allowed values for the length_field_check configuration parameter are:

• MSS_MAC_LENGTH_FIELD_CHECK_ENABLE
• MSS_MAC_LENGTH_FIELD_CHECK_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_LENGTH_FIELD_CHECK_ENABLE

append_CRC: This parameter specifies enable or disable appending a CRC to transmitted packets. When enabled, the MAC appends a CRC to all frames. When disabled, frames presented to the MAC must have a valid length and contain a valid CRC. The allowed values for the append_CRC parameter are:

• MSS_MAC_CRC_ENABLE
• MSS_MAC_CRC_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_CRC_ENABLE.

fullduplex: This specifies enable or disable full duplex. When enabled, the MAC operates in full duplex mode. When disabled, the MAC operates in half duplex mode. The allowed values for the fullduplex configuration parameter are:

• MSS_MAC_FULLDUPLEX_ENABLE
• MSS_MAC_FULLDUPLEX_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_FULLDUPLEX_ENABLE.

loopback: This parameter specifies enable or disable loop back mode. When enabled, the MAC transmit outputs to be looped back to its receiving inputs. The allowed values for the loopback configuration parameter are:

• MSS_MAC_LOOPBACK_ENABLE
• MSS_MAC_LOOPBACK_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_LOOPBACK_DISABLE.

rx_flow_ctrl: This parameter allows enabling or disabling receiver flow control. When enabled, the MAC detects and acts on PAUSE flow control frames. When disabled, it ignores PAUSE flow control frames. The allowed values for the rx_flow_ctrl configuration parameter are:

• MSS_MAC_RX_FLOW_CTRL_ENABLE
• MSS_MAC_RX_FLOW_CTRL_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_RX_FLOW_CTRL_ENABLE.

tx_flow_ctrl: This parameter allows enabling or disabling transmitter flow control. When enabled, the transmitter sends PAUSE flow control frames when requested by the system. When disabled, prevents the transmitter from sending flow control frames. The allowed values for the tx_flow_ctrl configuration parameter are:

• MSS_MAC_TX_FLOW_CTRL_ENABLE
• MSS_MAC_TX_FLOW_CTRL_DISABLE

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_TX_FLOW_CTRL_ENABLE.

ipg_multiplier ipg_divisor: These parameters specify the minimum size of gap (IPG/IFG) to enforce between frames (expressed in bit times). They are both 8 bit values and are used to calculate an IPG value based on the last packet sent by multiplying the length by ipg_multiplier and dividing the result by ipg_divisor. The resulting number of bits is used if it is greater than the default 96 bits.

To select standard 96 bit IPG, set ipg_multiplier to MSS_MAC_IPG_DEFVAL.

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_IPG_DEFVAL.

phyclk: This parameter specifies the MII management clock divider value. PCLK is the source clock. This should be chosen to ensure that MDC has a frequency that is no greater than 2.5MHz. The allowed values for the phyclk configuration parameter are:

• MSS_MAC_DEF_PHY_CLK
• MSS_MAC_BY8_PHY_CLK
• MSS_MAC_BY16_PHY_CLK
• MSS_MAC_BY32_PHY_CLK
• MSS_MAC_BY48_PHY_CLK
• MSS_MAC_BY64_PHY_CLK
• MSS_MAC_BY96_PHY_CLK
• MSS_MAC_BY128_PHY_CLK
• MSS_MAC_BY224_PHY_CLK

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_DEF_PHY_CLK.

max_frame_length: This parameter specifies the maximum frame size in both the transmit and receive directions. The allowed values for the max_frame_length configuration parameter are:

• MSS_MAC_MAXFRAMELEN_DEFVAL
• MSS_MAC_MAXFRAMELEN_MAXVAL

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to MSS_MAC_MAXFRAMELEN_DEFVAL.

use_hi_address: When set to 0, use_hi_address selects the default AXI slave slot 5 address for the location of the registers of the GEM device. When set to non 0, AXI slave slot 6 is used to access the device.

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to 0.

use_local_ints: When set to 0, use_local_ints selects the PLIC interrupts as the source for interrupts from the GEM. When set to non 0, local interrupts are used. GEM0 is connected to the local interrupts of U54 numbers 1 and 2. GEM1 is connected to the local interrupts of U54 numbers 3 and 4.

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to 0.

queue0_int_priority: queue1_int_priority: queue2_int_priority: queue3_int_priority: mmsl_int_priority: These parameters indicate the interrupt priority to use for each of the interrupt sources that the GEM supports. A priority of 0 effectively disables an interrupt and a priority of 7 is the highest priority that can be assigned.

queue0_int_priority is the priority for the primary queue for the pMAC and the only queue for the eMAC.

The MSS_MAC_cfg_struct_def_init() function sets these configuration parameters to 7.

tsu_clock_select: Selects the TSU clock source. 0 is the default TSU clock source and 1 is the alternative TSU clock source driven from the fabric.

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to 0.

amba_burst_length: Sets the burst length for the DMA AXI data access transfers. Valid values are:

• 0x00 - Attempt to use bursts up to 256
• 0x01 - Always use single bursts
• 0x02 - Always use single bursts
• 0x04 - Attempt to use bursts up to 4
• 0x08 - Attempt to use bursts up to 8
• 0x10 - Attempt to use bursts up to 16

The MSS_MAC_cfg_struct_def_init() function sets this configuration parameter to 0x10 for bursts up to 16.

Fields

interface_type: u32

< Type of network interface associated with this GEM

phy_type: u32

< PHY device type associated with this GEM

phy_init: mss_mac_phy_init_t

< Pointer to PHY init function

phy_set_link_speed: mss_mac_phy_set_speed_t

< Pointer to PHY set link speed function

phy_autonegotiate: mss_mac_phy_autonegotiate_t

< Pointer to PHY initiate autonegotiation function

phy_mac_autonegotiate: mss_mac_phy_autonegotiate_t

< Pointer to PHY initiate autonegotiation for SGMII link function

phy_get_link_status: mss_mac_phy_get_link_status_t

< Pointer to PHY get link status function

phy_extended_read: mss_mac_phy_extended_read_t

< Pointer to PHY extended read function

phy_extended_write: mss_mac_phy_extended_write_t

< Pointer to PHY extended write function

queue_enable: [u32; 4]

< Enables for additional queues

speed_mode: mss_mac_speed_mode_t

< Link speed mode of operation

speed_duplex_select: u32

< Link speed and duplex mode allowed to setup a link when autonegotiation is enabled.

mac_addr: [u8; 6]

< Station’s MAC address

phy_addr: u32

< Address of Ethernet PHY on MII management interface.

pcs_phy_addr: u32

< Address of SGMII interface controller on MII management interface.

phy_controller: *mut mss_mac_instance

tx_edc_enable: u32

< Enable / disable error detection and correction for tx FIFOs

rx_edc_enable: u32

< Enable / disable error detection and correction for rx FIFOs

jumbo_frame_enable: u32

< Enable / disable jumbo frame support: default is disable 0

jumbo_frame_default: u32

< Default maximum size for jumbo frames

length_field_check: u32

< Enable / disable length field checking

append_CRC: u32

< Enable / disable appending CRC

fullduplex: u32

< Enable / disable full duplex: default is disable 0

loopback: u32

< Enable / disable loopback mode: default is disable 0

rx_flow_ctrl: u32

< Enable / disable receiver flow control: default is disable 0

tx_flow_ctrl: u32

< Enable / disable transmitter flow control: default is disable 0

ipg_multiplier: u32

< 8-bit IPG multiplication factor, if 0 we disable IPG stretching

ipg_divisor: u32

< 8-bit back to back inter-frame gap value

phyclk: u32

< 3-bit MGMT clock divider value

max_frame_length: u32

< Maximum frame length: default value is 0x0600(1536d)

use_hi_address: u32

< Non 0 means use upper address range for this device

use_local_ints: u32

< non 0 means use local interrupts for MAC instead of PLIC

queue0_int_priority: u32

< Main MAC interrupt

queue1_int_priority: u32

< Queue 1 interrupt

queue2_int_priority: u32

< Queue 2 interrupt

queue3_int_priority: u32

< Queue 3 interrupt

mmsl_int_priority: u32

< MMSL interrupt

tsu_clock_select: u32

< 0 for default TSU clock, 1 for fabric tsu clock

amba_burst_length: u32

< AXI burst length for DMA data transfers

Trait Implementations

impl Clone for __mss_mac_cfg_t

fn clone(&self) -> __mss_mac_cfg_t

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for __mss_mac_cfg_t

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Copy for __mss_mac_cfg_t