mpfs-pac

This is a Peripheral Access Crate (PAC) for the Microchip PolarFire SoC. It is build on the Mirochip-provided platform and bindgen.

Because of this approach, this is a fairly gnarly PAC, with no structure to speak of. On the flip side, there's a lot of advanced functionality available. See https://github.com/polarfire-soc/polarfire-soc-bare-metal-examples for usage examples for the platform.

Currently only the BeagleV-Fire board is supported, but adding new boards is a matter of adding the board-specific files to the mpfs-platform/boards directory and enabling it through a feature flag in build.rs.

Usage

You should almost certainly use this with the mpfs-hal crate, which - if nothing else - provides macros for entrypoints. If you don't want to use the HAL, you must define of the following entrypoints yourself (one for each hart):

• u54_1
• u54_2
• u54_3
• u54_4

Use the MPFS_RESERVED_MEMORY_SIZE environment variable to set the size of the reserved memory region. This amount of memory is reserved at the end of the address space, and is meant to be used by the application for fixed-address, non-heap memory. Defaults to 0x0.

TODO

There's plenty of functionality in platform that isn't yet exposed, either because they are static functions, or defines that aren't recognized by bindgen. I also haven't added all headers to the wrapper, but most MSS peripherals are there.

The docs for this crate are a bit broken, presumably due to some bindgen issue.