Expand description
A VHDL parser.
Re-exports§
pub use self::token_stream::TokenStream;
Modules§
- basic
- This module implements a basic parser that accepts tokens from the VHDL lexer and emits errors back to it.
- rules
- This module implements a first stage recursive descent parser for VHDL. It
can process a stream of input tokens into the coarse, generalized abstract
syntax tree defined in
ast. The grammar productions/rules outlined in the VHDL standard are collapsed into more general rules as outlined in the following table. - token_
stream