Struct Ctimer4

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pub struct Ctimer4 { /* private fields */ }

Expand description

LPC-Next0 Standard async counter/timer

Implementations§

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impl Ctimer4

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pub const PTR: const RegisterBlock = {0x4002c000 as const ctimer0::RegisterBlock}

Pointer to the register block

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pub const fn ptr() -> *const RegisterBlock

Return the pointer to the register block

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pub unsafe fn steal() -> Self

Steal an instance of this peripheral

§Safety

Ensure that the new instance of the peripheral cannot be used in a way that may race with any existing instances, for example by only accessing read-only or write-only registers, or by consuming the original peripheral and using critical sections to coordinate access between multiple new instances.

Additionally, other software such as HALs may rely on only one peripheral instance existing to ensure memory safety; ensure no stolen instances are passed to such software.

Methods from Deref<Target = RegisterBlock>§

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pub fn ir(&self) -> &Ir

0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.

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pub fn tcr(&self) -> &Tcr

0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.

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pub fn tc(&self) -> &Tc

0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.

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pub fn pr(&self) -> &Pr

0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.

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pub fn pc(&self) -> &Pc

0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.

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pub fn mcr(&self) -> &Mcr

0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.

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pub fn mr(&self, n: usize) -> &Mr

0x18..0x28 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

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pub fn mr_iter(&self) -> impl Iterator<Item = &Mr>

Iterator for array of: 0x18..0x28 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.

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pub fn ccr(&self) -> &Ccr

0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.

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pub fn cr(&self, n: usize) -> &Cr

0x2c..0x3c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.

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pub fn cr_iter(&self) -> impl Iterator<Item = &Cr>

Iterator for array of: 0x2c..0x3c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.

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pub fn emr(&self) -> &Emr

0x3c - External Match Register. The EMR controls the match function and the external match pins.

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pub fn ctcr(&self) -> &Ctcr

0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.

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pub fn pwmc(&self) -> &Pwmc

0x74 - PWM Control Register. The PWMCON enables PWM mode for the external match pins.

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pub fn msr(&self, n: usize) -> &Msr

0x78..0x88 - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.

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pub fn msr_iter(&self) -> impl Iterator<Item = &Msr>

Iterator for array of: 0x78..0x88 - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.