mimxrt685s_pac/
ctimer0.rs

1#[repr(C)]
2#[cfg_attr(feature = "debug", derive(Debug))]
3#[doc = "Register block"]
4pub struct RegisterBlock {
5    ir: Ir,
6    tcr: Tcr,
7    tc: Tc,
8    pr: Pr,
9    pc: Pc,
10    mcr: Mcr,
11    mr: [Mr; 4],
12    ccr: Ccr,
13    cr: [Cr; 4],
14    emr: Emr,
15    _reserved10: [u8; 0x30],
16    ctcr: Ctcr,
17    pwmc: Pwmc,
18    msr: [Msr; 4],
19}
20impl RegisterBlock {
21    #[doc = "0x00 - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
22    #[inline(always)]
23    pub const fn ir(&self) -> &Ir {
24        &self.ir
25    }
26    #[doc = "0x04 - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
27    #[inline(always)]
28    pub const fn tcr(&self) -> &Tcr {
29        &self.tcr
30    }
31    #[doc = "0x08 - Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."]
32    #[inline(always)]
33    pub const fn tc(&self) -> &Tc {
34        &self.tc
35    }
36    #[doc = "0x0c - Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
37    #[inline(always)]
38    pub const fn pr(&self) -> &Pr {
39        &self.pr
40    }
41    #[doc = "0x10 - Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
42    #[inline(always)]
43    pub const fn pc(&self) -> &Pc {
44        &self.pc
45    }
46    #[doc = "0x14 - Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
47    #[inline(always)]
48    pub const fn mcr(&self) -> &Mcr {
49        &self.mcr
50    }
51    #[doc = "0x18..0x28 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
52    #[inline(always)]
53    pub const fn mr(&self, n: usize) -> &Mr {
54        &self.mr[n]
55    }
56    #[doc = "Iterator for array of:"]
57    #[doc = "0x18..0x28 - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
58    #[inline(always)]
59    pub fn mr_iter(&self) -> impl Iterator<Item = &Mr> {
60        self.mr.iter()
61    }
62    #[doc = "0x28 - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
63    #[inline(always)]
64    pub const fn ccr(&self) -> &Ccr {
65        &self.ccr
66    }
67    #[doc = "0x2c..0x3c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."]
68    #[inline(always)]
69    pub const fn cr(&self, n: usize) -> &Cr {
70        &self.cr[n]
71    }
72    #[doc = "Iterator for array of:"]
73    #[doc = "0x2c..0x3c - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."]
74    #[inline(always)]
75    pub fn cr_iter(&self) -> impl Iterator<Item = &Cr> {
76        self.cr.iter()
77    }
78    #[doc = "0x3c - External Match Register. The EMR controls the match function and the external match pins."]
79    #[inline(always)]
80    pub const fn emr(&self) -> &Emr {
81        &self.emr
82    }
83    #[doc = "0x70 - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
84    #[inline(always)]
85    pub const fn ctcr(&self) -> &Ctcr {
86        &self.ctcr
87    }
88    #[doc = "0x74 - PWM Control Register. The PWMCON enables PWM mode for the external match pins."]
89    #[inline(always)]
90    pub const fn pwmc(&self) -> &Pwmc {
91        &self.pwmc
92    }
93    #[doc = "0x78..0x88 - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero."]
94    #[inline(always)]
95    pub const fn msr(&self, n: usize) -> &Msr {
96        &self.msr[n]
97    }
98    #[doc = "Iterator for array of:"]
99    #[doc = "0x78..0x88 - Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero."]
100    #[inline(always)]
101    pub fn msr_iter(&self) -> impl Iterator<Item = &Msr> {
102        self.msr.iter()
103    }
104}
105#[doc = "IR (rw) register accessor: Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.\n\nYou can [`read`](crate::Reg::read) this register and get [`ir::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ir::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ir`]
106module"]
107#[doc(alias = "IR")]
108pub type Ir = crate::Reg<ir::IrSpec>;
109#[doc = "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending."]
110pub mod ir;
111#[doc = "TCR (rw) register accessor: Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.\n\nYou can [`read`](crate::Reg::read) this register and get [`tcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tcr`]
112module"]
113#[doc(alias = "TCR")]
114pub type Tcr = crate::Reg<tcr::TcrSpec>;
115#[doc = "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR."]
116pub mod tcr;
117#[doc = "TC (rw) register accessor: Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR.\n\nYou can [`read`](crate::Reg::read) this register and get [`tc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`tc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@tc`]
118module"]
119#[doc(alias = "TC")]
120pub type Tc = crate::Reg<tc::TcSpec>;
121#[doc = "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of the APB bus clock. The TC is controlled through the TCR."]
122pub mod tc;
123#[doc = "PR (rw) register accessor: Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.\n\nYou can [`read`](crate::Reg::read) this register and get [`pr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pr`]
124module"]
125#[doc(alias = "PR")]
126pub type Pr = crate::Reg<pr::PrSpec>;
127#[doc = "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC."]
128pub mod pr;
129#[doc = "PC (rw) register accessor: Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.\n\nYou can [`read`](crate::Reg::read) this register and get [`pc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pc`]
130module"]
131#[doc(alias = "PC")]
132pub type Pc = crate::Reg<pc::PcSpec>;
133#[doc = "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface."]
134pub mod pc;
135#[doc = "MCR (rw) register accessor: Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.\n\nYou can [`read`](crate::Reg::read) this register and get [`mcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mcr`]
136module"]
137#[doc(alias = "MCR")]
138pub type Mcr = crate::Reg<mcr::McrSpec>;
139#[doc = "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs."]
140pub mod mcr;
141#[doc = "MR (rw) register accessor: Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC.\n\nYou can [`read`](crate::Reg::read) this register and get [`mr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mr`]
142module"]
143#[doc(alias = "MR")]
144pub type Mr = crate::Reg<mr::MrSpec>;
145#[doc = "Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC."]
146pub mod mr;
147#[doc = "CCR (rw) register accessor: Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.\n\nYou can [`read`](crate::Reg::read) this register and get [`ccr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ccr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ccr`]
148module"]
149#[doc(alias = "CCR")]
150pub type Ccr = crate::Reg<ccr::CcrSpec>;
151#[doc = "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place."]
152pub mod ccr;
153#[doc = "CR (r) register accessor: Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input.\n\nYou can [`read`](crate::Reg::read) this register and get [`cr::R`]. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@cr`]
154module"]
155#[doc(alias = "CR")]
156pub type Cr = crate::Reg<cr::CrSpec>;
157#[doc = "Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input."]
158pub mod cr;
159#[doc = "EMR (rw) register accessor: External Match Register. The EMR controls the match function and the external match pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`emr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`emr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@emr`]
160module"]
161#[doc(alias = "EMR")]
162pub type Emr = crate::Reg<emr::EmrSpec>;
163#[doc = "External Match Register. The EMR controls the match function and the external match pins."]
164pub mod emr;
165#[doc = "CTCR (rw) register accessor: Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.\n\nYou can [`read`](crate::Reg::read) this register and get [`ctcr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctcr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@ctcr`]
166module"]
167#[doc(alias = "CTCR")]
168pub type Ctcr = crate::Reg<ctcr::CtcrSpec>;
169#[doc = "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting."]
170pub mod ctcr;
171#[doc = "PWMC (rw) register accessor: PWM Control Register. The PWMCON enables PWM mode for the external match pins.\n\nYou can [`read`](crate::Reg::read) this register and get [`pwmc::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`pwmc::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@pwmc`]
172module"]
173#[doc(alias = "PWMC")]
174pub type Pwmc = crate::Reg<pwmc::PwmcSpec>;
175#[doc = "PWM Control Register. The PWMCON enables PWM mode for the external match pins."]
176pub mod pwmc;
177#[doc = "MSR (rw) register accessor: Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero.\n\nYou can [`read`](crate::Reg::read) this register and get [`msr::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`msr::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@msr`]
178module"]
179#[doc(alias = "MSR")]
180pub type Msr = crate::Reg<msr::MsrSpec>;
181#[doc = "Match Shadow Register . If enabled, the Match Register will be automatically reloaded with the contents of this register whenever the TC is reset to zero."]
182pub mod msr;
mimxrt685s_pac/ctimer0.rs

mimxrt685s_pac/
ctimer0.rs
