Struct FDIV_W 

pub struct FDIV_W<'a> { /* private fields */ }

Field FDIV writer - Functional clock divider, or 0 if no divide. The term “clocks” in this spec then refer to divided clocks. For a 12MHz input (e.g. FRO 12MHz), this would normally be set to generate a 4MHz output (so, 2). For a 1MHz input, it should be 0. Note for internal use: this does not produce a 50/50 duty cycle when non even divide.

Implementations

impl<'a> FDIV_W<'a>

pub fn variant(self, variant: FDIV_A) -> &'a mut W

Writes variant to the field

pub fn fdiv_0(self) -> &'a mut W

No divide

pub fn fdiv_1(self) -> &'a mut W

/2

pub fn fdiv_2(self) -> &'a mut W

/3

pub fn fdiv_3(self) -> &'a mut W

/4

pub fn fdiv_4(self) -> &'a mut W

/5

pub fn fdiv_5(self) -> &'a mut W

/6

pub fn fdiv_7(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_8(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_9(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_10(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_11(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_12(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_13(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_14(self) -> &'a mut W

/(FDIV+1)

pub fn fdiv_15(self) -> &'a mut W

/(FDIV+1)

pub unsafe fn bits(self, value: u8) -> &'a mut W

Writes raw bits to the field