Struct lpc845_pac::adc0::ctrl::ASYNMODE_W [−][src]
pub struct ASYNMODE_W<'a> { /* fields omitted */ }
Expand description
Field ASYNMODE
writer - Select clock mode.
Implementations
Writes variant
to the field
Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.
Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.