Struct lpc845_pac::adc0::ctrl::ASYNMODE_W

pub struct ASYNMODE_W<'a> { /* fields omitted */ }

Field ASYNMODE writer - Select clock mode.

Implementations

impl<'a> ASYNMODE_W<'a>

pub fn variant(self, variant: ASYNMODE_A) -> &'a mut W

Writes variant to the field

pub fn synchronous_mode(self) -> &'a mut W

Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.

pub fn asynchronous_mode(self) -> &'a mut W

Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.

pub fn set_bit(self) -> &'a mut W

Sets the field bit

pub fn clear_bit(self) -> &'a mut W

Clears the field bit

pub fn bit(self, value: bool) -> &'a mut W

Writes raw bits to the field