Enum lpc845_pac::adc0::ctrl::ASYNMODE_A

pub enum ASYNMODE_A {
    SYNCHRONOUS_MODE,
    ASYNCHRONOUS_MODE,
}

Select clock mode.

Value on reset: 0

Variants

SYNCHRONOUS_MODE

0: Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.

ASYNCHRONOUS_MODE

1: Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.

Trait Implementations

impl Clone for ASYNMODE_A

fn clone(&self) -> ASYNMODE_A

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for ASYNMODE_A

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl From<ASYNMODE_A> for bool

fn from(variant: ASYNMODE_A) -> Self

Performs the conversion.

impl PartialEq<ASYNMODE_A> for ASYNMODE_A

fn eq(&self, other: &ASYNMODE_A) -> bool

This method tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

This method tests for !=.

impl Copy for ASYNMODE_A

impl StructuralPartialEq for ASYNMODE_A