Enum lpc845_pac::adc0::ctrl::ASYNMODE_A [−][src]
pub enum ASYNMODE_A {
SYNCHRONOUS_MODE,
ASYNCHRONOUS_MODE,
}
Expand description
Select clock mode.
Value on reset: 0
Variants
0: Synchronous mode. The ADC clock is derived from the system clock based on the divide value selected in the CLKDIV field. The ADC clock will be started in a controlled fashion in response to a trigger to eliminate any uncertainty in the launching of an ADC conversion in response to any synchronous (on-chip) trigger. In Synchronous mode with the SYNCBYPASS bit (in a sequence control register) set, sampling of the ADC input and start of conversion will initiate 2 system clocks after the leading edge of a (synchronous) trigger pulse.
1: Asynchronous mode. The ADC clock is based on the output of the ADC clock divider ADCCLKSEL in the SYSCON block.
Trait Implementations
Performs the conversion.