Struct RegisterBlock 

pub struct RegisterBlock {
    pub lcr: LCR,
    pub mcr: MCR,
    pub lsr: LSR,
    pub msr: MSR,
    pub scr: SCR,
    pub acr: ACR,
    pub fdr: FDR,
    pub ter: TER,
    pub rs485ctrl: RS485CTRL,
    pub rs485adrmatch: RS485ADRMATCH,
    pub rs485dly: RS485DLY,
    /* private fields */
}

Register block

Fields

lcr: LCR

0x0c - Line Control Register. Contains controls for frame formatting and break generation.

mcr: MCR

0x10 - Modem control register

lsr: LSR

0x14 - Line Status Register. Contains flags for transmit and receive status, including line errors.

msr: MSR

0x18 - Modem status register

scr: SCR

0x1c - Scratch Pad Register. Eight-bit temporary storage for software.

acr: ACR

0x20 - Auto-baud Control Register. Contains controls for the auto-baud feature.

fdr: FDR

0x28 - Fractional Divider Register. Generates a clock input for the baud rate divider.

ter: TER

0x30 - Transmit Enable Register. Turns off UART transmitter for use with software flow control.

rs485ctrl: RS485CTRL

0x4c - RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.

rs485adrmatch: RS485ADRMATCH

0x50 - RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.

rs485dly: RS485DLY

0x54 - RS-485/EIA-485 direction control delay.

Implementations

impl RegisterBlock

pub fn dll(&self) -> &DLL

0x00 - Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1.

pub fn thr(&self) -> &THR

0x00 - Transmit Holding Register. The next character to be transmitted is written here. When DLAB=0.

pub fn rbr(&self) -> &RBR

0x00 - Receiver Buffer Register. Contains the next received character to be read. When DLAB=0.

pub fn ier(&self) -> &IER

0x04 - Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0.

pub fn dlm(&self) -> &DLM

0x04 - Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1.

pub fn fcr(&self) -> &FCR

0x08 - FIFO Control Register. Controls UART FIFO usage and modes.

pub fn iir(&self) -> &IIR

0x08 - Interrupt ID Register. Identifies which interrupt(s) are pending.