lpc13xx_pac/lpc1313/
uart.rs

1#[doc = r"Register block"]
2#[repr(C)]
3pub struct RegisterBlock {
4    _reserved_0_dll: [u8; 0x04],
5    _reserved_1_dlm: [u8; 0x04],
6    _reserved_2_fcr: [u8; 0x04],
7    #[doc = "0x0c - Line Control Register. Contains controls for frame formatting and break generation."]
8    pub lcr: LCR,
9    #[doc = "0x10 - Modem control register"]
10    pub mcr: MCR,
11    #[doc = "0x14 - Line Status Register. Contains flags for transmit and receive status, including line errors."]
12    pub lsr: LSR,
13    #[doc = "0x18 - Modem status register"]
14    pub msr: MSR,
15    #[doc = "0x1c - Scratch Pad Register. Eight-bit temporary storage for software."]
16    pub scr: SCR,
17    #[doc = "0x20 - Auto-baud Control Register. Contains controls for the auto-baud feature."]
18    pub acr: ACR,
19    _reserved9: [u8; 0x04],
20    #[doc = "0x28 - Fractional Divider Register. Generates a clock input for the baud rate divider."]
21    pub fdr: FDR,
22    _reserved10: [u8; 0x04],
23    #[doc = "0x30 - Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
24    pub ter: TER,
25    _reserved11: [u8; 0x18],
26    #[doc = "0x4c - RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
27    pub rs485ctrl: RS485CTRL,
28    #[doc = "0x50 - RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
29    pub rs485adrmatch: RS485ADRMATCH,
30    #[doc = "0x54 - RS-485/EIA-485 direction control delay."]
31    pub rs485dly: RS485DLY,
32}
33impl RegisterBlock {
34    #[doc = "0x00 - Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1."]
35    #[inline(always)]
36    pub fn dll(&self) -> &DLL {
37        unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const DLL) }
38    }
39    #[doc = "0x00 - Transmit Holding Register. The next character to be transmitted is written here. When DLAB=0."]
40    #[inline(always)]
41    pub fn thr(&self) -> &THR {
42        unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const THR) }
43    }
44    #[doc = "0x00 - Receiver Buffer Register. Contains the next received character to be read. When DLAB=0."]
45    #[inline(always)]
46    pub fn rbr(&self) -> &RBR {
47        unsafe { &*(((self as *const Self) as *const u8).add(0usize) as *const RBR) }
48    }
49    #[doc = "0x04 - Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0."]
50    #[inline(always)]
51    pub fn ier(&self) -> &IER {
52        unsafe { &*(((self as *const Self) as *const u8).add(4usize) as *const IER) }
53    }
54    #[doc = "0x04 - Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1."]
55    #[inline(always)]
56    pub fn dlm(&self) -> &DLM {
57        unsafe { &*(((self as *const Self) as *const u8).add(4usize) as *const DLM) }
58    }
59    #[doc = "0x08 - FIFO Control Register. Controls UART FIFO usage and modes."]
60    #[inline(always)]
61    pub fn fcr(&self) -> &FCR {
62        unsafe { &*(((self as *const Self) as *const u8).add(8usize) as *const FCR) }
63    }
64    #[doc = "0x08 - Interrupt ID Register. Identifies which interrupt(s) are pending."]
65    #[inline(always)]
66    pub fn iir(&self) -> &IIR {
67        unsafe { &*(((self as *const Self) as *const u8).add(8usize) as *const IIR) }
68    }
69}
70#[doc = "RBR (r) register accessor: an alias for `Reg<RBR_SPEC>`"]
71pub type RBR = crate::Reg<rbr::RBR_SPEC>;
72#[doc = "Receiver Buffer Register. Contains the next received character to be read. When DLAB=0."]
73pub mod rbr;
74#[doc = "THR (w) register accessor: an alias for `Reg<THR_SPEC>`"]
75pub type THR = crate::Reg<thr::THR_SPEC>;
76#[doc = "Transmit Holding Register. The next character to be transmitted is written here. When DLAB=0."]
77pub mod thr;
78#[doc = "DLL (rw) register accessor: an alias for `Reg<DLL_SPEC>`"]
79pub type DLL = crate::Reg<dll::DLL_SPEC>;
80#[doc = "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1."]
81pub mod dll;
82#[doc = "DLM (rw) register accessor: an alias for `Reg<DLM_SPEC>`"]
83pub type DLM = crate::Reg<dlm::DLM_SPEC>;
84#[doc = "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. When DLAB=1."]
85pub mod dlm;
86#[doc = "IER (rw) register accessor: an alias for `Reg<IER_SPEC>`"]
87pub type IER = crate::Reg<ier::IER_SPEC>;
88#[doc = "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts. When DLAB=0."]
89pub mod ier;
90#[doc = "IIR (r) register accessor: an alias for `Reg<IIR_SPEC>`"]
91pub type IIR = crate::Reg<iir::IIR_SPEC>;
92#[doc = "Interrupt ID Register. Identifies which interrupt(s) are pending."]
93pub mod iir;
94#[doc = "FCR (w) register accessor: an alias for `Reg<FCR_SPEC>`"]
95pub type FCR = crate::Reg<fcr::FCR_SPEC>;
96#[doc = "FIFO Control Register. Controls UART FIFO usage and modes."]
97pub mod fcr;
98#[doc = "LCR (rw) register accessor: an alias for `Reg<LCR_SPEC>`"]
99pub type LCR = crate::Reg<lcr::LCR_SPEC>;
100#[doc = "Line Control Register. Contains controls for frame formatting and break generation."]
101pub mod lcr;
102#[doc = "MCR (rw) register accessor: an alias for `Reg<MCR_SPEC>`"]
103pub type MCR = crate::Reg<mcr::MCR_SPEC>;
104#[doc = "Modem control register"]
105pub mod mcr;
106#[doc = "LSR (r) register accessor: an alias for `Reg<LSR_SPEC>`"]
107pub type LSR = crate::Reg<lsr::LSR_SPEC>;
108#[doc = "Line Status Register. Contains flags for transmit and receive status, including line errors."]
109pub mod lsr;
110#[doc = "MSR (r) register accessor: an alias for `Reg<MSR_SPEC>`"]
111pub type MSR = crate::Reg<msr::MSR_SPEC>;
112#[doc = "Modem status register"]
113pub mod msr;
114#[doc = "SCR (rw) register accessor: an alias for `Reg<SCR_SPEC>`"]
115pub type SCR = crate::Reg<scr::SCR_SPEC>;
116#[doc = "Scratch Pad Register. Eight-bit temporary storage for software."]
117pub mod scr;
118#[doc = "ACR (rw) register accessor: an alias for `Reg<ACR_SPEC>`"]
119pub type ACR = crate::Reg<acr::ACR_SPEC>;
120#[doc = "Auto-baud Control Register. Contains controls for the auto-baud feature."]
121pub mod acr;
122#[doc = "FDR (rw) register accessor: an alias for `Reg<FDR_SPEC>`"]
123pub type FDR = crate::Reg<fdr::FDR_SPEC>;
124#[doc = "Fractional Divider Register. Generates a clock input for the baud rate divider."]
125pub mod fdr;
126#[doc = "TER (rw) register accessor: an alias for `Reg<TER_SPEC>`"]
127pub type TER = crate::Reg<ter::TER_SPEC>;
128#[doc = "Transmit Enable Register. Turns off UART transmitter for use with software flow control."]
129pub mod ter;
130#[doc = "RS485CTRL (rw) register accessor: an alias for `Reg<RS485CTRL_SPEC>`"]
131pub type RS485CTRL = crate::Reg<rs485ctrl::RS485CTRL_SPEC>;
132#[doc = "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes."]
133pub mod rs485ctrl;
134#[doc = "RS485ADRMATCH (rw) register accessor: an alias for `Reg<RS485ADRMATCH_SPEC>`"]
135pub type RS485ADRMATCH = crate::Reg<rs485adrmatch::RS485ADRMATCH_SPEC>;
136#[doc = "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode."]
137pub mod rs485adrmatch;
138#[doc = "RS485DLY (rw) register accessor: an alias for `Reg<RS485DLY_SPEC>`"]
139pub type RS485DLY = crate::Reg<rs485dly::RS485DLY_SPEC>;
140#[doc = "RS-485/EIA-485 direction control delay."]
141pub mod rs485dly;
lpc13xx_pac/lpc1313/uart.rs

lpc13xx_pac/lpc1313/
uart.rs
