Enum TargetArchitecture 

pub enum TargetArchitecture {
    X86_64,
    Aarch64,
    Arm32,
    Armv7,
    Thumbv6m,
    Thumbv7m,
    I686,
    Riscv32,
    Riscv64,
    Wasm32,
    Wasm64,
    PowerPC64,
    PowerPC64Be,
    Mips64,
    Mips64El,
    LoongArch64,
    S390x,
    Nvptx64,
    Amdgcn,
}

An architecture lamina has a backend for, or has reserved a name for.

Every property is stated in the table in crate::arch_table; there are no per-property matches anywhere else.

Variants

X86_64

Aarch64

Arm32

32-bit ARM with no revision, float ABI or profile named. Reserved, and refused by FromStr in favour of armv7, thumbv6m and thumbv7m.

Armv7

Thumbv6m

ARMv6-M, Thumb-1 only: Cortex-M0 and M0+.

Thumbv7m

ARMv7-M, Thumb-2: Cortex-M3, M4 and M7.

I686

Riscv32

Riscv64

Wasm32

Wasm64

PowerPC64

Little-endian 64-bit POWER, ELFv2.

PowerPC64Be

Big-endian 64-bit POWER, ELFv2.

Mips64

Mips64El

LoongArch64

S390x

Nvptx64

Amdgcn

Implementations

impl TargetArchitecture

pub const fn spec(self) -> ArchSpec

Everything this architecture states about itself.

pub fn all() -> Vec<Self>

Every architecture in the table, in declaration order.

impl TargetArchitecture

Shorthands for the fields of TargetArchitecture::spec.

Each one reads the table; none of them is a second place a property is decided. A target that carries a variant should read crate::Target::spec instead, which applies the variant’s refinements.

pub const fn pointer_width(self) -> PointerWidth

pub const fn max_int_register_bits(self) -> u32

pub const fn has_64bit_int_registers(self) -> bool

pub const fn endianness(self) -> Endianness

pub const fn va_list(self) -> VaListAbi

pub const fn stack_alignment_at_call(self) -> usize

pub const fn honors_argument_alignment(self) -> bool

pub const fn output_artifact(self) -> OutputArtifact

pub const fn data_layout(self) -> TargetDataLayout

pub const fn default_variant(self) -> ArchVariant

impl TargetArchitecture

pub fn vector_register_bits(self) -> &'static [u32]

Bit widths a vector register of this architecture comes in, ascending.

Empty for an architecture whose backend emits no vector registers, and for a scalable vector machine whose width is not a compile-time constant. A <N x T> whose lanes do not add up to one of these has no register to live in.

Trait Implementations

impl Clone for TargetArchitecture

fn clone(&self) -> Self

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Copy for TargetArchitecture

impl Debug for TargetArchitecture

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Display for TargetArchitecture

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl Eq for TargetArchitecture

impl FromStr for TargetArchitecture

type Err = &'static str

The associated error which can be returned from parsing.

fn from_str(s: &str) -> Result<Self, Self::Err>

Parses a string s to return a value of this type.

impl Hash for TargetArchitecture

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for TargetArchitecture

fn eq(&self, other: &Self) -> bool

Equality operator ==.

fn ne(&self, other: &Rhs) -> bool

Inequality operator !=.

impl StructuralPartialEq for TargetArchitecture