[][src]Struct ksz8863::smi::Smi

pub struct Smi<T>(pub T);

A higher-level wrapper around an smi::Read and/or smi::Write implementation.

Implementations

impl<T> Smi<T>[src]

pub fn chip_id0(&mut self) -> Reg<'_, T, ChipId0>[src]

pub fn chip_id1(&mut self) -> Reg<'_, T, ChipId1>[src]

pub fn gc0(&mut self) -> Reg<'_, T, Gc0>[src]

pub fn gc1(&mut self) -> Reg<'_, T, Gc1>[src]

pub fn gc2(&mut self) -> Reg<'_, T, Gc2>[src]

pub fn gc3(&mut self) -> Reg<'_, T, Gc3>[src]

pub fn gc4(&mut self) -> Reg<'_, T, Gc4>[src]

pub fn gc5(&mut self) -> Reg<'_, T, Gc5>[src]

pub fn gc9(&mut self) -> Reg<'_, T, Gc9>[src]

pub fn gc10(&mut self) -> Reg<'_, T, Gc10>[src]

pub fn gc11(&mut self) -> Reg<'_, T, Gc11>[src]

pub fn gc12(&mut self) -> Reg<'_, T, Gc12>[src]

pub fn gc13(&mut self) -> Reg<'_, T, Gc13>[src]

pub fn port1_ctrl0(&mut self) -> Reg<'_, T, Port1Ctrl0>[src]

pub fn port1_ctrl1(&mut self) -> Reg<'_, T, Port1Ctrl1>[src]

pub fn port1_ctrl2(&mut self) -> Reg<'_, T, Port1Ctrl2>[src]

pub fn port1_ctrl3(&mut self) -> Reg<'_, T, Port1Ctrl3>[src]

pub fn port1_ctrl4(&mut self) -> Reg<'_, T, Port1Ctrl4>[src]

pub fn port1_ctrl5(&mut self) -> Reg<'_, T, Port1Ctrl5>[src]

pub fn port1_q0_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port1Q0IngressRateLimit>
[src]

pub fn port1_q1_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port1Q1IngressRateLimit>
[src]

pub fn port1_q2_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port1Q2IngressRateLimit>
[src]

pub fn port1_q3_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port1Q3IngressRateLimit>
[src]

pub fn port1_phy_special(&mut self) -> Reg<'_, T, Port1PhySpecial>[src]

pub fn port1_ctrl12(&mut self) -> Reg<'_, T, Port1Ctrl12>[src]

pub fn port1_ctrl13(&mut self) -> Reg<'_, T, Port1Ctrl13>[src]

pub fn port1_status0(&mut self) -> Reg<'_, T, Port1Status0>[src]

pub fn port1_status1(&mut self) -> Reg<'_, T, Port1Status1>[src]

pub fn port2_ctrl0(&mut self) -> Reg<'_, T, Port2Ctrl0>[src]

pub fn port2_ctrl1(&mut self) -> Reg<'_, T, Port2Ctrl1>[src]

pub fn port2_ctrl2(&mut self) -> Reg<'_, T, Port2Ctrl2>[src]

pub fn port2_ctrl3(&mut self) -> Reg<'_, T, Port2Ctrl3>[src]

pub fn port2_ctrl4(&mut self) -> Reg<'_, T, Port2Ctrl4>[src]

pub fn port2_ctrl5(&mut self) -> Reg<'_, T, Port2Ctrl5>[src]

pub fn port2_q0_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port2Q0IngressRateLimit>
[src]

pub fn port2_q1_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port2Q1IngressRateLimit>
[src]

pub fn port2_q2_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port2Q2IngressRateLimit>
[src]

pub fn port2_q3_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port2Q3IngressRateLimit>
[src]

pub fn port2_phy_special(&mut self) -> Reg<'_, T, Port2PhySpecial>[src]

pub fn port2_ctrl12(&mut self) -> Reg<'_, T, Port2Ctrl12>[src]

pub fn port2_ctrl13(&mut self) -> Reg<'_, T, Port2Ctrl13>[src]

pub fn port2_status0(&mut self) -> Reg<'_, T, Port2Status0>[src]

pub fn port2_status1(&mut self) -> Reg<'_, T, Port2Status1>[src]

pub fn port3_ctrl0(&mut self) -> Reg<'_, T, Port3Ctrl0>[src]

pub fn port3_ctrl1(&mut self) -> Reg<'_, T, Port3Ctrl1>[src]

pub fn port3_ctrl2(&mut self) -> Reg<'_, T, Port3Ctrl2>[src]

pub fn port3_ctrl3(&mut self) -> Reg<'_, T, Port3Ctrl3>[src]

pub fn port3_ctrl4(&mut self) -> Reg<'_, T, Port3Ctrl4>[src]

pub fn port3_ctrl5(&mut self) -> Reg<'_, T, Port3Ctrl5>[src]

pub fn port3_q0_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port3Q0IngressRateLimit>
[src]

pub fn port3_q1_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port3Q1IngressRateLimit>
[src]

pub fn port3_q2_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port3Q2IngressRateLimit>
[src]

pub fn port3_q3_ingress_rate_limit(
    &mut self
) -> Reg<'_, T, Port3Q3IngressRateLimit>
[src]

pub fn port3_status1(&mut self) -> Reg<'_, T, Port3Status1>[src]

pub fn reset(&mut self) -> Reg<'_, T, Reset>[src]

pub fn tos_priority_ctrl_0(&mut self) -> Reg<'_, T, TosPriorityCtrl0>[src]

pub fn tos_priority_ctrl_1(&mut self) -> Reg<'_, T, TosPriorityCtrl1>[src]

pub fn tos_priority_ctrl_2(&mut self) -> Reg<'_, T, TosPriorityCtrl2>[src]

pub fn tos_priority_ctrl_3(&mut self) -> Reg<'_, T, TosPriorityCtrl3>[src]

pub fn tos_priority_ctrl_4(&mut self) -> Reg<'_, T, TosPriorityCtrl4>[src]

pub fn tos_priority_ctrl_5(&mut self) -> Reg<'_, T, TosPriorityCtrl5>[src]

pub fn tos_priority_ctrl_6(&mut self) -> Reg<'_, T, TosPriorityCtrl6>[src]

pub fn tos_priority_ctrl_7(&mut self) -> Reg<'_, T, TosPriorityCtrl7>[src]

pub fn tos_priority_ctrl_8(&mut self) -> Reg<'_, T, TosPriorityCtrl8>[src]

pub fn tos_priority_ctrl_9(&mut self) -> Reg<'_, T, TosPriorityCtrl9>[src]

pub fn tos_priority_ctrl_10(&mut self) -> Reg<'_, T, TosPriorityCtrl10>[src]

pub fn tos_priority_ctrl_11(&mut self) -> Reg<'_, T, TosPriorityCtrl11>[src]

pub fn tos_priority_ctrl_12(&mut self) -> Reg<'_, T, TosPriorityCtrl12>[src]

pub fn tos_priority_ctrl_13(&mut self) -> Reg<'_, T, TosPriorityCtrl13>[src]

pub fn tos_priority_ctrl_14(&mut self) -> Reg<'_, T, TosPriorityCtrl14>[src]

pub fn tos_priority_ctrl_15(&mut self) -> Reg<'_, T, TosPriorityCtrl15>[src]

pub fn mac_addr_0(&mut self) -> Reg<'_, T, MacAddr0>[src]

pub fn mac_addr_1(&mut self) -> Reg<'_, T, MacAddr1>[src]

pub fn mac_addr_2(&mut self) -> Reg<'_, T, MacAddr2>[src]

pub fn mac_addr_3(&mut self) -> Reg<'_, T, MacAddr3>[src]

pub fn mac_addr_4(&mut self) -> Reg<'_, T, MacAddr4>[src]

pub fn mac_addr_5(&mut self) -> Reg<'_, T, MacAddr5>[src]

pub fn user_def1(&mut self) -> Reg<'_, T, UserDef1>[src]

pub fn user_def2(&mut self) -> Reg<'_, T, UserDef2>[src]

pub fn user_def3(&mut self) -> Reg<'_, T, UserDef3>[src]

pub fn indirect_access_ctrl0(&mut self) -> Reg<'_, T, IndirectAccessCtrl0>[src]

pub fn indirect_access_ctrl1(&mut self) -> Reg<'_, T, IndirectAccessCtrl1>[src]

pub fn indirect_data8(&mut self) -> Reg<'_, T, IndirectData8>[src]

pub fn indirect_data7(&mut self) -> Reg<'_, T, IndirectData7>[src]

pub fn indirect_data6(&mut self) -> Reg<'_, T, IndirectData6>[src]

pub fn indirect_data5(&mut self) -> Reg<'_, T, IndirectData5>[src]

pub fn indirect_data4(&mut self) -> Reg<'_, T, IndirectData4>[src]

pub fn indirect_data3(&mut self) -> Reg<'_, T, IndirectData3>[src]

pub fn indirect_data2(&mut self) -> Reg<'_, T, IndirectData2>[src]

pub fn indirect_data1(&mut self) -> Reg<'_, T, IndirectData1>[src]

pub fn indirect_data0(&mut self) -> Reg<'_, T, IndirectData0>[src]

pub fn station1_mac_addr0(&mut self) -> Reg<'_, T, Station1MacAddr0>[src]

pub fn station1_mac_addr1(&mut self) -> Reg<'_, T, Station1MacAddr1>[src]

pub fn station1_mac_addr2(&mut self) -> Reg<'_, T, Station1MacAddr2>[src]

pub fn station1_mac_addr3(&mut self) -> Reg<'_, T, Station1MacAddr3>[src]

pub fn station1_mac_addr4(&mut self) -> Reg<'_, T, Station1MacAddr4>[src]

pub fn station1_mac_addr5(&mut self) -> Reg<'_, T, Station1MacAddr5>[src]

pub fn station2_mac_addr0(&mut self) -> Reg<'_, T, Station2MacAddr0>[src]

pub fn station2_mac_addr1(&mut self) -> Reg<'_, T, Station2MacAddr1>[src]

pub fn station2_mac_addr2(&mut self) -> Reg<'_, T, Station2MacAddr2>[src]

pub fn station2_mac_addr3(&mut self) -> Reg<'_, T, Station2MacAddr3>[src]

pub fn station2_mac_addr4(&mut self) -> Reg<'_, T, Station2MacAddr4>[src]

pub fn station2_mac_addr5(&mut self) -> Reg<'_, T, Station2MacAddr5>[src]

pub fn mode(&mut self) -> Reg<'_, T, Mode>[src]

pub fn high_priority_packet_buffer_q3(
    &mut self
) -> Reg<'_, T, HighPriorityPacketBufferQ3>
[src]

pub fn high_priority_packet_buffer_q2(
    &mut self
) -> Reg<'_, T, HighPriorityPacketBufferQ2>
[src]

pub fn high_priority_packet_buffer_q1(
    &mut self
) -> Reg<'_, T, HighPriorityPacketBufferQ1>
[src]

pub fn high_priority_packet_buffer_q0(
    &mut self
) -> Reg<'_, T, HighPriorityPacketBufferQ0>
[src]

pub fn pm_usage_flow_ctrl_select_mode_1(
    &mut self
) -> Reg<'_, T, PmUsageFlowCtrlSelectMode1>
[src]

pub fn pm_usage_flow_ctrl_select_mode_2(
    &mut self
) -> Reg<'_, T, PmUsageFlowCtrlSelectMode2>
[src]

pub fn pm_usage_flow_ctrl_select_mode_3(
    &mut self
) -> Reg<'_, T, PmUsageFlowCtrlSelectMode3>
[src]

pub fn pm_usage_flow_ctrl_select_mode_4(
    &mut self
) -> Reg<'_, T, PmUsageFlowCtrlSelectMode4>
[src]

pub fn port1_txq_split_for_q3(&mut self) -> Reg<'_, T, Port1TxqSplitForQ3>[src]

pub fn port1_txq_split_for_q2(&mut self) -> Reg<'_, T, Port1TxqSplitForQ2>[src]

pub fn port1_txq_split_for_q1(&mut self) -> Reg<'_, T, Port1TxqSplitForQ1>[src]

pub fn port1_txq_split_for_q0(&mut self) -> Reg<'_, T, Port1TxqSplitForQ0>[src]

pub fn port2_txq_split_for_q3(&mut self) -> Reg<'_, T, Port2TxqSplitForQ3>[src]

pub fn port2_txq_split_for_q2(&mut self) -> Reg<'_, T, Port2TxqSplitForQ2>[src]

pub fn port2_txq_split_for_q1(&mut self) -> Reg<'_, T, Port2TxqSplitForQ1>[src]

pub fn port2_txq_split_for_q0(&mut self) -> Reg<'_, T, Port2TxqSplitForQ0>[src]

pub fn port3_txq_split_for_q3(&mut self) -> Reg<'_, T, Port3TxqSplitForQ3>[src]

pub fn port3_txq_split_for_q2(&mut self) -> Reg<'_, T, Port3TxqSplitForQ2>[src]

pub fn port3_txq_split_for_q1(&mut self) -> Reg<'_, T, Port3TxqSplitForQ1>[src]

pub fn port3_txq_split_for_q0(&mut self) -> Reg<'_, T, Port3TxqSplitForQ0>[src]

pub fn interrupt_enable(&mut self) -> Reg<'_, T, InterruptEnable>[src]

pub fn force_pause_off(&mut self) -> Reg<'_, T, ForcePauseOff>[src]

pub fn fiber_signal_threshold(&mut self) -> Reg<'_, T, FiberSignalThreshold>[src]

pub fn internal_ldo_ctrl(&mut self) -> Reg<'_, T, InternalLdoCtrl>[src]

pub fn insert_src_pvid(&mut self) -> Reg<'_, T, InsertSrcPvid>[src]

pub fn pwr_mgmt_and_led_mode(&mut self) -> Reg<'_, T, PwrMgmtAndLedMode>[src]

pub fn sleep_mode(&mut self) -> Reg<'_, T, SleepMode>[src]

pub fn fwd_invalid_vid_frame_and_host_mode(
    &mut self
) -> Reg<'_, T, FwdInvalidVidFrameAndHostMode>
[src]

impl<T> Smi<T>[src]

pub fn reg<R>(&mut self) -> Reg<'_, T, R>[src]

Access a particular register associated with this PHY.

pub fn read(&mut self, addr: Address) -> Result<State, T::Error> where
    T: Read
[src]

Read the register with the given address.

pub fn write(&mut self, state: State) -> Result<(), T::Error> where
    T: Write
[src]

Write the given register state to the register with the associated address.

Auto Trait Implementations

impl<T> Send for Smi<T> where
    T: Send
[src]

impl<T> Sync for Smi<T> where
    T: Sync
[src]

impl<T> Unpin for Smi<T> where
    T: Unpin
[src]

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> Conv for T

impl<T> Conv for T

impl<T> FmtForward for T

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Pipe for T where
    T: ?Sized

impl<T> Pipe for T

impl<T> PipeAsRef for T

impl<T> PipeBorrow for T

impl<T> PipeDeref for T

impl<T> PipeRef for T

impl<T> Tap for T

impl<T> Tap for T

impl<T, U> TapAsRef<U> for T where
    U: ?Sized

impl<T, U> TapBorrow<U> for T where
    U: ?Sized

impl<T> TapDeref for T

impl<T> TryConv for T

impl<T> TryConv for T

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.