[][src]Enum ksz8863::smi::Address

#[repr(u8)]pub enum Address {
    ChipId0,
    ChipId1,
    Gc0,
    Gc1,
    Gc2,
    Gc3,
    Gc4,
    Gc5,
    Gc9,
    Gc10,
    Gc11,
    Gc12,
    Gc13,
    Port1Ctrl0,
    Port1Ctrl1,
    Port1Ctrl2,
    Port1Ctrl3,
    Port1Ctrl4,
    Port1Ctrl5,
    Port1Q0IngressRateLimit,
    Port1Q1IngressRateLimit,
    Port1Q2IngressRateLimit,
    Port1Q3IngressRateLimit,
    Port1PhySpecial,
    Port1LinkMdResult,
    Port1Ctrl12,
    Port1Ctrl13,
    Port1Status0,
    Port1Status1,
    Port2Ctrl0,
    Port2Ctrl1,
    Port2Ctrl2,
    Port2Ctrl3,
    Port2Ctrl4,
    Port2Ctrl5,
    Port2Q0IngressRateLimit,
    Port2Q1IngressRateLimit,
    Port2Q2IngressRateLimit,
    Port2Q3IngressRateLimit,
    Port2PhySpecial,
    Port2LinkMdResult,
    Port2Ctrl12,
    Port2Ctrl13,
    Port2Status0,
    Port2Status1,
    Port3Ctrl0,
    Port3Ctrl1,
    Port3Ctrl2,
    Port3Ctrl3,
    Port3Ctrl4,
    Port3Ctrl5,
    Port3Q0IngressRateLimit,
    Port3Q1IngressRateLimit,
    Port3Q2IngressRateLimit,
    Port3Q3IngressRateLimit,
    Port3Status1,
    Reset,
    TosPriorityCtrl0,
    TosPriorityCtrl1,
    TosPriorityCtrl2,
    TosPriorityCtrl3,
    TosPriorityCtrl4,
    TosPriorityCtrl5,
    TosPriorityCtrl6,
    TosPriorityCtrl7,
    TosPriorityCtrl8,
    TosPriorityCtrl9,
    TosPriorityCtrl10,
    TosPriorityCtrl11,
    TosPriorityCtrl12,
    TosPriorityCtrl13,
    TosPriorityCtrl14,
    TosPriorityCtrl15,
    MacAddr0,
    MacAddr1,
    MacAddr2,
    MacAddr3,
    MacAddr4,
    MacAddr5,
    UserDef1,
    UserDef2,
    UserDef3,
    IndirectAccessCtrl0,
    IndirectAccessCtrl1,
    IndirectData8,
    IndirectData7,
    IndirectData6,
    IndirectData5,
    IndirectData4,
    IndirectData3,
    IndirectData2,
    IndirectData1,
    IndirectData0,
    Station1MacAddr0,
    Station1MacAddr1,
    Station1MacAddr2,
    Station1MacAddr3,
    Station1MacAddr4,
    Station1MacAddr5,
    Station2MacAddr0,
    Station2MacAddr1,
    Station2MacAddr2,
    Station2MacAddr3,
    Station2MacAddr4,
    Station2MacAddr5,
    Mode,
    HighPriorityPacketBufferQ3,
    HighPriorityPacketBufferQ2,
    HighPriorityPacketBufferQ1,
    HighPriorityPacketBufferQ0,
    PmUsageFlowCtrlSelectMode1,
    PmUsageFlowCtrlSelectMode2,
    PmUsageFlowCtrlSelectMode3,
    PmUsageFlowCtrlSelectMode4,
    Port1TxqSplitForQ3,
    Port1TxqSplitForQ2,
    Port1TxqSplitForQ1,
    Port1TxqSplitForQ0,
    Port2TxqSplitForQ3,
    Port2TxqSplitForQ2,
    Port2TxqSplitForQ1,
    Port2TxqSplitForQ0,
    Port3TxqSplitForQ3,
    Port3TxqSplitForQ2,
    Port3TxqSplitForQ1,
    Port3TxqSplitForQ0,
    InterruptEnable,
    LinkChangeInterrupt,
    ForcePauseOff,
    FiberSignalThreshold,
    InternalLdoCtrl,
    InsertSrcPvid,
    PwrMgmtAndLedMode,
    SleepMode,
    FwdInvalidVidFrameAndHostMode,
}

The set of implemented MIIM register addresses on the KSZ8863.

Variants

ChipId0
ChipId1
Gc0
Gc1
Gc2
Gc3
Gc4
Gc5
Gc9
Gc10
Gc11
Gc12
Gc13
Port1Ctrl0
Port1Ctrl1
Port1Ctrl2
Port1Ctrl3
Port1Ctrl4
Port1Ctrl5
Port1Q0IngressRateLimit
Port1Q1IngressRateLimit
Port1Q2IngressRateLimit
Port1Q3IngressRateLimit
Port1PhySpecial
Port1LinkMdResult
Port1Ctrl12
Port1Ctrl13
Port1Status0
Port1Status1
Port2Ctrl0
Port2Ctrl1
Port2Ctrl2
Port2Ctrl3
Port2Ctrl4
Port2Ctrl5
Port2Q0IngressRateLimit
Port2Q1IngressRateLimit
Port2Q2IngressRateLimit
Port2Q3IngressRateLimit
Port2PhySpecial
Port2LinkMdResult
Port2Ctrl12
Port2Ctrl13
Port2Status0
Port2Status1
Port3Ctrl0
Port3Ctrl1
Port3Ctrl2
Port3Ctrl3
Port3Ctrl4
Port3Ctrl5
Port3Q0IngressRateLimit
Port3Q1IngressRateLimit
Port3Q2IngressRateLimit
Port3Q3IngressRateLimit
Port3Status1
Reset
TosPriorityCtrl0
TosPriorityCtrl1
TosPriorityCtrl2
TosPriorityCtrl3
TosPriorityCtrl4
TosPriorityCtrl5
TosPriorityCtrl6
TosPriorityCtrl7
TosPriorityCtrl8
TosPriorityCtrl9
TosPriorityCtrl10
TosPriorityCtrl11
TosPriorityCtrl12
TosPriorityCtrl13
TosPriorityCtrl14
TosPriorityCtrl15
MacAddr0
MacAddr1
MacAddr2
MacAddr3
MacAddr4
MacAddr5
UserDef1
UserDef2
UserDef3
IndirectAccessCtrl0
IndirectAccessCtrl1
IndirectData8
IndirectData7
IndirectData6
IndirectData5
IndirectData4
IndirectData3
IndirectData2
IndirectData1
IndirectData0
Station1MacAddr0
Station1MacAddr1
Station1MacAddr2
Station1MacAddr3
Station1MacAddr4
Station1MacAddr5
Station2MacAddr0
Station2MacAddr1
Station2MacAddr2
Station2MacAddr3
Station2MacAddr4
Station2MacAddr5
Mode
HighPriorityPacketBufferQ3
HighPriorityPacketBufferQ2
HighPriorityPacketBufferQ1
HighPriorityPacketBufferQ0
PmUsageFlowCtrlSelectMode1
PmUsageFlowCtrlSelectMode2
PmUsageFlowCtrlSelectMode3
PmUsageFlowCtrlSelectMode4
Port1TxqSplitForQ3
Port1TxqSplitForQ2
Port1TxqSplitForQ1
Port1TxqSplitForQ0
Port2TxqSplitForQ3
Port2TxqSplitForQ2
Port2TxqSplitForQ1
Port2TxqSplitForQ0
Port3TxqSplitForQ3
Port3TxqSplitForQ2
Port3TxqSplitForQ1
Port3TxqSplitForQ0
InterruptEnable
LinkChangeInterrupt
ForcePauseOff
FiberSignalThreshold
InternalLdoCtrl
InsertSrcPvid
PwrMgmtAndLedMode
SleepMode
FwdInvalidVidFrameAndHostMode

Implementations

impl Address[src]

pub const ALL: &'static [Self][src]

All register addresses.

Trait Implementations

impl Clone for Address[src]

impl Copy for Address[src]

impl Debug for Address[src]

impl<'de> Deserialize<'de> for Address[src]

impl Eq for Address[src]

impl From<Address> for u8[src]

impl Hash for Address[src]

impl Hash for Address[src]

impl Index<Address> for Map[src]

type Output = State

The returned type after indexing.

impl IndexMut<Address> for Map[src]

impl Ord for Address[src]

impl PartialEq<Address> for Address[src]

impl PartialOrd<Address> for Address[src]

impl Serialize for Address[src]

impl StructuralEq for Address[src]

impl StructuralPartialEq for Address[src]

impl TryFrom<u8> for Address[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl uDebug for Address[src]

Auto Trait Implementations

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> Conv for T

impl<T> Conv for T

impl<T> DeserializeOwned for T where
    T: for<'de> Deserialize<'de>, 
[src]

impl<T> FmtForward for T

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Pipe for T where
    T: ?Sized

impl<T> Pipe for T

impl<T> PipeAsRef for T

impl<T> PipeBorrow for T

impl<T> PipeDeref for T

impl<T> PipeRef for T

impl<T> Tap for T

impl<T> Tap for T

impl<T, U> TapAsRef<U> for T where
    U: ?Sized

impl<T, U> TapBorrow<U> for T where
    U: ?Sized

impl<T> TapDeref for T

impl<T> TryConv for T

impl<T> TryConv for T

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.