[][src]Enum ksz8863::smi::State

pub enum State {
    ChipId0(ChipId0),
    ChipId1(ChipId1),
    Gc0(Gc0),
    Gc1(Gc1),
    Gc2(Gc2),
    Gc3(Gc3),
    Gc4(Gc4),
    Gc5(Gc5),
    Gc9(Gc9),
    Gc10(Gc10),
    Gc11(Gc11),
    Gc12(Gc12),
    Gc13(Gc13),
    Port1Ctrl0(Port1Ctrl0),
    Port1Ctrl1(Port1Ctrl1),
    Port1Ctrl2(Port1Ctrl2),
    Port1Ctrl3(Port1Ctrl3),
    Port1Ctrl4(Port1Ctrl4),
    Port1Ctrl5(Port1Ctrl5),
    Port1Q0IngressRateLimit(Port1Q0IngressRateLimit),
    Port1Q1IngressRateLimit(Port1Q1IngressRateLimit),
    Port1Q2IngressRateLimit(Port1Q2IngressRateLimit),
    Port1Q3IngressRateLimit(Port1Q3IngressRateLimit),
    Port1PhySpecial(Port1PhySpecial),
    Port1LinkMdResult(Port1LinkMdResult),
    Port1Ctrl12(Port1Ctrl12),
    Port1Ctrl13(Port1Ctrl13),
    Port1Status0(Port1Status0),
    Port1Status1(Port1Status1),
    Port2Ctrl0(Port2Ctrl0),
    Port2Ctrl1(Port2Ctrl1),
    Port2Ctrl2(Port2Ctrl2),
    Port2Ctrl3(Port2Ctrl3),
    Port2Ctrl4(Port2Ctrl4),
    Port2Ctrl5(Port2Ctrl5),
    Port2Q0IngressRateLimit(Port2Q0IngressRateLimit),
    Port2Q1IngressRateLimit(Port2Q1IngressRateLimit),
    Port2Q2IngressRateLimit(Port2Q2IngressRateLimit),
    Port2Q3IngressRateLimit(Port2Q3IngressRateLimit),
    Port2PhySpecial(Port2PhySpecial),
    Port2LinkMdResult(Port2LinkMdResult),
    Port2Ctrl12(Port2Ctrl12),
    Port2Ctrl13(Port2Ctrl13),
    Port2Status0(Port2Status0),
    Port2Status1(Port2Status1),
    Port3Ctrl0(Port3Ctrl0),
    Port3Ctrl1(Port3Ctrl1),
    Port3Ctrl2(Port3Ctrl2),
    Port3Ctrl3(Port3Ctrl3),
    Port3Ctrl4(Port3Ctrl4),
    Port3Ctrl5(Port3Ctrl5),
    Port3Q0IngressRateLimit(Port3Q0IngressRateLimit),
    Port3Q1IngressRateLimit(Port3Q1IngressRateLimit),
    Port3Q2IngressRateLimit(Port3Q2IngressRateLimit),
    Port3Q3IngressRateLimit(Port3Q3IngressRateLimit),
    Port3Status1(Port3Status1),
    Reset(Reset),
    TosPriorityCtrl0(TosPriorityCtrl0),
    TosPriorityCtrl1(TosPriorityCtrl1),
    TosPriorityCtrl2(TosPriorityCtrl2),
    TosPriorityCtrl3(TosPriorityCtrl3),
    TosPriorityCtrl4(TosPriorityCtrl4),
    TosPriorityCtrl5(TosPriorityCtrl5),
    TosPriorityCtrl6(TosPriorityCtrl6),
    TosPriorityCtrl7(TosPriorityCtrl7),
    TosPriorityCtrl8(TosPriorityCtrl8),
    TosPriorityCtrl9(TosPriorityCtrl9),
    TosPriorityCtrl10(TosPriorityCtrl10),
    TosPriorityCtrl11(TosPriorityCtrl11),
    TosPriorityCtrl12(TosPriorityCtrl12),
    TosPriorityCtrl13(TosPriorityCtrl13),
    TosPriorityCtrl14(TosPriorityCtrl14),
    TosPriorityCtrl15(TosPriorityCtrl15),
    MacAddr0(MacAddr0),
    MacAddr1(MacAddr1),
    MacAddr2(MacAddr2),
    MacAddr3(MacAddr3),
    MacAddr4(MacAddr4),
    MacAddr5(MacAddr5),
    UserDef1(UserDef1),
    UserDef2(UserDef2),
    UserDef3(UserDef3),
    IndirectAccessCtrl0(IndirectAccessCtrl0),
    IndirectAccessCtrl1(IndirectAccessCtrl1),
    IndirectData8(IndirectData8),
    IndirectData7(IndirectData7),
    IndirectData6(IndirectData6),
    IndirectData5(IndirectData5),
    IndirectData4(IndirectData4),
    IndirectData3(IndirectData3),
    IndirectData2(IndirectData2),
    IndirectData1(IndirectData1),
    IndirectData0(IndirectData0),
    Station1MacAddr0(Station1MacAddr0),
    Station1MacAddr1(Station1MacAddr1),
    Station1MacAddr2(Station1MacAddr2),
    Station1MacAddr3(Station1MacAddr3),
    Station1MacAddr4(Station1MacAddr4),
    Station1MacAddr5(Station1MacAddr5),
    Station2MacAddr0(Station2MacAddr0),
    Station2MacAddr1(Station2MacAddr1),
    Station2MacAddr2(Station2MacAddr2),
    Station2MacAddr3(Station2MacAddr3),
    Station2MacAddr4(Station2MacAddr4),
    Station2MacAddr5(Station2MacAddr5),
    Mode(Mode),
    HighPriorityPacketBufferQ3(HighPriorityPacketBufferQ3),
    HighPriorityPacketBufferQ2(HighPriorityPacketBufferQ2),
    HighPriorityPacketBufferQ1(HighPriorityPacketBufferQ1),
    HighPriorityPacketBufferQ0(HighPriorityPacketBufferQ0),
    PmUsageFlowCtrlSelectMode1(PmUsageFlowCtrlSelectMode1),
    PmUsageFlowCtrlSelectMode2(PmUsageFlowCtrlSelectMode2),
    PmUsageFlowCtrlSelectMode3(PmUsageFlowCtrlSelectMode3),
    PmUsageFlowCtrlSelectMode4(PmUsageFlowCtrlSelectMode4),
    Port1TxqSplitForQ3(Port1TxqSplitForQ3),
    Port1TxqSplitForQ2(Port1TxqSplitForQ2),
    Port1TxqSplitForQ1(Port1TxqSplitForQ1),
    Port1TxqSplitForQ0(Port1TxqSplitForQ0),
    Port2TxqSplitForQ3(Port2TxqSplitForQ3),
    Port2TxqSplitForQ2(Port2TxqSplitForQ2),
    Port2TxqSplitForQ1(Port2TxqSplitForQ1),
    Port2TxqSplitForQ0(Port2TxqSplitForQ0),
    Port3TxqSplitForQ3(Port3TxqSplitForQ3),
    Port3TxqSplitForQ2(Port3TxqSplitForQ2),
    Port3TxqSplitForQ1(Port3TxqSplitForQ1),
    Port3TxqSplitForQ0(Port3TxqSplitForQ0),
    InterruptEnable(InterruptEnable),
    LinkChangeInterrupt(LinkChangeInterrupt),
    ForcePauseOff(ForcePauseOff),
    FiberSignalThreshold(FiberSignalThreshold),
    InternalLdoCtrl(InternalLdoCtrl),
    InsertSrcPvid(InsertSrcPvid),
    PwrMgmtAndLedMode(PwrMgmtAndLedMode),
    SleepMode(SleepMode),
    FwdInvalidVidFrameAndHostMode(FwdInvalidVidFrameAndHostMode),
}

A dynamic representation of a register's state.

Variants

ChipId0(ChipId0)
ChipId1(ChipId1)
Gc0(Gc0)
Gc1(Gc1)
Gc2(Gc2)
Gc3(Gc3)
Gc4(Gc4)
Gc5(Gc5)
Gc9(Gc9)
Gc10(Gc10)
Gc11(Gc11)
Gc12(Gc12)
Gc13(Gc13)
Port1Ctrl0(Port1Ctrl0)
Port1Ctrl1(Port1Ctrl1)
Port1Ctrl2(Port1Ctrl2)
Port1Ctrl3(Port1Ctrl3)
Port1Ctrl4(Port1Ctrl4)
Port1Ctrl5(Port1Ctrl5)
Port1Q0IngressRateLimit(Port1Q0IngressRateLimit)
Port1Q1IngressRateLimit(Port1Q1IngressRateLimit)
Port1Q2IngressRateLimit(Port1Q2IngressRateLimit)
Port1Q3IngressRateLimit(Port1Q3IngressRateLimit)
Port1PhySpecial(Port1PhySpecial)
Port1LinkMdResult(Port1LinkMdResult)
Port1Ctrl12(Port1Ctrl12)
Port1Ctrl13(Port1Ctrl13)
Port1Status0(Port1Status0)
Port1Status1(Port1Status1)
Port2Ctrl0(Port2Ctrl0)
Port2Ctrl1(Port2Ctrl1)
Port2Ctrl2(Port2Ctrl2)
Port2Ctrl3(Port2Ctrl3)
Port2Ctrl4(Port2Ctrl4)
Port2Ctrl5(Port2Ctrl5)
Port2Q0IngressRateLimit(Port2Q0IngressRateLimit)
Port2Q1IngressRateLimit(Port2Q1IngressRateLimit)
Port2Q2IngressRateLimit(Port2Q2IngressRateLimit)
Port2Q3IngressRateLimit(Port2Q3IngressRateLimit)
Port2PhySpecial(Port2PhySpecial)
Port2LinkMdResult(Port2LinkMdResult)
Port2Ctrl12(Port2Ctrl12)
Port2Ctrl13(Port2Ctrl13)
Port2Status0(Port2Status0)
Port2Status1(Port2Status1)
Port3Ctrl0(Port3Ctrl0)
Port3Ctrl1(Port3Ctrl1)
Port3Ctrl2(Port3Ctrl2)
Port3Ctrl3(Port3Ctrl3)
Port3Ctrl4(Port3Ctrl4)
Port3Ctrl5(Port3Ctrl5)
Port3Q0IngressRateLimit(Port3Q0IngressRateLimit)
Port3Q1IngressRateLimit(Port3Q1IngressRateLimit)
Port3Q2IngressRateLimit(Port3Q2IngressRateLimit)
Port3Q3IngressRateLimit(Port3Q3IngressRateLimit)
Port3Status1(Port3Status1)
Reset(Reset)
TosPriorityCtrl0(TosPriorityCtrl0)
TosPriorityCtrl1(TosPriorityCtrl1)
TosPriorityCtrl2(TosPriorityCtrl2)
TosPriorityCtrl3(TosPriorityCtrl3)
TosPriorityCtrl4(TosPriorityCtrl4)
TosPriorityCtrl5(TosPriorityCtrl5)
TosPriorityCtrl6(TosPriorityCtrl6)
TosPriorityCtrl7(TosPriorityCtrl7)
TosPriorityCtrl8(TosPriorityCtrl8)
TosPriorityCtrl9(TosPriorityCtrl9)
TosPriorityCtrl10(TosPriorityCtrl10)
TosPriorityCtrl11(TosPriorityCtrl11)
TosPriorityCtrl12(TosPriorityCtrl12)
TosPriorityCtrl13(TosPriorityCtrl13)
TosPriorityCtrl14(TosPriorityCtrl14)
TosPriorityCtrl15(TosPriorityCtrl15)
MacAddr0(MacAddr0)
MacAddr1(MacAddr1)
MacAddr2(MacAddr2)
MacAddr3(MacAddr3)
MacAddr4(MacAddr4)
MacAddr5(MacAddr5)
UserDef1(UserDef1)
UserDef2(UserDef2)
UserDef3(UserDef3)
IndirectAccessCtrl0(IndirectAccessCtrl0)
IndirectAccessCtrl1(IndirectAccessCtrl1)
IndirectData8(IndirectData8)
IndirectData7(IndirectData7)
IndirectData6(IndirectData6)
IndirectData5(IndirectData5)
IndirectData4(IndirectData4)
IndirectData3(IndirectData3)
IndirectData2(IndirectData2)
IndirectData1(IndirectData1)
IndirectData0(IndirectData0)
Station1MacAddr0(Station1MacAddr0)
Station1MacAddr1(Station1MacAddr1)
Station1MacAddr2(Station1MacAddr2)
Station1MacAddr3(Station1MacAddr3)
Station1MacAddr4(Station1MacAddr4)
Station1MacAddr5(Station1MacAddr5)
Station2MacAddr0(Station2MacAddr0)
Station2MacAddr1(Station2MacAddr1)
Station2MacAddr2(Station2MacAddr2)
Station2MacAddr3(Station2MacAddr3)
Station2MacAddr4(Station2MacAddr4)
Station2MacAddr5(Station2MacAddr5)
Mode(Mode)
HighPriorityPacketBufferQ3(HighPriorityPacketBufferQ3)
HighPriorityPacketBufferQ2(HighPriorityPacketBufferQ2)
HighPriorityPacketBufferQ1(HighPriorityPacketBufferQ1)
HighPriorityPacketBufferQ0(HighPriorityPacketBufferQ0)
PmUsageFlowCtrlSelectMode1(PmUsageFlowCtrlSelectMode1)
PmUsageFlowCtrlSelectMode2(PmUsageFlowCtrlSelectMode2)
PmUsageFlowCtrlSelectMode3(PmUsageFlowCtrlSelectMode3)
PmUsageFlowCtrlSelectMode4(PmUsageFlowCtrlSelectMode4)
Port1TxqSplitForQ3(Port1TxqSplitForQ3)
Port1TxqSplitForQ2(Port1TxqSplitForQ2)
Port1TxqSplitForQ1(Port1TxqSplitForQ1)
Port1TxqSplitForQ0(Port1TxqSplitForQ0)
Port2TxqSplitForQ3(Port2TxqSplitForQ3)
Port2TxqSplitForQ2(Port2TxqSplitForQ2)
Port2TxqSplitForQ1(Port2TxqSplitForQ1)
Port2TxqSplitForQ0(Port2TxqSplitForQ0)
Port3TxqSplitForQ3(Port3TxqSplitForQ3)
Port3TxqSplitForQ2(Port3TxqSplitForQ2)
Port3TxqSplitForQ1(Port3TxqSplitForQ1)
Port3TxqSplitForQ0(Port3TxqSplitForQ0)
InterruptEnable(InterruptEnable)
LinkChangeInterrupt(LinkChangeInterrupt)
ForcePauseOff(ForcePauseOff)
FiberSignalThreshold(FiberSignalThreshold)
InternalLdoCtrl(InternalLdoCtrl)
InsertSrcPvid(InsertSrcPvid)
PwrMgmtAndLedMode(PwrMgmtAndLedMode)
SleepMode(SleepMode)
FwdInvalidVidFrameAndHostMode(FwdInvalidVidFrameAndHostMode)

Implementations

impl State[src]

pub fn from_addr_and_data(addr: Address, data: u8) -> Self[src]

Construct a register state from its address and data represented as a u32.

pub fn from_addr_default(addr: Address) -> Self[src]

Construct the default register state associated with the given address.

pub fn addr(&self) -> Address[src]

The address of the register with which this state is associated.

pub fn reg<R>(&self) -> Result<&R, InvalidAddress> where
    R: 'static + Register
[src]

Attempt to retrieve a reference to a register of type R from the dynamic register State representation.

Returns an Err if the register type does not match.

pub fn reg_mut<R>(&mut self) -> Result<&mut R, InvalidAddress> where
    R: 'static + Register
[src]

Attempt to retrieve a mutable reference to a register of type R from the dynamic register State representation.

Returns an Err if the register type does not match.

Trait Implementations

impl Clone for State[src]

impl Copy for State[src]

impl Debug for State[src]

impl<'de> Deserialize<'de> for State[src]

impl Eq for State[src]

impl From<ChipId0> for State[src]

impl From<ChipId1> for State[src]

impl From<FiberSignalThreshold> for State[src]

impl From<ForcePauseOff> for State[src]

impl From<FwdInvalidVidFrameAndHostMode> for State[src]

impl From<Gc0> for State[src]

impl From<Gc1> for State[src]

impl From<Gc10> for State[src]

impl From<Gc11> for State[src]

impl From<Gc12> for State[src]

impl From<Gc13> for State[src]

impl From<Gc2> for State[src]

impl From<Gc3> for State[src]

impl From<Gc4> for State[src]

impl From<Gc5> for State[src]

impl From<Gc9> for State[src]

impl From<HighPriorityPacketBufferQ0> for State[src]

impl From<HighPriorityPacketBufferQ1> for State[src]

impl From<HighPriorityPacketBufferQ2> for State[src]

impl From<HighPriorityPacketBufferQ3> for State[src]

impl From<IndirectAccessCtrl0> for State[src]

impl From<IndirectAccessCtrl1> for State[src]

impl From<IndirectData0> for State[src]

impl From<IndirectData1> for State[src]

impl From<IndirectData2> for State[src]

impl From<IndirectData3> for State[src]

impl From<IndirectData4> for State[src]

impl From<IndirectData5> for State[src]

impl From<IndirectData6> for State[src]

impl From<IndirectData7> for State[src]

impl From<IndirectData8> for State[src]

impl From<InsertSrcPvid> for State[src]

impl From<InternalLdoCtrl> for State[src]

impl From<InterruptEnable> for State[src]

impl From<LinkChangeInterrupt> for State[src]

impl From<MacAddr0> for State[src]

impl From<MacAddr1> for State[src]

impl From<MacAddr2> for State[src]

impl From<MacAddr3> for State[src]

impl From<MacAddr4> for State[src]

impl From<MacAddr5> for State[src]

impl From<Mode> for State[src]

impl From<PmUsageFlowCtrlSelectMode1> for State[src]

impl From<PmUsageFlowCtrlSelectMode2> for State[src]

impl From<PmUsageFlowCtrlSelectMode3> for State[src]

impl From<PmUsageFlowCtrlSelectMode4> for State[src]

impl From<Port1Ctrl0> for State[src]

impl From<Port1Ctrl1> for State[src]

impl From<Port1Ctrl12> for State[src]

impl From<Port1Ctrl13> for State[src]

impl From<Port1Ctrl2> for State[src]

impl From<Port1Ctrl3> for State[src]

impl From<Port1Ctrl4> for State[src]

impl From<Port1Ctrl5> for State[src]

impl From<Port1LinkMdResult> for State[src]

impl From<Port1PhySpecial> for State[src]

impl From<Port1Q0IngressRateLimit> for State[src]

impl From<Port1Q1IngressRateLimit> for State[src]

impl From<Port1Q2IngressRateLimit> for State[src]

impl From<Port1Q3IngressRateLimit> for State[src]

impl From<Port1Status0> for State[src]

impl From<Port1Status1> for State[src]

impl From<Port1TxqSplitForQ0> for State[src]

impl From<Port1TxqSplitForQ1> for State[src]

impl From<Port1TxqSplitForQ2> for State[src]

impl From<Port1TxqSplitForQ3> for State[src]

impl From<Port2Ctrl0> for State[src]

impl From<Port2Ctrl1> for State[src]

impl From<Port2Ctrl12> for State[src]

impl From<Port2Ctrl13> for State[src]

impl From<Port2Ctrl2> for State[src]

impl From<Port2Ctrl3> for State[src]

impl From<Port2Ctrl4> for State[src]

impl From<Port2Ctrl5> for State[src]

impl From<Port2LinkMdResult> for State[src]

impl From<Port2PhySpecial> for State[src]

impl From<Port2Q0IngressRateLimit> for State[src]

impl From<Port2Q1IngressRateLimit> for State[src]

impl From<Port2Q2IngressRateLimit> for State[src]

impl From<Port2Q3IngressRateLimit> for State[src]

impl From<Port2Status0> for State[src]

impl From<Port2Status1> for State[src]

impl From<Port2TxqSplitForQ0> for State[src]

impl From<Port2TxqSplitForQ1> for State[src]

impl From<Port2TxqSplitForQ2> for State[src]

impl From<Port2TxqSplitForQ3> for State[src]

impl From<Port3Ctrl0> for State[src]

impl From<Port3Ctrl1> for State[src]

impl From<Port3Ctrl2> for State[src]

impl From<Port3Ctrl3> for State[src]

impl From<Port3Ctrl4> for State[src]

impl From<Port3Ctrl5> for State[src]

impl From<Port3Q0IngressRateLimit> for State[src]

impl From<Port3Q1IngressRateLimit> for State[src]

impl From<Port3Q2IngressRateLimit> for State[src]

impl From<Port3Q3IngressRateLimit> for State[src]

impl From<Port3Status1> for State[src]

impl From<Port3TxqSplitForQ0> for State[src]

impl From<Port3TxqSplitForQ1> for State[src]

impl From<Port3TxqSplitForQ2> for State[src]

impl From<Port3TxqSplitForQ3> for State[src]

impl From<PwrMgmtAndLedMode> for State[src]

impl From<Reset> for State[src]

impl From<SleepMode> for State[src]

impl From<State> for u8[src]

impl From<Station1MacAddr0> for State[src]

impl From<Station1MacAddr1> for State[src]

impl From<Station1MacAddr2> for State[src]

impl From<Station1MacAddr3> for State[src]

impl From<Station1MacAddr4> for State[src]

impl From<Station1MacAddr5> for State[src]

impl From<Station2MacAddr0> for State[src]

impl From<Station2MacAddr1> for State[src]

impl From<Station2MacAddr2> for State[src]

impl From<Station2MacAddr3> for State[src]

impl From<Station2MacAddr4> for State[src]

impl From<Station2MacAddr5> for State[src]

impl From<TosPriorityCtrl0> for State[src]

impl From<TosPriorityCtrl1> for State[src]

impl From<TosPriorityCtrl10> for State[src]

impl From<TosPriorityCtrl11> for State[src]

impl From<TosPriorityCtrl12> for State[src]

impl From<TosPriorityCtrl13> for State[src]

impl From<TosPriorityCtrl14> for State[src]

impl From<TosPriorityCtrl15> for State[src]

impl From<TosPriorityCtrl2> for State[src]

impl From<TosPriorityCtrl3> for State[src]

impl From<TosPriorityCtrl4> for State[src]

impl From<TosPriorityCtrl5> for State[src]

impl From<TosPriorityCtrl6> for State[src]

impl From<TosPriorityCtrl7> for State[src]

impl From<TosPriorityCtrl8> for State[src]

impl From<TosPriorityCtrl9> for State[src]

impl From<UserDef1> for State[src]

impl From<UserDef2> for State[src]

impl From<UserDef3> for State[src]

impl Hash for State[src]

impl Hash for State[src]

impl PartialEq<State> for State[src]

impl Serialize for State[src]

impl StructuralEq for State[src]

impl StructuralPartialEq for State[src]

impl TryFrom<State> for ChipId0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for ChipId1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc11[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station2MacAddr1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station2MacAddr2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station2MacAddr3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station2MacAddr4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station2MacAddr5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Mode[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for HighPriorityPacketBufferQ3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for HighPriorityPacketBufferQ2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for HighPriorityPacketBufferQ1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for HighPriorityPacketBufferQ0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc12[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for PmUsageFlowCtrlSelectMode1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for PmUsageFlowCtrlSelectMode2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for PmUsageFlowCtrlSelectMode3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for PmUsageFlowCtrlSelectMode4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1TxqSplitForQ3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1TxqSplitForQ2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1TxqSplitForQ1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1TxqSplitForQ0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2TxqSplitForQ3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2TxqSplitForQ2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc13[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2TxqSplitForQ1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2TxqSplitForQ0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3TxqSplitForQ3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3TxqSplitForQ2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3TxqSplitForQ1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3TxqSplitForQ0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for InterruptEnable[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for LinkChangeInterrupt[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for ForcePauseOff[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for FiberSignalThreshold[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for InternalLdoCtrl[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for InsertSrcPvid[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for PwrMgmtAndLedMode[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for SleepMode[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for FwdInvalidVidFrameAndHostMode[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Q0IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Q1IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Q2IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Q3IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1PhySpecial[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1LinkMdResult[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl12[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Ctrl13[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Status0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port1Status1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Q0IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Q1IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Q2IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Q3IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2PhySpecial[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2LinkMdResult[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl12[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Ctrl13[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Status0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port2Status1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Ctrl0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Ctrl1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Ctrl2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Ctrl3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Ctrl4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Ctrl5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Q0IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Q1IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Q2IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Q3IngressRateLimit[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Port3Status1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Reset[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl6[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl7[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl8[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl9[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl10[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl11[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl12[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl13[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl14[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for TosPriorityCtrl15[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for MacAddr0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for MacAddr1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for MacAddr2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for MacAddr3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for MacAddr4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for MacAddr5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for UserDef1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc9[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for UserDef2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for UserDef3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectAccessCtrl0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectAccessCtrl1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData8[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData7[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData6[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Gc10[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for IndirectData0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station1MacAddr0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station1MacAddr1[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station1MacAddr2[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station1MacAddr3[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station1MacAddr4[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station1MacAddr5[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl TryFrom<State> for Station2MacAddr0[src]

type Error = InvalidAddress

The type returned in the event of a conversion error.

impl uDebug for State[src]

Auto Trait Implementations

impl Send for State[src]

impl Sync for State[src]

impl Unpin for State[src]

Blanket Implementations

impl<T> Any for T where
    T: 'static + ?Sized
[src]

impl<T> Borrow<T> for T where
    T: ?Sized
[src]

impl<T> BorrowMut<T> for T where
    T: ?Sized
[src]

impl<T> Conv for T

impl<T> Conv for T

impl<T> DeserializeOwned for T where
    T: for<'de> Deserialize<'de>, 
[src]

impl<T> FmtForward for T

impl<T> From<T> for T[src]

impl<T, U> Into<U> for T where
    U: From<T>, 
[src]

impl<T> Pipe for T where
    T: ?Sized

impl<T> Pipe for T

impl<T> PipeAsRef for T

impl<T> PipeBorrow for T

impl<T> PipeDeref for T

impl<T> PipeRef for T

impl<T> Tap for T

impl<T> Tap for T

impl<T, U> TapAsRef<U> for T where
    U: ?Sized

impl<T, U> TapBorrow<U> for T where
    U: ?Sized

impl<T> TapDeref for T

impl<T> TryConv for T

impl<T> TryConv for T

impl<T, U> TryFrom<U> for T where
    U: Into<T>, 
[src]

type Error = Infallible

The type returned in the event of a conversion error.

impl<T, U> TryInto<U> for T where
    U: TryFrom<T>, 
[src]

type Error = <U as TryFrom<T>>::Error

The type returned in the event of a conversion error.