#[repr(usize)]pub enum AuxvType {
Show 43 variants
NULL = 0,
IGNORE = 1,
EXECFD = 2,
PHDR = 3,
PHENT = 4,
PHNUM = 5,
PAGESZ = 6,
BASE = 7,
FLAGS = 8,
ENTRY = 9,
NOTELF = 10,
UID = 11,
EUID = 12,
GID = 13,
EGID = 14,
PLATFORM = 15,
HWCAP = 16,
CLKTCK = 17,
FPUCW = 18,
DCACHEBSIZE = 19,
ICACHEBSIZE = 20,
UCACHEBSIZE = 21,
IGNOREPPC = 22,
SECURE = 23,
BASE_PLATFORM = 24,
RANDOM = 25,
HWCAP2 = 26,
EXECFN = 31,
SYSINFO = 32,
SYSINFO_EHDR = 33,
L1I_CACHESHAPE = 34,
L1D_CACHESHAPE = 35,
L2_CACHESHAPE = 36,
L3_CACHESHAPE = 37,
L1I_CACHESIZE = 40,
L1I_CACHEGEOMETRY = 41,
L1D_CACHESIZE = 42,
L1D_CACHEGEOMETRY = 43,
L2_CACHESIZE = 44,
L2_CACHEGEOMETRY = 45,
L3_CACHESIZE = 46,
L3_CACHEGEOMETRY = 47,
MINSIGSTKSZ = 51,
}
Expand description
Represents the type of an auxiliary vector entry.
Variants§
NULL = 0
End of vector
IGNORE = 1
Entry should be ignored
EXECFD = 2
File descriptor of program
PHDR = 3
Program headers for program
PHENT = 4
Size of program header entry
PHNUM = 5
Number of program headers
PAGESZ = 6
System page size
BASE = 7
Base address of interpreter
FLAGS = 8
Flags
ENTRY = 9
Entry point of program
NOTELF = 10
Program is not ELF
UID = 11
Real UID
EUID = 12
Effective UID
GID = 13
Real GID
EGID = 14
Effective GID
PLATFORM = 15
String identifying CPU for optimizations
HWCAP = 16
Arch dependent hints at CPU capabilities
CLKTCK = 17
Frequency at which times() increments
FPUCW = 18
Floating point unit control word
DCACHEBSIZE = 19
Data cache block size
ICACHEBSIZE = 20
Instruction cache block size
UCACHEBSIZE = 21
Unified cache block size
IGNOREPPC = 22
Entry should be ignored on PowerPC
SECURE = 23
Secure mode boolean
BASE_PLATFORM = 24
String identifying real platform, may differ from AT_PLATFORM
RANDOM = 25
Address of 16 random bytes
HWCAP2 = 26
Extension of AT_HWCAP
EXECFN = 31
Filename of program
SYSINFO = 32
Address of the VDSO
SYSINFO_EHDR = 33
Address of the ELF header of the VDSO
L1I_CACHESHAPE = 34
Shape of level 1 instruction cache
L1D_CACHESHAPE = 35
Shape of level 1 data cache
L2_CACHESHAPE = 36
Shape of level 2 cache
L3_CACHESHAPE = 37
Shape of level 3 cache
L1I_CACHESIZE = 40
Size of level 1 instruction cache
L1I_CACHEGEOMETRY = 41
Geometry of level 1 instruction cache
L1D_CACHESIZE = 42
Size of level 1 data cache
L1D_CACHEGEOMETRY = 43
Geometry of level 1 data cache
L2_CACHESIZE = 44
Size of level 2 cache
L2_CACHEGEOMETRY = 45
Geometry of level 2 cache
L3_CACHESIZE = 46
Size of level 3 cache
L3_CACHEGEOMETRY = 47
Geometry of level 3 cache
MINSIGSTKSZ = 51
Minimal stack size for signal delivery