kernel_elf_parser/
auxv.rs

1/// Represents the type of an auxiliary vector entry.
2#[derive(Clone, Copy, PartialEq, Eq)]
3#[allow(non_camel_case_types, unused)]
4#[repr(usize)]
5pub enum AuxvType {
6    /// End of vector
7    NULL = 0,
8    /// Entry should be ignored
9    IGNORE = 1,
10    /// File descriptor of program
11    EXECFD = 2,
12    /// Program headers for program
13    PHDR = 3,
14    /// Size of program header entry
15    PHENT = 4,
16    /// Number of program headers
17    PHNUM = 5,
18    /// System page size
19    PAGESZ = 6,
20    /// Base address of interpreter
21    BASE = 7,
22    /// Flags
23    FLAGS = 8,
24    /// Entry point of program
25    ENTRY = 9,
26    /// Program is not ELF
27    NOTELF = 10,
28    /// Real UID
29    UID = 11,
30    /// Effective UID
31    EUID = 12,
32    /// Real GID
33    GID = 13,
34    /// Effective GID
35    EGID = 14,
36    /// String identifying CPU for optimizations
37    PLATFORM = 15,
38    /// Arch dependent hints at CPU capabilities
39    HWCAP = 16,
40    /// Frequency at which times() increments
41    CLKTCK = 17,
42    /// Floating point unit control word
43    FPUCW = 18,
44    /// Data cache block size
45    DCACHEBSIZE = 19,
46    /// Instruction cache block size
47    ICACHEBSIZE = 20,
48    /// Unified cache block size
49    UCACHEBSIZE = 21,
50    /// Entry should be ignored on PowerPC
51    IGNOREPPC = 22,
52    /// Secure mode boolean
53    SECURE = 23,
54    /// String identifying real platform, may differ from AT_PLATFORM
55    BASE_PLATFORM = 24,
56    /// Address of 16 random bytes
57    RANDOM = 25,
58    /// Extension of AT_HWCAP
59    HWCAP2 = 26,
60    /// Filename of program
61    EXECFN = 31,
62    /// Address of the VDSO
63    SYSINFO = 32,
64    /// Address of the ELF header of the VDSO
65    SYSINFO_EHDR = 33,
66    /// Shape of level 1 instruction cache
67    L1I_CACHESHAPE = 34,
68    /// Shape of level 1 data cache
69    L1D_CACHESHAPE = 35,
70    /// Shape of level 2 cache
71    L2_CACHESHAPE = 36,
72    /// Shape of level 3 cache
73    L3_CACHESHAPE = 37,
74    /// Size of level 1 instruction cache
75    L1I_CACHESIZE = 40,
76    /// Geometry of level 1 instruction cache
77    L1I_CACHEGEOMETRY = 41,
78    /// Size of level 1 data cache
79    L1D_CACHESIZE = 42,
80    /// Geometry of level 1 data cache
81    L1D_CACHEGEOMETRY = 43,
82    /// Size of level 2 cache
83    L2_CACHESIZE = 44,
84    /// Geometry of level 2 cache
85    L2_CACHEGEOMETRY = 45,
86    /// Size of level 3 cache
87    L3_CACHESIZE = 46,
88    /// Geometry of level 3 cache
89    L3_CACHEGEOMETRY = 47,
90    /// Minimal stack size for signal delivery
91    MINSIGSTKSZ = 51,
92}
93
94/// Represents an entry in the auxiliary vector.
95#[derive(Clone, Copy)]
96#[repr(C)]
97pub struct AuxvEntry {
98    /// The type of the auxiliary vector entry.
99    auxv_type: AuxvType,
100    /// The value associated with the auxiliary vector entry.
101    auxv_val: usize,
102}
103
104impl AuxvEntry {
105    /// Create a new auxv entry
106    pub fn new(auxv_type: AuxvType, auxv_val: usize) -> Self {
107        Self {
108            auxv_type,
109            auxv_val,
110        }
111    }
112
113    /// Get [self::AuxvType] of the auxv entry
114    pub fn get_type(&self) -> AuxvType {
115        self.auxv_type
116    }
117
118    /// Get the value of the auxv entry
119    pub fn value(&self) -> usize {
120        self.auxv_val
121    }
122
123    /// Get a mutable reference to the value of the auxv entry
124    pub fn value_mut_ref(&mut self) -> &mut usize {
125        &mut self.auxv_val
126    }
127}
kernel_elf_parser/auxv.rs

kernel_elf_parser/
auxv.rs
