[][src]Type Definition imxrt1062_snvs::hpsicr::R

type R = R<u32, HPSICR>;

Reader of register HPSICR

Methods

impl R[src]

pub fn sv0_en(&self) -> SV0_EN_R[src]

Bit 0 - Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation

pub fn sv1_en(&self) -> SV1_EN_R[src]

Bit 1 - Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation

pub fn sv2_en(&self) -> SV2_EN_R[src]

Bit 2 - Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation

pub fn sv3_en(&self) -> SV3_EN_R[src]

Bit 3 - Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation

pub fn sv4_en(&self) -> SV4_EN_R[src]

Bit 4 - Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation

pub fn sv5_en(&self) -> SV5_EN_R[src]

Bit 5 - Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation

pub fn lpsvi_en(&self) -> LPSVI_EN_R[src]

Bit 31 - LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section