[−][src]Module imxrt1062_snvs::hpsicr
SNVS_HP Security Interrupt Control Register
Structs
LPSVI_EN_W | Write proxy for field |
SV0_EN_W | Write proxy for field |
SV1_EN_W | Write proxy for field |
SV2_EN_W | Write proxy for field |
SV3_EN_W | Write proxy for field |
SV4_EN_W | Write proxy for field |
SV5_EN_W | Write proxy for field |
Enums
LPSVI_EN_A | LP Security Violation Interrupt Enable This bit enables generating of the security interrupt to the host processor upon security violation signal from the LP section |
SV0_EN_A | Security Violation 0 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 0 security violation |
SV1_EN_A | Security Violation 1 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 1 security violation |
SV2_EN_A | Security Violation 2 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 2 security violation |
SV3_EN_A | Security Violation 3 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 3 security violation |
SV4_EN_A | Security Violation 4 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 4 security violation |
SV5_EN_A | Security Violation 5 Interrupt Enable Setting this bit to 1 enables generation of the security interrupt to the host processor upon detection of the Security Violation 5 security violation |
Type Definitions
LPSVI_EN_R | Reader of field |
R | Reader of register HPSICR |
SV0_EN_R | Reader of field |
SV1_EN_R | Reader of field |
SV2_EN_R | Reader of field |
SV3_EN_R | Reader of field |
SV4_EN_R | Reader of field |
SV5_EN_R | Reader of field |
W | Writer for register HPSICR |