[][src]Type Definition imxrt1062_ccm_analog::pll_usb1_tog::W

type W = W<u32, PLL_USB1_TOG>;

Writer for register PLL_USB1_TOG

Methods

impl W[src]

pub fn div_select(&mut self) -> DIV_SELECT_W[src]

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W[src]

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&mut self) -> POWER_W[src]

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W[src]

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W[src]

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W[src]

Bit 16 - Bypass the PLL.