Struct imxrt1062_ccm_analog::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _PLL_ARM>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn pll_sel(&mut self) -> PLL_SEL_W

Bit 19 - Reserved

impl W<u32, Reg<u32, _PLL_ARM_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn pll_sel(&mut self) -> PLL_SEL_W

Bit 19 - Reserved

impl W<u32, Reg<u32, _PLL_ARM_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn pll_sel(&mut self) -> PLL_SEL_W

Bit 19 - Reserved

impl W<u32, Reg<u32, _PLL_ARM_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn pll_sel(&mut self) -> PLL_SEL_W

Bit 19 - Reserved

impl W<u32, Reg<u32, _PLL_USB1>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB1_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB1_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB1_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - Powers the 9-phase PLL outputs for USBPHYn

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY0 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB2>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB2_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB2_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_USB2_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 1 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn en_usb_clks(&mut self) -> EN_USB_CLKS_W

Bit 6 - 0: 8-phase PLL outputs for USBPHY1 are powered down

pub fn power(&mut self) -> POWER_W

Bit 12 - Powers up the PLL. This bit will be set automatically when USBPHY1 remote wakeup event happens.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL clock output.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_SYS>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_SYS_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_SYS_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_SYS_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bit 0 - This field controls the PLL loop divider. 0 - Fout=Fref20; 1 - Fout=Fref22.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

impl W<u32, Reg<u32, _PLL_SYS_SS>>

pub fn step(&mut self) -> STEP_W

Bits 0:14 - Frequency change step = step/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.

pub fn enable(&mut self) -> ENABLE_W

Bit 15 - Enable bit

pub fn stop(&mut self) -> STOP_W

Bits 16:31 - Frequency change = stop/CCM_ANALOG_PLL_SYS_DENOM[B]*24MHz.

impl W<u32, Reg<u32, _PLL_SYS_NUM>>

pub fn a(&mut self) -> A_W

Bits 0:29 - 30 bit numerator (A) of fractional loop divider (signed integer).

impl W<u32, Reg<u32, _PLL_SYS_DENOM>>

pub fn b(&mut self) -> B_W

Bits 0:29 - 30 bit Denominator (B) of fractional loop divider (unsigned integer).

impl W<u32, Reg<u32, _PLL_AUDIO>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_AUDIO_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_AUDIO_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_AUDIO_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_AUDIO_NUM>>

pub fn a(&mut self) -> A_W

Bits 0:29 - 30 bit numerator of fractional loop divider.

impl W<u32, Reg<u32, _PLL_AUDIO_DENOM>>

pub fn b(&mut self) -> B_W

Bits 0:29 - 30 bit Denominator of fractional loop divider.

impl W<u32, Reg<u32, _PLL_VIDEO>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_VIDEO_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_VIDEO_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_VIDEO_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enalbe PLL output

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W

Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux.

impl W<u32, Reg<u32, _PLL_VIDEO_NUM>>

pub fn a(&mut self) -> A_W

Bits 0:29 - 30 bit numerator of fractional loop divider(Signed number), absolute value should be less than denominator

impl W<u32, Reg<u32, _PLL_VIDEO_DENOM>>

pub fn b(&mut self) -> B_W

Bits 0:29 - 30 bit Denominator of fractional loop divider.

impl W<u32, Reg<u32, _PLL_ENET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&mut self) -> ENET2_DIV_SELECT_W

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&mut self) -> ENET2_REF_EN_W

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&mut self) -> ENET_25M_REF_EN_W

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

impl W<u32, Reg<u32, _PLL_ENET_SET>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&mut self) -> ENET2_DIV_SELECT_W

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&mut self) -> ENET2_REF_EN_W

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&mut self) -> ENET_25M_REF_EN_W

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

impl W<u32, Reg<u32, _PLL_ENET_CLR>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&mut self) -> ENET2_DIV_SELECT_W

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&mut self) -> ENET2_REF_EN_W

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&mut self) -> ENET_25M_REF_EN_W

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

impl W<u32, Reg<u32, _PLL_ENET_TOG>>

pub fn div_select(&mut self) -> DIV_SELECT_W

Bits 0:1 - Controls the frequency of the ethernet reference clock

pub fn enet2_div_select(&mut self) -> ENET2_DIV_SELECT_W

Bits 2:3 - Controls the frequency of the ENET2 reference clock.

pub fn powerdown(&mut self) -> POWERDOWN_W

Bit 12 - Powers down the PLL.

pub fn enable(&mut self) -> ENABLE_W

Bit 13 - Enable the PLL providing the ENET reference clock.

pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W

Bits 14:15 - Determines the bypass source.

pub fn bypass(&mut self) -> BYPASS_W

Bit 16 - Bypass the PLL.

pub fn enet2_ref_en(&mut self) -> ENET2_REF_EN_W

Bit 20 - Enable the PLL providing the ENET2 reference clock

pub fn enet_25m_ref_en(&mut self) -> ENET_25M_REF_EN_W

Bit 21 - Enable the PLL providing ENET 25 MHz reference clock

impl W<u32, Reg<u32, _PFD_480>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_480_SET>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_480_CLR>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_480_TOG>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_528>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_528_SET>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_528_CLR>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _PFD_528_TOG>>

pub fn pfd0_frac(&mut self) -> PFD0_FRAC_W

Bits 0:5 - This field controls the fractional divide value

pub fn pfd0_clkgate(&mut self) -> PFD0_CLKGATE_W

Bit 7 - If set to 1, the IO fractional divider clock (reference ref_pfd0) is off (power savings)

pub fn pfd1_frac(&mut self) -> PFD1_FRAC_W

Bits 8:13 - This field controls the fractional divide value

pub fn pfd1_clkgate(&mut self) -> PFD1_CLKGATE_W

Bit 15 - IO Clock Gate

pub fn pfd2_frac(&mut self) -> PFD2_FRAC_W

Bits 16:21 - This field controls the fractional divide value

pub fn pfd2_clkgate(&mut self) -> PFD2_CLKGATE_W

Bit 23 - IO Clock Gate

pub fn pfd3_frac(&mut self) -> PFD3_FRAC_W

Bits 24:29 - This field controls the fractional divide value

pub fn pfd3_clkgate(&mut self) -> PFD3_CLKGATE_W

Bit 31 - IO Clock Gate

impl W<u32, Reg<u32, _MISC0>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&mut self) -> RTC_XTAL_SOURCE_W

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl W<u32, Reg<u32, _MISC0_SET>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&mut self) -> RTC_XTAL_SOURCE_W

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl W<u32, Reg<u32, _MISC0_CLR>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&mut self) -> RTC_XTAL_SOURCE_W

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl W<u32, Reg<u32, _MISC0_TOG>>

pub fn reftop_pwd(&mut self) -> REFTOP_PWD_W

Bit 0 - Control bit to power-down the analog bandgap reference circuitry

pub fn reftop_selfbiasoff(&mut self) -> REFTOP_SELFBIASOFF_W

Bit 3 - Control bit to disable the self-bias circuit in the analog bandgap

pub fn reftop_vbgadj(&mut self) -> REFTOP_VBGADJ_W

Bits 4:6 - Not related to CCM. See Power Management Unit (PMU)

pub fn reftop_vbgup(&mut self) -> REFTOP_VBGUP_W

Bit 7 - Status bit that signals the analog bandgap voltage is up and stable

pub fn stop_mode_config(&mut self) -> STOP_MODE_CONFIG_W

Bits 10:11 - Configure the analog behavior in stop mode.

pub fn discon_high_snvs(&mut self) -> DISCON_HIGH_SNVS_W

Bit 12 - This bit controls a switch from VDD_HIGH_IN to VDD_SNVS_IN.

pub fn osc_i(&mut self) -> OSC_I_W

Bits 13:14 - This field determines the bias current in the 24MHz oscillator

pub fn osc_xtalok_en(&mut self) -> OSC_XTALOK_EN_W

Bit 16 - This bit enables the detector that signals when the 24MHz crystal oscillator is stable

pub fn clkgate_ctrl(&mut self) -> CLKGATE_CTRL_W

Bit 25 - This bit allows disabling the clock gate (always ungated) for the xtal 24MHz clock that clocks the digital logic in the analog block

pub fn clkgate_delay(&mut self) -> CLKGATE_DELAY_W

Bits 26:28 - This field specifies the delay between powering up the XTAL 24MHz clock and releasing the clock to the digital logic inside the analog block

pub fn rtc_xtal_source(&mut self) -> RTC_XTAL_SOURCE_W

Bit 29 - This field indicates which chip source is being used for the rtc clock

pub fn xtal_24m_pwd(&mut self) -> XTAL_24M_PWD_W

Bit 30 - This field powers down the 24M crystal oscillator if set true

impl W<u32, Reg<u32, _MISC1>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC1_SET>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC1_CLR>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC1_TOG>>

pub fn lvds1_clk_sel(&mut self) -> LVDS1_CLK_SEL_W

Bits 0:4 - This field selects the clk to be routed to anaclk1/1b.

pub fn lvdsclk1_oben(&mut self) -> LVDSCLK1_OBEN_W

Bit 10 - This enables the LVDS output buffer for anaclk1/1b

pub fn lvdsclk1_iben(&mut self) -> LVDSCLK1_IBEN_W

Bit 12 - This enables the LVDS input buffer for anaclk1/1b

pub fn pfd_480_autogate_en(&mut self) -> PFD_480_AUTOGATE_EN_W

Bit 16 - This enables a feature that will clkgate (reset) all PFD_480 clocks anytime the USB1_PLL_480 is unlocked or powered off

pub fn pfd_528_autogate_en(&mut self) -> PFD_528_AUTOGATE_EN_W

Bit 17 - This enables a feature that will clkgate (reset) all PFD_528 clocks anytime the PLL_528 is unlocked or powered off

pub fn irq_temppanic(&mut self) -> IRQ_TEMPPANIC_W

Bit 27 - This status bit is set to one when the temperature sensor panic interrupt asserts for a panic high temperature

pub fn irq_templow(&mut self) -> IRQ_TEMPLOW_W

Bit 28 - This status bit is set to one when the temperature sensor low interrupt asserts for low temperature

pub fn irq_temphigh(&mut self) -> IRQ_TEMPHIGH_W

Bit 29 - This status bit is set to one when the temperature sensor high interrupt asserts for high temperature

pub fn irq_ana_bo(&mut self) -> IRQ_ANA_BO_W

Bit 30 - This status bit is set to one when when any of the analog regulator brownout interrupts assert

pub fn irq_dig_bo(&mut self) -> IRQ_DIG_BO_W

Bit 31 - This status bit is set to one when when any of the digital regulator brownout interrupts assert

impl W<u32, Reg<u32, _MISC2>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video

impl W<u32, Reg<u32, _MISC2_SET>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video

impl W<u32, Reg<u32, _MISC2_CLR>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video

impl W<u32, Reg<u32, _MISC2_TOG>>

pub fn reg0_enable_bo(&mut self) -> REG0_ENABLE_BO_W

Bit 5 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn pll3_disable(&mut self) -> PLL3_DISABLE_W

Bit 7 - When USB is in low power suspend mode this Control bit is used to indicate if other system peripherals require the USB PLL3 clock when the SoC is not in low power mode

pub fn reg1_enable_bo(&mut self) -> REG1_ENABLE_BO_W

Bit 13 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_lsb(&mut self) -> AUDIO_DIV_LSB_W

Bit 15 - LSB of Post-divider for Audio PLL

pub fn reg2_enable_bo(&mut self) -> REG2_ENABLE_BO_W

Bit 21 - Enables the brownout detection.Not related to CCM. See Power Management Unit (PMU)

pub fn audio_div_msb(&mut self) -> AUDIO_DIV_MSB_W

Bit 23 - MSB of Post-divider for Audio PLL

pub fn reg0_step_time(&mut self) -> REG0_STEP_TIME_W

Bits 24:25 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg1_step_time(&mut self) -> REG1_STEP_TIME_W

Bits 26:27 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn reg2_step_time(&mut self) -> REG2_STEP_TIME_W

Bits 28:29 - Number of clock periods (24MHz clock).Not related to CCM. See Power Management Unit (PMU)

pub fn video_div(&mut self) -> VIDEO_DIV_W

Bits 30:31 - Post-divider for video