1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314
#[doc = "Reader of register PLL_VIDEO_TOG"] pub type R = crate::R<u32, super::PLL_VIDEO_TOG>; #[doc = "Writer for register PLL_VIDEO_TOG"] pub type W = crate::W<u32, super::PLL_VIDEO_TOG>; #[doc = "Register PLL_VIDEO_TOG `reset()`'s with value 0x0001_100c"] impl crate::ResetValue for super::PLL_VIDEO_TOG { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x0001_100c } } #[doc = "Reader of field `DIV_SELECT`"] pub type DIV_SELECT_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DIV_SELECT`"] pub struct DIV_SELECT_W<'a> { w: &'a mut W, } impl<'a> DIV_SELECT_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f); self.w } } #[doc = "Reader of field `POWERDOWN`"] pub type POWERDOWN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `POWERDOWN`"] pub struct POWERDOWN_W<'a> { w: &'a mut W, } impl<'a> POWERDOWN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `ENABLE`"] pub type ENABLE_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ENABLE`"] pub struct ENABLE_W<'a> { w: &'a mut W, } impl<'a> ENABLE_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Determines the bypass source.\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum BYPASS_CLK_SRC_A { #[doc = "0: Select the 24MHz oscillator as source."] REF_CLK_24M = 0, #[doc = "1: Select the CLK1_N / CLK1_P as source."] CLK1 = 1, } impl From<BYPASS_CLK_SRC_A> for u8 { #[inline(always)] fn from(variant: BYPASS_CLK_SRC_A) -> Self { variant as _ } } #[doc = "Reader of field `BYPASS_CLK_SRC`"] pub type BYPASS_CLK_SRC_R = crate::R<u8, BYPASS_CLK_SRC_A>; impl BYPASS_CLK_SRC_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, BYPASS_CLK_SRC_A> { use crate::Variant::*; match self.bits { 0 => Val(BYPASS_CLK_SRC_A::REF_CLK_24M), 1 => Val(BYPASS_CLK_SRC_A::CLK1), i => Res(i), } } #[doc = "Checks if the value of the field is `REF_CLK_24M`"] #[inline(always)] pub fn is_ref_clk_24m(&self) -> bool { *self == BYPASS_CLK_SRC_A::REF_CLK_24M } #[doc = "Checks if the value of the field is `CLK1`"] #[inline(always)] pub fn is_clk1(&self) -> bool { *self == BYPASS_CLK_SRC_A::CLK1 } } #[doc = "Write proxy for field `BYPASS_CLK_SRC`"] pub struct BYPASS_CLK_SRC_W<'a> { w: &'a mut W, } impl<'a> BYPASS_CLK_SRC_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: BYPASS_CLK_SRC_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Select the 24MHz oscillator as source."] #[inline(always)] pub fn ref_clk_24m(self) -> &'a mut W { self.variant(BYPASS_CLK_SRC_A::REF_CLK_24M) } #[doc = "Select the CLK1_N / CLK1_P as source."] #[inline(always)] pub fn clk1(self) -> &'a mut W { self.variant(BYPASS_CLK_SRC_A::CLK1) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 14)) | (((value as u32) & 0x03) << 14); self.w } } #[doc = "Reader of field `BYPASS`"] pub type BYPASS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `BYPASS`"] pub struct BYPASS_W<'a> { w: &'a mut W, } impl<'a> BYPASS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "These bits implement a divider after the PLL, but before the enable and bypass mux.\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum POST_DIV_SELECT_A { #[doc = "0: Divide by 4."] POST_DIV_SELECT_0 = 0, #[doc = "1: Divide by 2."] POST_DIV_SELECT_1 = 1, #[doc = "2: Divide by 1."] POST_DIV_SELECT_2 = 2, } impl From<POST_DIV_SELECT_A> for u8 { #[inline(always)] fn from(variant: POST_DIV_SELECT_A) -> Self { variant as _ } } #[doc = "Reader of field `POST_DIV_SELECT`"] pub type POST_DIV_SELECT_R = crate::R<u8, POST_DIV_SELECT_A>; impl POST_DIV_SELECT_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> crate::Variant<u8, POST_DIV_SELECT_A> { use crate::Variant::*; match self.bits { 0 => Val(POST_DIV_SELECT_A::POST_DIV_SELECT_0), 1 => Val(POST_DIV_SELECT_A::POST_DIV_SELECT_1), 2 => Val(POST_DIV_SELECT_A::POST_DIV_SELECT_2), i => Res(i), } } #[doc = "Checks if the value of the field is `POST_DIV_SELECT_0`"] #[inline(always)] pub fn is_post_div_select_0(&self) -> bool { *self == POST_DIV_SELECT_A::POST_DIV_SELECT_0 } #[doc = "Checks if the value of the field is `POST_DIV_SELECT_1`"] #[inline(always)] pub fn is_post_div_select_1(&self) -> bool { *self == POST_DIV_SELECT_A::POST_DIV_SELECT_1 } #[doc = "Checks if the value of the field is `POST_DIV_SELECT_2`"] #[inline(always)] pub fn is_post_div_select_2(&self) -> bool { *self == POST_DIV_SELECT_A::POST_DIV_SELECT_2 } } #[doc = "Write proxy for field `POST_DIV_SELECT`"] pub struct POST_DIV_SELECT_W<'a> { w: &'a mut W, } impl<'a> POST_DIV_SELECT_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: POST_DIV_SELECT_A) -> &'a mut W { unsafe { self.bits(variant.into()) } } #[doc = "Divide by 4."] #[inline(always)] pub fn post_div_select_0(self) -> &'a mut W { self.variant(POST_DIV_SELECT_A::POST_DIV_SELECT_0) } #[doc = "Divide by 2."] #[inline(always)] pub fn post_div_select_1(self) -> &'a mut W { self.variant(POST_DIV_SELECT_A::POST_DIV_SELECT_1) } #[doc = "Divide by 1."] #[inline(always)] pub fn post_div_select_2(self) -> &'a mut W { self.variant(POST_DIV_SELECT_A::POST_DIV_SELECT_2) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 19)) | (((value as u32) & 0x03) << 19); self.w } } #[doc = "Reader of field `LOCK`"] pub type LOCK_R = crate::R<bool, bool>; impl R { #[doc = "Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."] #[inline(always)] pub fn div_select(&self) -> DIV_SELECT_R { DIV_SELECT_R::new((self.bits & 0x7f) as u8) } #[doc = "Bit 12 - Powers down the PLL."] #[inline(always)] pub fn powerdown(&self) -> POWERDOWN_R { POWERDOWN_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 13 - Enalbe PLL output"] #[inline(always)] pub fn enable(&self) -> ENABLE_R { ENABLE_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bits 14:15 - Determines the bypass source."] #[inline(always)] pub fn bypass_clk_src(&self) -> BYPASS_CLK_SRC_R { BYPASS_CLK_SRC_R::new(((self.bits >> 14) & 0x03) as u8) } #[doc = "Bit 16 - Bypass the PLL."] #[inline(always)] pub fn bypass(&self) -> BYPASS_R { BYPASS_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux."] #[inline(always)] pub fn post_div_select(&self) -> POST_DIV_SELECT_R { POST_DIV_SELECT_R::new(((self.bits >> 19) & 0x03) as u8) } #[doc = "Bit 31 - 1 - PLL is currently locked; 0 - PLL is not currently locked."] #[inline(always)] pub fn lock(&self) -> LOCK_R { LOCK_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bits 0:6 - This field controls the PLL loop divider. Valid range for DIV_SELECT divider value: 27~54."] #[inline(always)] pub fn div_select(&mut self) -> DIV_SELECT_W { DIV_SELECT_W { w: self } } #[doc = "Bit 12 - Powers down the PLL."] #[inline(always)] pub fn powerdown(&mut self) -> POWERDOWN_W { POWERDOWN_W { w: self } } #[doc = "Bit 13 - Enalbe PLL output"] #[inline(always)] pub fn enable(&mut self) -> ENABLE_W { ENABLE_W { w: self } } #[doc = "Bits 14:15 - Determines the bypass source."] #[inline(always)] pub fn bypass_clk_src(&mut self) -> BYPASS_CLK_SRC_W { BYPASS_CLK_SRC_W { w: self } } #[doc = "Bit 16 - Bypass the PLL."] #[inline(always)] pub fn bypass(&mut self) -> BYPASS_W { BYPASS_W { w: self } } #[doc = "Bits 19:20 - These bits implement a divider after the PLL, but before the enable and bypass mux."] #[inline(always)] pub fn post_div_select(&mut self) -> POST_DIV_SELECT_W { POST_DIV_SELECT_W { w: self } } }