Type Definition imxrt1062_can1::esr1::R

type R = R<u32, ESR1>;

Reader of register ESR1

Methods

impl R

pub fn wakint(&self) -> WAKINT_R

Bit 0 - When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm

pub fn errint(&self) -> ERRINT_R

Bit 1 - This bit indicates that at least one of the Error Bits (bits 15-10) is set

pub fn boffint(&self) -> BOFFINT_R

Bit 2 - This bit is set when FLEXCAN enters 'Bus Off' state

pub fn rx(&self) -> RX_R

Bit 3 - This bit indicates if FlexCAN is receiving a message. Refer to .

pub fn fltconf(&self) -> FLTCONF_R

Bits 4:5 - If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive"

pub fn tx(&self) -> TX_R

Bit 6 - This bit indicates if FLEXCAN is transmitting a message.Refer to .

pub fn idle(&self) -> IDLE_R

Bit 7 - This bit indicates when CAN bus is in IDLE state.Refer to .

pub fn rxwrn(&self) -> RXWRN_R

Bit 8 - This bit indicates when repetitive errors are occurring during message reception.

pub fn txwrn(&self) -> TXWRN_R

Bit 9 - This bit indicates when repetitive errors are occurring during message transmission.

pub fn stferr(&self) -> STFERR_R

Bit 10 - This bit indicates that a Stuffing Error has been detected.

pub fn frmerr(&self) -> FRMERR_R

Bit 11 - This bit indicates that a Form Error has been detected by the receiver node, i

pub fn crcerr(&self) -> CRCERR_R

Bit 12 - This bit indicates that a CRC Error has been detected by the receiver node, i

pub fn ackerr(&self) -> ACKERR_R

Bit 13 - This bit indicates that an Acknowledge Error has been detected by the transmitter node, i

pub fn bit0err(&self) -> BIT0ERR_R

Bit 14 - This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message

pub fn bit1err(&self) -> BIT1ERR_R

Bit 15 - This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message

pub fn rwrnint(&self) -> RWRNINT_R

Bit 16 - If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96

pub fn twrnint(&self) -> TWRNINT_R

Bit 17 - If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96

pub fn synch(&self) -> SYNCH_R

Bit 18 - This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process