Module imxrt1062_can1::esr1

Error and Status 1 Register

Structs

BOFFINT_W	Write proxy for field BOFFINT
ERRINT_W	Write proxy for field ERRINT
RWRNINT_W	Write proxy for field RWRNINT
TWRNINT_W	Write proxy for field TWRNINT
WAKINT_W	Write proxy for field WAKINT

Enums

ACKERR_A	This bit indicates that an Acknowledge Error has been detected by the transmitter node, i
BIT0ERR_A	This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message
BIT1ERR_A	This bit indicates when an inconsistency occurs between the transmitted and the received bit in a message
BOFFINT_A	This bit is set when FLEXCAN enters 'Bus Off' state
CRCERR_A	This bit indicates that a CRC Error has been detected by the receiver node, i
ERRINT_A	This bit indicates that at least one of the Error Bits (bits 15-10) is set
FLTCONF_A	If the LOM bit in the Control Register is asserted, after some delay that depends on the CAN bit timing the FLT_CONF field will indicate "Error Passive"
FRMERR_A	This bit indicates that a Form Error has been detected by the receiver node, i
IDLE_A	This bit indicates when CAN bus is in IDLE state.Refer to .
RWRNINT_A	If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96
RXWRN_A	This bit indicates when repetitive errors are occurring during message reception.
RX_A	This bit indicates if FlexCAN is receiving a message. Refer to .
STFERR_A	This bit indicates that a Stuffing Error has been detected.
SYNCH_A	This read-only flag indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the communication process
TWRNINT_A	If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96
TXWRN_A	This bit indicates when repetitive errors are occurring during message transmission.
TX_A	This bit indicates if FLEXCAN is transmitting a message.Refer to .
WAKINT_A	When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm

Type Definitions

ACKERR_R	Reader of field ACKERR
BIT0ERR_R	Reader of field BIT0ERR
BIT1ERR_R	Reader of field BIT1ERR
BOFFINT_R	Reader of field BOFFINT
CRCERR_R	Reader of field CRCERR
ERRINT_R	Reader of field ERRINT
FLTCONF_R	Reader of field FLTCONF
FRMERR_R	Reader of field FRMERR
IDLE_R	Reader of field IDLE
R	Reader of register ESR1
RWRNINT_R	Reader of field RWRNINT
RXWRN_R	Reader of field RXWRN
RX_R	Reader of field RX
STFERR_R	Reader of field STFERR
SYNCH_R	Reader of field SYNCH
TWRNINT_R	Reader of field TWRNINT
TXWRN_R	Reader of field TXWRN
TX_R	Reader of field TX
W	Writer for register ESR1
WAKINT_R	Reader of field WAKINT