[][src]Type Definition imxrt1062_can1::ctrl1::W

type W = W<u32, CTRL1>;

Writer for register CTRL1

Methods

impl W[src]

pub fn propseg(&mut self) -> PROPSEG_W[src]

Bits 0:2 - This 3-bit field defines the length of the Propagation Segment in the bit time

pub fn lom(&mut self) -> LOM_W[src]

Bit 3 - This bit configures FLEXCAN to operate in Listen Only Mode

pub fn lbuf(&mut self) -> LBUF_W[src]

Bit 4 - This bit defines the ordering mechanism for Message Buffer transmission

pub fn tsyn(&mut self) -> TSYN_W[src]

Bit 5 - This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0

pub fn boffrec(&mut self) -> BOFFREC_W[src]

Bit 6 - This bit defines how FLEXCAN recovers from Bus Off state

pub fn smp(&mut self) -> SMP_W[src]

Bit 7 - This bit defines the sampling mode of CAN bits at the FLEXCAN_RX

pub fn rwrnmsk(&mut self) -> RWRNMSK_W[src]

Bit 10 - This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register

pub fn twrnmsk(&mut self) -> TWRNMSK_W[src]

Bit 11 - This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register

pub fn lpb(&mut self) -> LPB_W[src]

Bit 12 - This bit configures FlexCAN to operate in Loop-Back Mode

pub fn errmsk(&mut self) -> ERRMSK_W[src]

Bit 14 - This bit provides a mask for the Error Interrupt.

pub fn boffmsk(&mut self) -> BOFFMSK_W[src]

Bit 15 - This bit provides a mask for the Bus Off Interrupt.

pub fn pseg2(&mut self) -> PSEG2_W[src]

Bits 16:18 - This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time

pub fn pseg1(&mut self) -> PSEG1_W[src]

Bits 19:21 - This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time

pub fn rjw(&mut self) -> RJW_W[src]

Bits 22:23 - This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period

pub fn presdiv(&mut self) -> PRESDIV_W[src]

Bits 24:31 - This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency