Struct imxrt1062_can1::W

pub struct W<U, REG> { /* fields omitted */ }

Register writer

Used as an argument to the closures in the write and modify methods of the register

Methods

impl<U, REG> W<U, REG>

pub unsafe fn bits(&mut self, bits: U) -> &mut Self

Writes raw bits to the register

impl W<u32, Reg<u32, _MCR>>

pub fn maxmb(&mut self) -> MAXMB_W

Bits 0:6 - This 7-bit field defines the number of the last Message Buffers that will take part in the matching and arbitration processes

pub fn idam(&mut self) -> IDAM_W

Bits 8:9 - This 2-bit field identifies the format of the elements of the Rx FIFO filter table, as shown below

pub fn aen(&mut self) -> AEN_W

Bit 12 - This bit is supplied for backwards compatibility reasons

pub fn lprioen(&mut self) -> LPRIOEN_W

Bit 13 - This bit is provided for backwards compatibility reasons

pub fn irmq(&mut self) -> IRMQ_W

Bit 16 - This bit indicates whether Rx matching process will be based either on individual masking and queue or on masking scheme with RXMGMASK, RX14MASK and RX15MASK, RXFGMASK

pub fn srxdis(&mut self) -> SRXDIS_W

Bit 17 - This bit defines whether FlexCAN is allowed to receive frames transmitted by itself

pub fn waksrc(&mut self) -> WAKSRC_W

Bit 19 - This bit defines whether the integrated low-pass filter is applied to protect the FLEXCAN_RX input from spurious wake up

pub fn wrnen(&mut self) -> WRNEN_W

Bit 21 - When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and Status Register

pub fn slfwak(&mut self) -> SLFWAK_W

Bit 22 - This bit enables the Self Wake Up feature when FLEXCAN is in Stop Mode

pub fn supv(&mut self) -> SUPV_W

Bit 23 - This bit configures some of the FLEXCAN registers to be either in Supervisor or User Mode

pub fn softrst(&mut self) -> SOFTRST_W

Bit 25 - When this bit is asserted, FlexCAN resets its internal state machines and some of the memory mapped registers

pub fn wakmsk(&mut self) -> WAKMSK_W

Bit 26 - This bit enables the Wake Up Interrupt generation.

pub fn halt(&mut self) -> HALT_W

Bit 28 - Assertion of this bit puts the FLEXCAN module into Freeze Mode

pub fn rfen(&mut self) -> RFEN_W

Bit 29 - This bit controls whether the Rx FIFO feature is enabled or not

pub fn frz(&mut self) -> FRZ_W

Bit 30 - The FRZ bit specifies the FLEXCAN behavior when the HALT bit in the MCR Register is set or when Debug Mode is requested at Arm level

pub fn mdis(&mut self) -> MDIS_W

Bit 31 - This bit controls whether FLEXCAN is enabled or not

impl W<u32, Reg<u32, _CTRL1>>

pub fn propseg(&mut self) -> PROPSEG_W

Bits 0:2 - This 3-bit field defines the length of the Propagation Segment in the bit time

pub fn lom(&mut self) -> LOM_W

Bit 3 - This bit configures FLEXCAN to operate in Listen Only Mode

pub fn lbuf(&mut self) -> LBUF_W

Bit 4 - This bit defines the ordering mechanism for Message Buffer transmission

pub fn tsyn(&mut self) -> TSYN_W

Bit 5 - This bit enables a mechanism that resets the free-running timer each time a message is received in Message Buffer 0

pub fn boffrec(&mut self) -> BOFFREC_W

Bit 6 - This bit defines how FLEXCAN recovers from Bus Off state

pub fn smp(&mut self) -> SMP_W

Bit 7 - This bit defines the sampling mode of CAN bits at the FLEXCAN_RX

pub fn rwrnmsk(&mut self) -> RWRNMSK_W

Bit 10 - This bit provides a mask for the Rx Warning Interrupt associated with the RWRN_INT flag in the Error and Status Register

pub fn twrnmsk(&mut self) -> TWRNMSK_W

Bit 11 - This bit provides a mask for the Tx Warning Interrupt associated with the TWRN_INT flag in the Error and Status Register

pub fn lpb(&mut self) -> LPB_W

Bit 12 - This bit configures FlexCAN to operate in Loop-Back Mode

pub fn errmsk(&mut self) -> ERRMSK_W

Bit 14 - This bit provides a mask for the Error Interrupt.

pub fn boffmsk(&mut self) -> BOFFMSK_W

Bit 15 - This bit provides a mask for the Bus Off Interrupt.

pub fn pseg2(&mut self) -> PSEG2_W

Bits 16:18 - This 3-bit field defines the length of Phase Buffer Segment 2 in the bit time

pub fn pseg1(&mut self) -> PSEG1_W

Bits 19:21 - This 3-bit field defines the length of Phase Buffer Segment 1 in the bit time

pub fn rjw(&mut self) -> RJW_W

Bits 22:23 - This 2-bit field defines the maximum number of time quanta One time quantum is equal to the Sclock period

pub fn presdiv(&mut self) -> PRESDIV_W

Bits 24:31 - This 8-bit field defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency

impl W<u32, Reg<u32, _TIMER>>

pub fn timer(&mut self) -> TIMER_W

Bits 0:15 - TIMER

impl W<u32, Reg<u32, _RXMGMASK>>

pub fn mg(&mut self) -> MG_W

Bits 0:31 - These bits mask the Mailbox filter bits as shown in the figure above

impl W<u32, Reg<u32, _RX14MASK>>

pub fn rx14m(&mut self) -> RX14M_W

Bits 0:31 - These bits mask Mailbox 14 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register )

impl W<u32, Reg<u32, _RX15MASK>>

pub fn rx15m(&mut self) -> RX15M_W

Bits 0:31 - These bits mask Mailbox 15 filter bits in the same fashion as RXMGMASK masks other Mailboxes filters (see RXMGMASKRx Mailboxes Global Mask Register )

impl W<u32, Reg<u32, _ECR>>

pub fn tx_err_counter(&mut self) -> TX_ERR_COUNTER_W

Bits 0:7 - Tx_Err_Counter

pub fn rx_err_counter(&mut self) -> RX_ERR_COUNTER_W

Bits 8:15 - Rx_Err_Counter

impl W<u32, Reg<u32, _ESR1>>

pub fn wakint(&mut self) -> WAKINT_W

Bit 0 - When FLEXCAN is Stop Mode and a recessive to dominant transition is detected on the CAN bus and if the WAK_MSK bit in the MCR Register is set, an interrupt is generated to the Arm

pub fn errint(&mut self) -> ERRINT_W

Bit 1 - This bit indicates that at least one of the Error Bits (bits 15-10) is set

pub fn boffint(&mut self) -> BOFFINT_W

Bit 2 - This bit is set when FLEXCAN enters 'Bus Off' state

pub fn rwrnint(&mut self) -> RWRNINT_W

Bit 16 - If the WRN_EN bit in MCR is asserted, the RWRN_INT bit is set when the RX_WRN flag transition from '0' to '1', meaning that the Rx error counters reached 96

pub fn twrnint(&mut self) -> TWRNINT_W

Bit 17 - If the WRN_EN bit in MCR is asserted, the TWRN_INT bit is set when the TX_WRN flag transition from '0' to '1', meaning that the Tx error counter reached 96

impl W<u32, Reg<u32, _IMASK2>>

pub fn bufhm(&mut self) -> BUFHM_W

Bits 0:31 - Each bit enables or disables the respective FLEXCAN Message Buffer (MB32 to MB63) Interrupt

impl W<u32, Reg<u32, _IMASK1>>

pub fn buflm(&mut self) -> BUFLM_W

Bits 0:31 - Each bit enables or disables the respective FLEXCAN Message Buffer (MB0 to MB31) Interrupt

impl W<u32, Reg<u32, _IFLAG2>>

pub fn bufhi(&mut self) -> BUFHI_W

Bits 0:31 - Each bit flags the respective FLEXCAN Message Buffer (MB32 to MB63) interrupt.

impl W<u32, Reg<u32, _IFLAG1>>

pub fn buf4to0i(&mut self) -> BUF4TO0I_W

Bits 0:4 - If the Rx FIFO is not enabled, these bits flag the interrupts for MB0 to MB4

pub fn buf5i(&mut self) -> BUF5I_W

Bit 5 - If the Rx FIFO is not enabled, this bit flags the interrupt for MB5

pub fn buf6i(&mut self) -> BUF6I_W

Bit 6 - If the Rx FIFO is not enabled, this bit flags the interrupt for MB6

pub fn buf7i(&mut self) -> BUF7I_W

Bit 7 - If the Rx FIFO is not enabled, this bit flags the interrupt for MB7

pub fn buf31to8i(&mut self) -> BUF31TO8I_W

Bits 8:31 - Each bit flags the respective FLEXCAN Message Buffer (MB8 to MB31) interrupt.

impl W<u32, Reg<u32, _CTRL2>>

pub fn eacen(&mut self) -> EACEN_W

Bit 16 - This bit controls the comparison of IDE and RTR bits within Rx Mailboxes filters with their corresponding bits in the incoming frame by the matching process

pub fn rrs(&mut self) -> RRS_W

Bit 17 - If this bit is asserted Remote Request Frame is submitted to a matching process and stored in the corresponding Message Buffer in the same fashion of a Data Frame

pub fn mrp(&mut self) -> MRP_W

Bit 18 - If this bit is set the matching process starts from the Mailboxes and if no match occurs the matching continues on the Rx FIFO

pub fn tasd(&mut self) -> TASD_W

Bits 19:23 - This 5-bit field indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus

pub fn rffn(&mut self) -> RFFN_W

Bits 24:27 - This 4-bit field defines the number of Rx FIFO filters according to

pub fn wrmfrz(&mut self) -> WRMFRZ_W

Bit 28 - Enable unrestricted write access to FlexCAN memory in Freeze mode

impl W<u32, Reg<u32, _RXFGMASK>>

pub fn fgm(&mut self) -> FGM_W

Bits 0:31 - These bits mask the ID Filter Table elements bits in a perfect alignment

impl W<u32, Reg<u32, _RXIMR>>

pub fn mi(&mut self) -> MI_W

Bits 0:31 - These bits mask both Mailbox filter and Rx FIFO ID Filter Table element in distinct ways

impl W<u32, Reg<u32, _GFWR>>

pub fn gfwr(&mut self) -> GFWR_W

Bits 0:7 - It determines the Glitch Filter Width