Struct CoreInfo 

pub struct CoreInfo {
    pub id: usize,
    pub socket_id: usize,
    pub core_type: CoreType,
    pub logical_processor_ids: Vec<usize>,
    pub l1_instruction_cache: Option<CacheInfo>,
    pub l1_data_cache: Option<CacheInfo>,
    pub l2_cache: Option<CacheInfo>,
}

Represents detailed information about a single physical CPU core.

This structure provides data about a core’s identification, its type (especially in hybrid architectures), the logical processors (hardware threads) it hosts, and information about its dedicated or closely associated caches (L1, L2).

Fields

id: usize

A unique identifier for this physical core across the entire system (all sockets).

This ID is assigned by the library and may not directly correspond to OS-level core IDs.

socket_id: usize

The identifier of the CPU socket (physical package) to which this core belongs.

core_type: CoreType

The architectural type of this core (e.g., Performance or Efficiency).

This is particularly relevant for hybrid CPUs. For non-hybrid CPUs, this defaults to CoreType::Performance.

logical_processor_ids: Vec<usize>

A list of OS-specific identifiers for the logical processors (hardware threads) that are executed on this physical core.

For cores without Hyper-Threading/SMT, this will typically contain one ID. For cores with Hyper-Threading/SMT, it will contain multiple IDs (e.g., two for HT). These IDs can be used for setting thread affinity.

l1_instruction_cache: Option<CacheInfo>

Information about the L1 instruction cache specific to this core, if available and detected.

L1 instruction caches (L1i) store frequently executed instructions.

l1_data_cache: Option<CacheInfo>

Information about the L1 data cache specific to this core, if available and detected.

L1 data caches (L1d) store frequently accessed data.

l2_cache: Option<CacheInfo>

Information about the L2 cache associated with this core, if available and detected.

L2 caches are generally larger and slower than L1 caches. They might be exclusive to this core or shared with a small cluster of other cores, depending on the CPU architecture.

Trait Implementations

impl Clone for CoreInfo

fn clone(&self) -> CoreInfo

Returns a duplicate of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for CoreInfo

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.