gdt_cpus/cpu/
core_info.rs

1use super::{CacheInfo, CoreType};
2
3/// Represents detailed information about a single physical CPU core.
4///
5/// This structure provides data about a core's identification, its type (especially
6/// in hybrid architectures), the logical processors (hardware threads) it hosts,
7/// and information about its dedicated or closely associated caches (L1, L2).
8#[derive(Debug, Clone)]
9#[cfg_attr(feature = "serde", derive(serde::Serialize, serde::Deserialize))]
10pub struct CoreInfo {
11    /// A unique identifier for this physical core across the entire system (all sockets).
12    ///
13    /// This ID is assigned by the library and may not directly correspond to OS-level core IDs.
14    pub id: usize,
15    /// The identifier of the CPU socket (physical package) to which this core belongs.
16    pub socket_id: usize,
17    /// The architectural type of this core (e.g., Performance or Efficiency).
18    ///
19    /// This is particularly relevant for hybrid CPUs. For non-hybrid CPUs,
20    /// this defaults to `CoreType::Performance`.
21    pub core_type: CoreType,
22    /// A list of OS-specific identifiers for the logical processors (hardware threads)
23    /// that are executed on this physical core.
24    ///
25    /// For cores without Hyper-Threading/SMT, this will typically contain one ID.
26    /// For cores with Hyper-Threading/SMT, it will contain multiple IDs (e.g., two for HT).
27    /// These IDs can be used for setting thread affinity.
28    pub logical_processor_ids: Vec<usize>,
29
30    /// Information about the L1 instruction cache specific to this core, if available and detected.
31    ///
32    /// L1 instruction caches (L1i) store frequently executed instructions.
33    pub l1_instruction_cache: Option<CacheInfo>,
34    /// Information about the L1 data cache specific to this core, if available and detected.
35    ///
36    /// L1 data caches (L1d) store frequently accessed data.
37    pub l1_data_cache: Option<CacheInfo>,
38    /// Information about the L2 cache associated with this core, if available and detected.
39    ///
40    /// L2 caches are generally larger and slower than L1 caches. They might be exclusive
41    /// to this core or shared with a small cluster of other cores, depending on the CPU architecture.
42    pub l2_cache: Option<CacheInfo>,
43}
gdt_cpus/cpu/core_info.rs

gdt_cpus/cpu/
core_info.rs
