[−][src]Struct gd32vf103_pac::dma1::RegisterBlock

#[repr(C)]pub struct RegisterBlock {
    pub intf: INTF,
    pub intc: INTC,
    pub ch0ctl: CH0CTL,
    pub ch0cnt: CH0CNT,
    pub ch0paddr: CH0PADDR,
    pub ch0maddr: CH0MADDR,
    pub ch1ctl: CH1CTL,
    pub ch1cnt: CH1CNT,
    pub ch1paddr: CH1PADDR,
    pub ch1maddr: CH1MADDR,
    pub ch2ctl: CH2CTL,
    pub ch2cnt: CH2CNT,
    pub ch2paddr: CH2PADDR,
    pub ch2maddr: CH2MADDR,
    pub ch3ctl: CH3CTL,
    pub ch3cnt: CH3CNT,
    pub ch3paddr: CH3PADDR,
    pub ch3maddr: CH3MADDR,
    pub ch4ctl: CH4CTL,
    pub ch4cnt: CH4CNT,
    pub ch4paddr: CH4PADDR,
    pub ch4maddr: CH4MADDR,
    // some fields omitted
}

Register block

Fields

intf: INTF

0x00 - Interrupt flag register

intc: INTC

0x04 - Interrupt flag clear register

ch0ctl: CH0CTL

0x08 - Channel 0 control register

ch0cnt: CH0CNT

0x0c - Channel 0 counter register

ch0paddr: CH0PADDR

0x10 - Channel 0 peripheral base address register

ch0maddr: CH0MADDR

0x14 - Channel 0 memory base address register

ch1ctl: CH1CTL

0x1c - Channel 1 control register

ch1cnt: CH1CNT

0x20 - Channel 1 counter register

ch1paddr: CH1PADDR

0x24 - Channel 1 peripheral base address register

ch1maddr: CH1MADDR

0x28 - Channel 1 memory base address register

ch2ctl: CH2CTL

0x30 - Channel 2 control register

ch2cnt: CH2CNT

0x34 - Channel 2 counter register

ch2paddr: CH2PADDR

0x38 - Channel 2 peripheral base address register

ch2maddr: CH2MADDR

0x3c - Channel 2 memory base address register

ch3ctl: CH3CTL

0x44 - Channel 3 control register

ch3cnt: CH3CNT

0x48 - Channel 3 counter register

ch3paddr: CH3PADDR

0x4c - Channel 3 peripheral base address register

ch3maddr: CH3MADDR

0x50 - Channel 3 memory base address register

ch4ctl: CH4CTL

0x58 - Channel 4 control register

ch4cnt: CH4CNT

0x5c - Channel 4 counter register

ch4paddr: CH4PADDR

0x60 - Channel 4 peripheral base address register

ch4maddr: CH4MADDR

0x64 - Channel 4 memory base address register

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