[][src]Module gd32vf103_pac::dma1

Direct memory access controller

Modules

ch0cnt

Channel 0 counter register

ch0ctl

Channel 0 control register

ch0maddr

Channel 0 memory base address register

ch0paddr

Channel 0 peripheral base address register

ch1cnt

Channel 1 counter register

ch1ctl

Channel 1 control register

ch1maddr

Channel 1 memory base address register

ch1paddr

Channel 1 peripheral base address register

ch2cnt

Channel 2 counter register

ch2ctl

Channel 2 control register

ch2maddr

Channel 2 memory base address register

ch2paddr

Channel 2 peripheral base address register

ch3cnt

Channel 3 counter register

ch3ctl

Channel 3 control register

ch3maddr

Channel 3 memory base address register

ch3paddr

Channel 3 peripheral base address register

ch4cnt

Channel 4 counter register

ch4ctl

Channel 4 control register

ch4maddr

Channel 4 memory base address register

ch4paddr

Channel 4 peripheral base address register

intc

Interrupt flag clear register

intf

Interrupt flag register

Structs

RegisterBlock

Register block

Type Definitions

CH0CNT

Channel 0 counter register

CH0CTL

Channel 0 control register

CH0MADDR

Channel 0 memory base address register

CH0PADDR

Channel 0 peripheral base address register

CH1CNT

Channel 1 counter register

CH1CTL

Channel 1 control register

CH1MADDR

Channel 1 memory base address register

CH1PADDR

Channel 1 peripheral base address register

CH2CNT

Channel 2 counter register

CH2CTL

Channel 2 control register

CH2MADDR

Channel 2 memory base address register

CH2PADDR

Channel 2 peripheral base address register

CH3CNT

Channel 3 counter register

CH3CTL

Channel 3 control register

CH3MADDR

Channel 3 memory base address register

CH3PADDR

Channel 3 peripheral base address register

CH4CNT

Channel 4 counter register

CH4CTL

Channel 4 control register

CH4MADDR

Channel 4 memory base address register

CH4PADDR

Channel 4 peripheral base address register

INTC

Interrupt flag clear register

INTF

Interrupt flag register