Module gd32f1::gd32f130::dma [−][src]
DMA controller
Modules
| ch0cnt | DMA channel 0 counter register |
| ch0ctl0 | DMA channel configuration register (DMA_CH0CTL0) |
| ch0maddr | DMA channel 0 memory base address register |
| ch0paddr | DMA channel 0 peripheral base address register |
| ch1cnt | DMA channel 1 counter register |
| ch1ctl0 | DMA channel configuration register (DMA_CH1CTL0) |
| ch1maddr | DMA channel 1 memory base address register |
| ch1paddr | DMA channel 1 peripheral base address register |
| ch2cnt | DMA channel 2 counter register |
| ch2ctl0 | DMA channel configuration register (DMA_CH2CTL0) |
| ch2maddr | DMA channel 2 memory base address register |
| ch2paddr | DMA channel 2 peripheral base address register |
| ch3cnt | DMA channel 3 counter register |
| ch3ctl0 | DMA channel configuration register (DMA_CH3CTL0) |
| ch3maddr | DMA channel 3 memory base address register |
| ch3paddr | DMA channel 3 peripheral base address register |
| ch4cnt | DMA channel 4 counter register |
| ch4ctl0 | DMA channel configuration register (DMA_CH4CTL0) |
| ch4maddr | DMA channel 4 memory base address register |
| ch4paddr | DMA channel 4 peripheral base address register |
| ch5cnt | DMA channel 5 counter register |
| ch5ctl0 | DMA channel configuration register (DMA_CH5CTL0) |
| ch5maddr | DMA channel 5 memory base address register |
| ch5paddr | DMA channel 5 peripheral base address register |
| ch6cnt | DMA channel 6 counter register |
| ch6ctl0 | DMA channel configuration register (DMA_CH6CTL0) |
| ch6maddr | DMA channel 6 memory base address register |
| ch6paddr | DMA channel 6 peripheral base address register |
| intc | DMA interrupt flag clear register (DMA_INTC) |
| intf | DMA interrupt flag register (DMA_INTF) |
Structs
| RegisterBlock | Register block |
Type Definitions
| CH0CNT | DMA channel 0 counter register |
| CH0CTL0 | DMA channel configuration register (DMA_CH0CTL0) |
| CH0MADDR | DMA channel 0 memory base address register |
| CH0PADDR | DMA channel 0 peripheral base address register |
| CH1CNT | DMA channel 1 counter register |
| CH1CTL0 | DMA channel configuration register (DMA_CH1CTL0) |
| CH1MADDR | DMA channel 1 memory base address register |
| CH1PADDR | DMA channel 1 peripheral base address register |
| CH2CNT | DMA channel 2 counter register |
| CH2CTL0 | DMA channel configuration register (DMA_CH2CTL0) |
| CH2MADDR | DMA channel 2 memory base address register |
| CH2PADDR | DMA channel 2 peripheral base address register |
| CH3CNT | DMA channel 3 counter register |
| CH3CTL0 | DMA channel configuration register (DMA_CH3CTL0) |
| CH3MADDR | DMA channel 3 memory base address register |
| CH3PADDR | DMA channel 3 peripheral base address register |
| CH4CNT | DMA channel 4 counter register |
| CH4CTL0 | DMA channel configuration register (DMA_CH4CTL0) |
| CH4MADDR | DMA channel 4 memory base address register |
| CH4PADDR | DMA channel 4 peripheral base address register |
| CH5CNT | DMA channel 5 counter register |
| CH5CTL0 | DMA channel configuration register (DMA_CH5CTL0) |
| CH5MADDR | DMA channel 5 memory base address register |
| CH5PADDR | DMA channel 5 peripheral base address register |
| CH6CNT | DMA channel 6 counter register |
| CH6CTL0 | DMA channel configuration register (DMA_CH6CTL0) |
| CH6MADDR | DMA channel 6 memory base address register |
| CH6PADDR | DMA channel 6 peripheral base address register |
| INTC | DMA interrupt flag clear register (DMA_INTC) |
| INTF | DMA interrupt flag register (DMA_INTF) |