Expand description
DMA controller
Modules§
- DMA channel 0 counter register
- DMA channel configuration register (DMA_CH0CTL0)
- DMA channel 0 memory base address register
- DMA channel 0 peripheral base address register
- DMA channel 1 counter register
- DMA channel configuration register (DMA_CH1CTL0)
- DMA channel 1 memory base address register
- DMA channel 1 peripheral base address register
- DMA channel 2 counter register
- DMA channel configuration register (DMA_CH2CTL0)
- DMA channel 2 memory base address register
- DMA channel 2 peripheral base address register
- DMA channel 3 counter register
- DMA channel configuration register (DMA_CH3CTL0)
- DMA channel 3 memory base address register
- DMA channel 3 peripheral base address register
- DMA channel 4 counter register
- DMA channel configuration register (DMA_CH4CTL0)
- DMA channel 4 memory base address register
- DMA channel 4 peripheral base address register
- DMA channel 5 counter register
- DMA channel configuration register (DMA_CH5CTL0)
- DMA channel 5 memory base address register
- DMA channel 5 peripheral base address register
- DMA channel 6 counter register
- DMA channel configuration register (DMA_CH6CTL0)
- DMA channel 6 memory base address register
- DMA channel 6 peripheral base address register
- DMA interrupt flag clear register (DMA_INTC)
- DMA interrupt flag register (DMA_INTF)
Structs§
- Register block
Type Aliases§
- CH0CNT (rw) register accessor: DMA channel 0 counter register
- CH0CTL (rw) register accessor: DMA channel configuration register (DMA_CH0CTL0)
- CH0MADDR (rw) register accessor: DMA channel 0 memory base address register
- CH0PADDR (rw) register accessor: DMA channel 0 peripheral base address register
- CH1CNT (rw) register accessor: DMA channel 1 counter register
- CH1CTL (rw) register accessor: DMA channel configuration register (DMA_CH1CTL0)
- CH1MADDR (rw) register accessor: DMA channel 1 memory base address register
- CH1PADDR (rw) register accessor: DMA channel 1 peripheral base address register
- CH2CNT (rw) register accessor: DMA channel 2 counter register
- CH2CTL (rw) register accessor: DMA channel configuration register (DMA_CH2CTL0)
- CH2MADDR (rw) register accessor: DMA channel 2 memory base address register
- CH2PADDR (rw) register accessor: DMA channel 2 peripheral base address register
- CH3CNT (rw) register accessor: DMA channel 3 counter register
- CH3CTL (rw) register accessor: DMA channel configuration register (DMA_CH3CTL0)
- CH3MADDR (rw) register accessor: DMA channel 3 memory base address register
- CH3PADDR (rw) register accessor: DMA channel 3 peripheral base address register
- CH4CNT (rw) register accessor: DMA channel 4 counter register
- CH4CTL (rw) register accessor: DMA channel configuration register (DMA_CH4CTL0)
- CH4MADDR (rw) register accessor: DMA channel 4 memory base address register
- CH4PADDR (rw) register accessor: DMA channel 4 peripheral base address register
- CH5CNT (rw) register accessor: DMA channel 5 counter register
- CH5CTL (rw) register accessor: DMA channel configuration register (DMA_CH5CTL0)
- CH5MADDR (rw) register accessor: DMA channel 5 memory base address register
- CH5PADDR (rw) register accessor: DMA channel 5 peripheral base address register
- CH6CNT (rw) register accessor: DMA channel 6 counter register
- CH6CTL (rw) register accessor: DMA channel configuration register (DMA_CH6CTL0)
- CH6MADDR (rw) register accessor: DMA channel 6 memory base address register
- CH6PADDR (rw) register accessor: DMA channel 6 peripheral base address register
- INTC (w) register accessor: DMA interrupt flag clear register (DMA_INTC)
- INTF (r) register accessor: DMA interrupt flag register (DMA_INTF)