pub trait Simd:
ExtractToken<S = Self>
+ Sized
+ Clone
+ Copy
+ Send
+ Sync
+ Debug
+ Seal
+ ArchTypes
+ 'static {
Show 2120 associated items
type f32s: SimdFloat<Self, Element = f32, Block = f32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtFloat<Self::u32s> + SimdCvtFloat<Self::i32s> + SimdWiden<Self, Widened = Self::f64s>;
type f64s: SimdFloat<Self, Element = f64, Block = f64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtFloat<Self::u64s> + SimdCvtFloat<Self::i64s> + SimdNarrow<Self, Narrowed = Self::f32s>;
type u8s: SimdInt<Self, Element = u8, Block = u8x16<Self>, Mask = Self::mask8s, ByteVector = Self::u8s> + SimdIntWiden<Self, Widened = Self::u16s>;
type i8s: SimdInt<Self, Element = i8, Block = i8x16<Self>, Mask = Self::mask8s, ByteVector = Self::u8s> + SimdIntWiden<Self, Widened = Self::i16s> + Neg<Output = Self::i8s>;
type u16s: SimdInt<Self, Element = u16, Block = u16x8<Self>, Mask = Self::mask16s, ByteVector = Self::u8s> + SimdNarrow<Self, Narrowed = Self::u8s> + SimdIntWiden<Self, Widened = Self::u32s>;
type i16s: SimdInt<Self, Element = i16, Block = i16x8<Self>, Mask = Self::mask16s, ByteVector = Self::u8s> + SimdNarrow<Self, Narrowed = Self::i8s> + SimdIntWiden<Self, Widened = Self::i32s> + Neg<Output = Self::i16s>;
type u32s: SimdInt<Self, Element = u32, Block = u32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f32s> + SimdNarrow<Self, Narrowed = Self::u16s> + SimdIntWiden<Self, Widened = Self::u64s>;
type i32s: SimdInt<Self, Element = i32, Block = i32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f32s> + SimdNarrow<Self, Narrowed = Self::i16s> + SimdIntWiden<Self, Widened = Self::i64s> + Neg<Output = Self::i32s>;
type u64s: SimdInt<Self, Element = u64, Block = u64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f64s> + SimdNarrow<Self, Narrowed = Self::u32s>;
type i64s: SimdInt<Self, Element = i64, Block = i64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f64s> + SimdNarrow<Self, Narrowed = Self::i32s> + Neg<Output = Self::i64s>;
type mask8s: SimdMask<Self, Element = i8, Ints = Self::i8s> + Select<Self::u8s> + Select<Self::i8s> + Select<Self::mask8s> + MaskWiden<Self, Widened = Self::mask16s>;
type mask16s: SimdMask<Self, Element = i16, Ints = Self::i16s> + Select<Self::u16s> + Select<Self::i16s> + Select<Self::mask16s> + MaskNarrow<Self, Narrowed = Self::mask8s> + MaskWiden<Self, Widened = Self::mask32s>;
type mask32s: SimdMask<Self, Element = i32, Ints = Self::i32s> + Select<Self::f32s> + Select<Self::u32s> + Select<Self::i32s> + Select<Self::mask32s> + MaskNarrow<Self, Narrowed = Self::mask16s> + MaskWiden<Self, Widened = Self::mask64s>;
type mask64s: SimdMask<Self, Element = i64, Ints = Self::i64s> + Select<Self::f64s> + Select<Self::u64s> + Select<Self::i64s> + Select<Self::mask64s> + MaskNarrow<Self, Narrowed = Self::mask32s>;
// Required methods
fn level(self) -> Level;
fn vectorize<F: FnOnce() -> R, R>(self, f: F) -> R;
fn abs_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn splat_f32x4(self, val: f32) -> f32x4<Self>;
fn reverse_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn slide_f32x4<const SHIFT: usize>(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> f32x4<Self>;
fn compress_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
) -> f32x4<Self>;
fn compress_merge_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
merge: f32x4<Self>,
) -> f32x4<Self>;
fn expand_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
) -> f32x4<Self>;
fn expand_merge_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
merge: f32x4<Self>,
) -> f32x4<Self>;
fn neg_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn sqrt_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn approximate_recip_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn add_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn sub_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn mul_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn div_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn copysign_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn reduce_max_f32x4(self, a: f32x4<Self>) -> f32;
fn reduce_min_f32x4(self, a: f32x4<Self>) -> f32;
fn reduce_max_precise_f32x4(self, a: f32x4<Self>) -> f32;
fn reduce_min_precise_f32x4(self, a: f32x4<Self>) -> f32;
fn reduce_sum_f32x4(self, a: f32x4<Self>) -> f32;
fn reduce_product_f32x4(self, a: f32x4<Self>) -> f32;
fn max_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn min_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn max_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn min_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn clamp_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>;
fn simd_eq_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>;
fn simd_lt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>;
fn simd_le_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>;
fn zip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn zip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn unzip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn unzip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
fn interleave_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> (f32x4<Self>, f32x4<Self>);
fn deinterleave_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> (f32x4<Self>, f32x4<Self>);
fn mul_add_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>;
fn mul_add_precise_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>;
fn mul_sub_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>;
fn mul_sub_precise_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>;
fn floor_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn ceil_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn round_ties_even_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn round_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn fract_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn trunc_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn to_degrees_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn to_radians_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
fn is_nan_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn is_infinite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn is_finite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn is_subnormal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn is_normal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn is_sign_positive_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn is_sign_negative_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
fn select_f32x4(
self,
a: mask32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>;
fn combine_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x8<Self>;
fn load_four_interleaved_f32x4(self, src: &[f32; 16]) -> [f32x4<Self>; 4];
fn store_four_interleaved_f32x4(
self,
vectors: [f32x4<Self>; 4],
dest: &mut [f32; 16],
);
fn widen_f32x4(self, a: f32x4<Self>) -> (f64x2<Self>, f64x2<Self>);
fn cvt_u32_f32x4(self, a: f32x4<Self>) -> u32x4<Self>;
fn cvt_u32_precise_f32x4(self, a: f32x4<Self>) -> u32x4<Self>;
fn cvt_i32_f32x4(self, a: f32x4<Self>) -> i32x4<Self>;
fn cvt_i32_precise_f32x4(self, a: f32x4<Self>) -> i32x4<Self>;
fn abs_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
fn splat_i8x16(self, val: i8) -> i8x16<Self>;
fn reverse_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
fn slide_i8x16<const SHIFT: usize>(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> i8x16<Self>;
fn compress_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
) -> i8x16<Self>;
fn compress_merge_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
merge: i8x16<Self>,
) -> i8x16<Self>;
fn expand_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
) -> i8x16<Self>;
fn expand_merge_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
merge: i8x16<Self>,
) -> i8x16<Self>;
fn count_ones_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
fn count_zeros_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
fn add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn saturating_add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn saturating_sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn mul_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn and_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn or_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn xor_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn not_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
fn shl_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>;
fn shlv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn shr_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>;
fn shrv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn reduce_max_i8x16(self, a: i8x16<Self>) -> i8;
fn reduce_min_i8x16(self, a: i8x16<Self>) -> i8;
fn reduce_sum_i8x16(self, a: i8x16<Self>) -> i8;
fn reduce_product_i8x16(self, a: i8x16<Self>) -> i8;
fn max_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn min_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn clamp_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
c: i8x16<Self>,
) -> i8x16<Self>;
fn simd_eq_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>;
fn simd_lt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>;
fn simd_le_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>;
fn zip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn zip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn unzip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn unzip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
fn interleave_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i8x16<Self>, i8x16<Self>);
fn deinterleave_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i8x16<Self>, i8x16<Self>);
fn select_i8x16(
self,
a: mask8x16<Self>,
b: i8x16<Self>,
c: i8x16<Self>,
) -> i8x16<Self>;
fn combine_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x32<Self>;
fn neg_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
fn load_four_interleaved_i8x16(self, src: &[i8; 64]) -> [i8x16<Self>; 4];
fn store_four_interleaved_i8x16(
self,
vectors: [i8x16<Self>; 4],
dest: &mut [i8; 64],
);
fn widen_i8x16(self, a: i8x16<Self>) -> (i16x8<Self>, i16x8<Self>);
fn widening_mul_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i16x8<Self>, i16x8<Self>);
fn widening_add_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i16x8<Self>, i16x8<Self>);
fn pairwise_widening_add_i8x16(self, a: i8x16<Self>) -> i16x8<Self>;
fn pairwise_dot_product_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> i16x8<Self>;
fn splat_u8x16(self, val: u8) -> u8x16<Self>;
fn reverse_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
fn slide_u8x16<const SHIFT: usize>(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> u8x16<Self>;
fn swizzle_dyn_within_blocks_u8x16(
self,
a: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>;
fn swizzle_dyn_u8x16(
self,
a: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>;
fn swizzle_dyn_precise_u8x16(
self,
a: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>;
fn concat_swizzle_dyn_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>;
fn concat_swizzle_dyn_precise_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>;
fn compress_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
) -> u8x16<Self>;
fn compress_merge_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
merge: u8x16<Self>,
) -> u8x16<Self>;
fn expand_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
) -> u8x16<Self>;
fn expand_merge_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
merge: u8x16<Self>,
) -> u8x16<Self>;
fn count_ones_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
fn count_zeros_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
fn add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn saturating_add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn saturating_sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn mul_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn and_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn or_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn xor_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn not_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
fn shl_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>;
fn shlv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn shr_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>;
fn shrv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn reduce_max_u8x16(self, a: u8x16<Self>) -> u8;
fn reduce_min_u8x16(self, a: u8x16<Self>) -> u8;
fn reduce_sum_u8x16(self, a: u8x16<Self>) -> u8;
fn reduce_product_u8x16(self, a: u8x16<Self>) -> u8;
fn max_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn min_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn clamp_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
c: u8x16<Self>,
) -> u8x16<Self>;
fn simd_eq_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>;
fn simd_lt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>;
fn simd_le_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>;
fn zip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn zip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn unzip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn unzip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
fn interleave_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u8x16<Self>, u8x16<Self>);
fn deinterleave_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u8x16<Self>, u8x16<Self>);
fn select_u8x16(
self,
a: mask8x16<Self>,
b: u8x16<Self>,
c: u8x16<Self>,
) -> u8x16<Self>;
fn combine_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x32<Self>;
fn load_four_interleaved_u8x16(self, src: &[u8; 64]) -> [u8x16<Self>; 4];
fn store_four_interleaved_u8x16(
self,
vectors: [u8x16<Self>; 4],
dest: &mut [u8; 64],
);
fn widen_u8x16(self, a: u8x16<Self>) -> (u16x8<Self>, u16x8<Self>);
fn widening_mul_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u16x8<Self>, u16x8<Self>);
fn widening_add_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u16x8<Self>, u16x8<Self>);
fn pairwise_widening_add_u8x16(self, a: u8x16<Self>) -> u16x8<Self>;
fn pairwise_dot_product_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> u16x8<Self>;
fn splat_mask8x16(self, val: bool) -> mask8x16<Self>;
fn from_bitmask_mask8x16(self, bits: u64) -> mask8x16<Self>;
fn to_bitmask_mask8x16(self, a: mask8x16<Self>) -> u64;
fn from_vector_mask8x16(self, vector: i8x16<Self>) -> mask8x16<Self>;
fn to_vector_mask8x16(self, a: mask8x16<Self>) -> i8x16<Self>;
fn set_mask8x16(self, a: &mut mask8x16<Self>, index: usize, value: bool);
fn rotate_elements_left_mask8x16<const OFFSET: usize>(
self,
a: mask8x16<Self>,
) -> mask8x16<Self>;
fn rotate_elements_right_mask8x16<const OFFSET: usize>(
self,
a: mask8x16<Self>,
) -> mask8x16<Self>;
fn and_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x16<Self>;
fn or_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>;
fn xor_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x16<Self>;
fn not_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>;
fn reverse_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>;
fn select_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
c: mask8x16<Self>,
) -> mask8x16<Self>;
fn simd_eq_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x16<Self>;
fn any_true_mask8x16(self, a: mask8x16<Self>) -> bool;
fn all_true_mask8x16(self, a: mask8x16<Self>) -> bool;
fn any_false_mask8x16(self, a: mask8x16<Self>) -> bool;
fn all_false_mask8x16(self, a: mask8x16<Self>) -> bool;
fn combine_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x32<Self>;
fn widen_mask8x16(
self,
a: mask8x16<Self>,
) -> (mask16x8<Self>, mask16x8<Self>);
fn abs_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
fn splat_i16x8(self, val: i16) -> i16x8<Self>;
fn reverse_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
fn slide_i16x8<const SHIFT: usize>(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i16x8<Self>;
fn compress_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
) -> i16x8<Self>;
fn compress_merge_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
merge: i16x8<Self>,
) -> i16x8<Self>;
fn expand_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
) -> i16x8<Self>;
fn expand_merge_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
merge: i16x8<Self>,
) -> i16x8<Self>;
fn count_ones_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
fn count_zeros_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
fn add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn saturating_add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn saturating_sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn mul_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn and_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn or_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn xor_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn not_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
fn shl_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>;
fn shlv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn shr_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>;
fn shrv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn reduce_max_i16x8(self, a: i16x8<Self>) -> i16;
fn reduce_min_i16x8(self, a: i16x8<Self>) -> i16;
fn reduce_sum_i16x8(self, a: i16x8<Self>) -> i16;
fn reduce_product_i16x8(self, a: i16x8<Self>) -> i16;
fn max_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn min_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn clamp_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
c: i16x8<Self>,
) -> i16x8<Self>;
fn simd_eq_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>;
fn simd_lt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>;
fn simd_le_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>;
fn zip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn zip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn unzip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn unzip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
fn interleave_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i16x8<Self>, i16x8<Self>);
fn deinterleave_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i16x8<Self>, i16x8<Self>);
fn select_i16x8(
self,
a: mask16x8<Self>,
b: i16x8<Self>,
c: i16x8<Self>,
) -> i16x8<Self>;
fn combine_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x16<Self>;
fn neg_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
fn load_four_interleaved_i16x8(self, src: &[i16; 32]) -> [i16x8<Self>; 4];
fn store_four_interleaved_i16x8(
self,
vectors: [i16x8<Self>; 4],
dest: &mut [i16; 32],
);
fn widen_i16x8(self, a: i16x8<Self>) -> (i32x4<Self>, i32x4<Self>);
fn widening_mul_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i32x4<Self>, i32x4<Self>);
fn widening_add_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i32x4<Self>, i32x4<Self>);
fn pairwise_widening_add_i16x8(self, a: i16x8<Self>) -> i32x4<Self>;
fn pairwise_dot_product_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i32x4<Self>;
fn narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>;
fn saturating_narrow_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i8x16<Self>;
fn relaxed_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>;
fn splat_u16x8(self, val: u16) -> u16x8<Self>;
fn reverse_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
fn slide_u16x8<const SHIFT: usize>(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u16x8<Self>;
fn compress_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
) -> u16x8<Self>;
fn compress_merge_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
merge: u16x8<Self>,
) -> u16x8<Self>;
fn expand_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
) -> u16x8<Self>;
fn expand_merge_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
merge: u16x8<Self>,
) -> u16x8<Self>;
fn count_ones_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
fn count_zeros_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
fn add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn saturating_add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn saturating_sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn mul_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn and_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn or_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn xor_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn not_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
fn shl_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>;
fn shlv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn shr_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>;
fn shrv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn reduce_max_u16x8(self, a: u16x8<Self>) -> u16;
fn reduce_min_u16x8(self, a: u16x8<Self>) -> u16;
fn reduce_sum_u16x8(self, a: u16x8<Self>) -> u16;
fn reduce_product_u16x8(self, a: u16x8<Self>) -> u16;
fn max_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn min_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn clamp_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
c: u16x8<Self>,
) -> u16x8<Self>;
fn simd_eq_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>;
fn simd_lt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>;
fn simd_le_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>;
fn zip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn zip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn unzip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn unzip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
fn interleave_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u16x8<Self>, u16x8<Self>);
fn deinterleave_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u16x8<Self>, u16x8<Self>);
fn select_u16x8(
self,
a: mask16x8<Self>,
b: u16x8<Self>,
c: u16x8<Self>,
) -> u16x8<Self>;
fn combine_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x16<Self>;
fn load_four_interleaved_u16x8(self, src: &[u16; 32]) -> [u16x8<Self>; 4];
fn store_four_interleaved_u16x8(
self,
vectors: [u16x8<Self>; 4],
dest: &mut [u16; 32],
);
fn widen_u16x8(self, a: u16x8<Self>) -> (u32x4<Self>, u32x4<Self>);
fn widening_mul_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u32x4<Self>, u32x4<Self>);
fn widening_add_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u32x4<Self>, u32x4<Self>);
fn pairwise_widening_add_u16x8(self, a: u16x8<Self>) -> u32x4<Self>;
fn pairwise_dot_product_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u32x4<Self>;
fn narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>;
fn saturating_narrow_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u8x16<Self>;
fn relaxed_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>;
fn splat_mask16x8(self, val: bool) -> mask16x8<Self>;
fn from_bitmask_mask16x8(self, bits: u64) -> mask16x8<Self>;
fn to_bitmask_mask16x8(self, a: mask16x8<Self>) -> u64;
fn from_vector_mask16x8(self, vector: i16x8<Self>) -> mask16x8<Self>;
fn to_vector_mask16x8(self, a: mask16x8<Self>) -> i16x8<Self>;
fn set_mask16x8(self, a: &mut mask16x8<Self>, index: usize, value: bool);
fn rotate_elements_left_mask16x8<const OFFSET: usize>(
self,
a: mask16x8<Self>,
) -> mask16x8<Self>;
fn rotate_elements_right_mask16x8<const OFFSET: usize>(
self,
a: mask16x8<Self>,
) -> mask16x8<Self>;
fn and_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x8<Self>;
fn or_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>;
fn xor_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x8<Self>;
fn not_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>;
fn reverse_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>;
fn select_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
c: mask16x8<Self>,
) -> mask16x8<Self>;
fn simd_eq_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x8<Self>;
fn any_true_mask16x8(self, a: mask16x8<Self>) -> bool;
fn all_true_mask16x8(self, a: mask16x8<Self>) -> bool;
fn any_false_mask16x8(self, a: mask16x8<Self>) -> bool;
fn all_false_mask16x8(self, a: mask16x8<Self>) -> bool;
fn combine_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x16<Self>;
fn widen_mask16x8(
self,
a: mask16x8<Self>,
) -> (mask32x4<Self>, mask32x4<Self>);
fn narrow_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask8x16<Self>;
fn abs_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
fn splat_i32x4(self, val: i32) -> i32x4<Self>;
fn reverse_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
fn slide_i32x4<const SHIFT: usize>(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i32x4<Self>;
fn compress_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
) -> i32x4<Self>;
fn compress_merge_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
merge: i32x4<Self>,
) -> i32x4<Self>;
fn expand_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
) -> i32x4<Self>;
fn expand_merge_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
merge: i32x4<Self>,
) -> i32x4<Self>;
fn count_ones_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
fn count_zeros_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
fn add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn saturating_add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn saturating_sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn mul_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn and_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn or_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn xor_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn not_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
fn shl_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>;
fn shlv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn shr_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>;
fn shrv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn reduce_max_i32x4(self, a: i32x4<Self>) -> i32;
fn reduce_min_i32x4(self, a: i32x4<Self>) -> i32;
fn reduce_sum_i32x4(self, a: i32x4<Self>) -> i32;
fn reduce_product_i32x4(self, a: i32x4<Self>) -> i32;
fn max_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn min_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn clamp_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
c: i32x4<Self>,
) -> i32x4<Self>;
fn simd_eq_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>;
fn simd_lt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>;
fn simd_le_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>;
fn zip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn zip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn unzip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn unzip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
fn interleave_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i32x4<Self>, i32x4<Self>);
fn deinterleave_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i32x4<Self>, i32x4<Self>);
fn select_i32x4(
self,
a: mask32x4<Self>,
b: i32x4<Self>,
c: i32x4<Self>,
) -> i32x4<Self>;
fn combine_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x8<Self>;
fn neg_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
fn load_four_interleaved_i32x4(self, src: &[i32; 16]) -> [i32x4<Self>; 4];
fn store_four_interleaved_i32x4(
self,
vectors: [i32x4<Self>; 4],
dest: &mut [i32; 16],
);
fn widen_i32x4(self, a: i32x4<Self>) -> (i64x2<Self>, i64x2<Self>);
fn widening_mul_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i64x2<Self>, i64x2<Self>);
fn widening_add_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i64x2<Self>, i64x2<Self>);
fn pairwise_widening_add_i32x4(self, a: i32x4<Self>) -> i64x2<Self>;
fn pairwise_dot_product_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i64x2<Self>;
fn narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>;
fn saturating_narrow_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i16x8<Self>;
fn relaxed_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>;
fn cvt_f32_i32x4(self, a: i32x4<Self>) -> f32x4<Self>;
fn splat_u32x4(self, val: u32) -> u32x4<Self>;
fn reverse_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
fn slide_u32x4<const SHIFT: usize>(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u32x4<Self>;
fn compress_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
) -> u32x4<Self>;
fn compress_merge_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
merge: u32x4<Self>,
) -> u32x4<Self>;
fn expand_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
) -> u32x4<Self>;
fn expand_merge_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
merge: u32x4<Self>,
) -> u32x4<Self>;
fn count_ones_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
fn count_zeros_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
fn add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn saturating_add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn saturating_sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn mul_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn and_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn or_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn xor_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn not_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
fn shl_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>;
fn shlv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn shr_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>;
fn shrv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn reduce_max_u32x4(self, a: u32x4<Self>) -> u32;
fn reduce_min_u32x4(self, a: u32x4<Self>) -> u32;
fn reduce_sum_u32x4(self, a: u32x4<Self>) -> u32;
fn reduce_product_u32x4(self, a: u32x4<Self>) -> u32;
fn max_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn min_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn clamp_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
c: u32x4<Self>,
) -> u32x4<Self>;
fn simd_eq_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>;
fn simd_lt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>;
fn simd_le_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>;
fn zip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn zip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn unzip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn unzip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
fn interleave_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u32x4<Self>, u32x4<Self>);
fn deinterleave_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u32x4<Self>, u32x4<Self>);
fn select_u32x4(
self,
a: mask32x4<Self>,
b: u32x4<Self>,
c: u32x4<Self>,
) -> u32x4<Self>;
fn combine_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x8<Self>;
fn load_four_interleaved_u32x4(self, src: &[u32; 16]) -> [u32x4<Self>; 4];
fn store_four_interleaved_u32x4(
self,
vectors: [u32x4<Self>; 4],
dest: &mut [u32; 16],
);
fn widen_u32x4(self, a: u32x4<Self>) -> (u64x2<Self>, u64x2<Self>);
fn widening_mul_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u64x2<Self>, u64x2<Self>);
fn widening_add_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u64x2<Self>, u64x2<Self>);
fn pairwise_widening_add_u32x4(self, a: u32x4<Self>) -> u64x2<Self>;
fn pairwise_dot_product_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u64x2<Self>;
fn narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>;
fn saturating_narrow_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u16x8<Self>;
fn relaxed_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>;
fn cvt_f32_u32x4(self, a: u32x4<Self>) -> f32x4<Self>;
fn splat_mask32x4(self, val: bool) -> mask32x4<Self>;
fn from_bitmask_mask32x4(self, bits: u64) -> mask32x4<Self>;
fn to_bitmask_mask32x4(self, a: mask32x4<Self>) -> u64;
fn from_vector_mask32x4(self, vector: i32x4<Self>) -> mask32x4<Self>;
fn to_vector_mask32x4(self, a: mask32x4<Self>) -> i32x4<Self>;
fn set_mask32x4(self, a: &mut mask32x4<Self>, index: usize, value: bool);
fn rotate_elements_left_mask32x4<const OFFSET: usize>(
self,
a: mask32x4<Self>,
) -> mask32x4<Self>;
fn rotate_elements_right_mask32x4<const OFFSET: usize>(
self,
a: mask32x4<Self>,
) -> mask32x4<Self>;
fn and_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x4<Self>;
fn or_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>;
fn xor_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x4<Self>;
fn not_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>;
fn reverse_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>;
fn select_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
c: mask32x4<Self>,
) -> mask32x4<Self>;
fn simd_eq_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x4<Self>;
fn any_true_mask32x4(self, a: mask32x4<Self>) -> bool;
fn all_true_mask32x4(self, a: mask32x4<Self>) -> bool;
fn any_false_mask32x4(self, a: mask32x4<Self>) -> bool;
fn all_false_mask32x4(self, a: mask32x4<Self>) -> bool;
fn combine_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x8<Self>;
fn widen_mask32x4(
self,
a: mask32x4<Self>,
) -> (mask64x2<Self>, mask64x2<Self>);
fn narrow_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask16x8<Self>;
fn abs_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn splat_f64x2(self, val: f64) -> f64x2<Self>;
fn reverse_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn slide_f64x2<const SHIFT: usize>(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> f64x2<Self>;
fn compress_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
) -> f64x2<Self>;
fn compress_merge_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
merge: f64x2<Self>,
) -> f64x2<Self>;
fn expand_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
) -> f64x2<Self>;
fn expand_merge_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
merge: f64x2<Self>,
) -> f64x2<Self>;
fn neg_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn sqrt_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn approximate_recip_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn add_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn sub_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn mul_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn div_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn copysign_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn reduce_max_f64x2(self, a: f64x2<Self>) -> f64;
fn reduce_min_f64x2(self, a: f64x2<Self>) -> f64;
fn reduce_max_precise_f64x2(self, a: f64x2<Self>) -> f64;
fn reduce_min_precise_f64x2(self, a: f64x2<Self>) -> f64;
fn reduce_sum_f64x2(self, a: f64x2<Self>) -> f64;
fn reduce_product_f64x2(self, a: f64x2<Self>) -> f64;
fn max_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn min_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn max_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn min_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn clamp_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>;
fn simd_eq_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>;
fn simd_lt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>;
fn simd_le_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>;
fn zip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn zip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn unzip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn unzip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
fn interleave_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> (f64x2<Self>, f64x2<Self>);
fn deinterleave_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> (f64x2<Self>, f64x2<Self>);
fn mul_add_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>;
fn mul_add_precise_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>;
fn mul_sub_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>;
fn mul_sub_precise_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>;
fn floor_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn ceil_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn round_ties_even_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn round_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn fract_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn trunc_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn to_degrees_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn to_radians_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
fn is_nan_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn is_infinite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn is_finite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn is_subnormal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn is_normal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn is_sign_positive_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn is_sign_negative_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
fn select_f64x2(
self,
a: mask64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>;
fn combine_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x4<Self>;
fn load_four_interleaved_f64x2(self, src: &[f64; 8]) -> [f64x2<Self>; 4];
fn store_four_interleaved_f64x2(
self,
vectors: [f64x2<Self>; 4],
dest: &mut [f64; 8],
);
fn narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>;
fn saturating_narrow_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> f32x4<Self>;
fn relaxed_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>;
fn cvt_u64_f64x2(self, a: f64x2<Self>) -> u64x2<Self>;
fn cvt_u64_precise_f64x2(self, a: f64x2<Self>) -> u64x2<Self>;
fn cvt_i64_f64x2(self, a: f64x2<Self>) -> i64x2<Self>;
fn cvt_i64_precise_f64x2(self, a: f64x2<Self>) -> i64x2<Self>;
fn abs_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
fn splat_i64x2(self, val: i64) -> i64x2<Self>;
fn reverse_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
fn slide_i64x2<const SHIFT: usize>(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> i64x2<Self>;
fn compress_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
) -> i64x2<Self>;
fn compress_merge_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
merge: i64x2<Self>,
) -> i64x2<Self>;
fn expand_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
) -> i64x2<Self>;
fn expand_merge_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
merge: i64x2<Self>,
) -> i64x2<Self>;
fn count_ones_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
fn count_zeros_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
fn add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn saturating_add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn saturating_sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn mul_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn and_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn or_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn xor_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn not_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
fn shl_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>;
fn shlv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn shr_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>;
fn shrv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn reduce_max_i64x2(self, a: i64x2<Self>) -> i64;
fn reduce_min_i64x2(self, a: i64x2<Self>) -> i64;
fn reduce_sum_i64x2(self, a: i64x2<Self>) -> i64;
fn reduce_product_i64x2(self, a: i64x2<Self>) -> i64;
fn max_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn min_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn clamp_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
c: i64x2<Self>,
) -> i64x2<Self>;
fn simd_eq_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>;
fn simd_lt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>;
fn simd_le_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>;
fn zip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn zip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn unzip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn unzip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
fn interleave_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> (i64x2<Self>, i64x2<Self>);
fn deinterleave_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> (i64x2<Self>, i64x2<Self>);
fn select_i64x2(
self,
a: mask64x2<Self>,
b: i64x2<Self>,
c: i64x2<Self>,
) -> i64x2<Self>;
fn combine_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x4<Self>;
fn neg_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
fn load_four_interleaved_i64x2(self, src: &[i64; 8]) -> [i64x2<Self>; 4];
fn store_four_interleaved_i64x2(
self,
vectors: [i64x2<Self>; 4],
dest: &mut [i64; 8],
);
fn narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>;
fn saturating_narrow_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> i32x4<Self>;
fn relaxed_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>;
fn cvt_f64_i64x2(self, a: i64x2<Self>) -> f64x2<Self>;
fn splat_u64x2(self, val: u64) -> u64x2<Self>;
fn reverse_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
fn slide_u64x2<const SHIFT: usize>(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> u64x2<Self>;
fn compress_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
) -> u64x2<Self>;
fn compress_merge_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
merge: u64x2<Self>,
) -> u64x2<Self>;
fn expand_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
) -> u64x2<Self>;
fn expand_merge_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
merge: u64x2<Self>,
) -> u64x2<Self>;
fn count_ones_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
fn count_zeros_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
fn add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn saturating_add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn saturating_sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn mul_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn and_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn or_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn xor_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn not_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
fn shl_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>;
fn shlv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn shr_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>;
fn shrv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn reduce_max_u64x2(self, a: u64x2<Self>) -> u64;
fn reduce_min_u64x2(self, a: u64x2<Self>) -> u64;
fn reduce_sum_u64x2(self, a: u64x2<Self>) -> u64;
fn reduce_product_u64x2(self, a: u64x2<Self>) -> u64;
fn max_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn min_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn clamp_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
c: u64x2<Self>,
) -> u64x2<Self>;
fn simd_eq_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>;
fn simd_lt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>;
fn simd_le_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>;
fn zip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn zip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn unzip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn unzip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
fn interleave_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> (u64x2<Self>, u64x2<Self>);
fn deinterleave_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> (u64x2<Self>, u64x2<Self>);
fn select_u64x2(
self,
a: mask64x2<Self>,
b: u64x2<Self>,
c: u64x2<Self>,
) -> u64x2<Self>;
fn combine_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x4<Self>;
fn load_four_interleaved_u64x2(self, src: &[u64; 8]) -> [u64x2<Self>; 4];
fn store_four_interleaved_u64x2(
self,
vectors: [u64x2<Self>; 4],
dest: &mut [u64; 8],
);
fn narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>;
fn saturating_narrow_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> u32x4<Self>;
fn relaxed_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>;
fn cvt_f64_u64x2(self, a: u64x2<Self>) -> f64x2<Self>;
fn splat_mask64x2(self, val: bool) -> mask64x2<Self>;
fn from_bitmask_mask64x2(self, bits: u64) -> mask64x2<Self>;
fn to_bitmask_mask64x2(self, a: mask64x2<Self>) -> u64;
fn from_vector_mask64x2(self, vector: i64x2<Self>) -> mask64x2<Self>;
fn to_vector_mask64x2(self, a: mask64x2<Self>) -> i64x2<Self>;
fn set_mask64x2(self, a: &mut mask64x2<Self>, index: usize, value: bool);
fn rotate_elements_left_mask64x2<const OFFSET: usize>(
self,
a: mask64x2<Self>,
) -> mask64x2<Self>;
fn rotate_elements_right_mask64x2<const OFFSET: usize>(
self,
a: mask64x2<Self>,
) -> mask64x2<Self>;
fn and_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x2<Self>;
fn or_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>;
fn xor_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x2<Self>;
fn not_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>;
fn reverse_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>;
fn select_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
c: mask64x2<Self>,
) -> mask64x2<Self>;
fn simd_eq_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x2<Self>;
fn any_true_mask64x2(self, a: mask64x2<Self>) -> bool;
fn all_true_mask64x2(self, a: mask64x2<Self>) -> bool;
fn any_false_mask64x2(self, a: mask64x2<Self>) -> bool;
fn all_false_mask64x2(self, a: mask64x2<Self>) -> bool;
fn combine_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x4<Self>;
fn narrow_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask32x4<Self>;
fn slide_f32x8<const SHIFT: usize>(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> f32x8<Self>;
fn compress_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
) -> f32x8<Self>;
fn compress_merge_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
merge: f32x8<Self>,
) -> f32x8<Self>;
fn expand_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
) -> f32x8<Self>;
fn expand_merge_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
merge: f32x8<Self>,
) -> f32x8<Self>;
fn is_nan_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn is_infinite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn is_finite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn is_subnormal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn is_normal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn is_sign_positive_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn is_sign_negative_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
fn combine_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x16<Self>;
fn split_f32x8(self, a: f32x8<Self>) -> (f32x4<Self>, f32x4<Self>);
fn slide_i8x32<const SHIFT: usize>(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> i8x32<Self>;
fn compress_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
) -> i8x32<Self>;
fn compress_merge_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
merge: i8x32<Self>,
) -> i8x32<Self>;
fn expand_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
) -> i8x32<Self>;
fn expand_merge_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
merge: i8x32<Self>,
) -> i8x32<Self>;
fn combine_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x64<Self>;
fn split_i8x32(self, a: i8x32<Self>) -> (i8x16<Self>, i8x16<Self>);
fn slide_u8x32<const SHIFT: usize>(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> u8x32<Self>;
fn swizzle_dyn_u8x32(
self,
a: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>;
fn swizzle_dyn_precise_u8x32(
self,
a: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>;
fn concat_swizzle_dyn_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>;
fn concat_swizzle_dyn_precise_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>;
fn compress_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
) -> u8x32<Self>;
fn compress_merge_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
merge: u8x32<Self>,
) -> u8x32<Self>;
fn expand_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
) -> u8x32<Self>;
fn expand_merge_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
merge: u8x32<Self>,
) -> u8x32<Self>;
fn combine_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x64<Self>;
fn split_u8x32(self, a: u8x32<Self>) -> (u8x16<Self>, u8x16<Self>);
fn from_vector_mask8x32(self, vector: i8x32<Self>) -> mask8x32<Self>;
fn to_vector_mask8x32(self, a: mask8x32<Self>) -> i8x32<Self>;
fn set_mask8x32(self, a: &mut mask8x32<Self>, index: usize, value: bool);
fn rotate_elements_left_mask8x32<const OFFSET: usize>(
self,
a: mask8x32<Self>,
) -> mask8x32<Self>;
fn rotate_elements_right_mask8x32<const OFFSET: usize>(
self,
a: mask8x32<Self>,
) -> mask8x32<Self>;
fn combine_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x64<Self>;
fn split_mask8x32(
self,
a: mask8x32<Self>,
) -> (mask8x16<Self>, mask8x16<Self>);
fn slide_i16x16<const SHIFT: usize>(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i16x16<Self>;
fn compress_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
) -> i16x16<Self>;
fn compress_merge_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
merge: i16x16<Self>,
) -> i16x16<Self>;
fn expand_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
) -> i16x16<Self>;
fn expand_merge_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
merge: i16x16<Self>,
) -> i16x16<Self>;
fn combine_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x32<Self>;
fn split_i16x16(self, a: i16x16<Self>) -> (i16x8<Self>, i16x8<Self>);
fn slide_u16x16<const SHIFT: usize>(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u16x16<Self>;
fn compress_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
) -> u16x16<Self>;
fn compress_merge_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
merge: u16x16<Self>,
) -> u16x16<Self>;
fn expand_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
) -> u16x16<Self>;
fn expand_merge_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
merge: u16x16<Self>,
) -> u16x16<Self>;
fn combine_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x32<Self>;
fn split_u16x16(self, a: u16x16<Self>) -> (u16x8<Self>, u16x8<Self>);
fn from_vector_mask16x16(self, vector: i16x16<Self>) -> mask16x16<Self>;
fn to_vector_mask16x16(self, a: mask16x16<Self>) -> i16x16<Self>;
fn set_mask16x16(self, a: &mut mask16x16<Self>, index: usize, value: bool);
fn rotate_elements_left_mask16x16<const OFFSET: usize>(
self,
a: mask16x16<Self>,
) -> mask16x16<Self>;
fn rotate_elements_right_mask16x16<const OFFSET: usize>(
self,
a: mask16x16<Self>,
) -> mask16x16<Self>;
fn combine_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x32<Self>;
fn split_mask16x16(
self,
a: mask16x16<Self>,
) -> (mask16x8<Self>, mask16x8<Self>);
fn slide_i32x8<const SHIFT: usize>(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i32x8<Self>;
fn compress_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
) -> i32x8<Self>;
fn compress_merge_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
merge: i32x8<Self>,
) -> i32x8<Self>;
fn expand_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
) -> i32x8<Self>;
fn expand_merge_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
merge: i32x8<Self>,
) -> i32x8<Self>;
fn combine_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x16<Self>;
fn split_i32x8(self, a: i32x8<Self>) -> (i32x4<Self>, i32x4<Self>);
fn slide_u32x8<const SHIFT: usize>(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u32x8<Self>;
fn compress_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
) -> u32x8<Self>;
fn compress_merge_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
merge: u32x8<Self>,
) -> u32x8<Self>;
fn expand_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
) -> u32x8<Self>;
fn expand_merge_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
merge: u32x8<Self>,
) -> u32x8<Self>;
fn combine_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x16<Self>;
fn split_u32x8(self, a: u32x8<Self>) -> (u32x4<Self>, u32x4<Self>);
fn from_vector_mask32x8(self, vector: i32x8<Self>) -> mask32x8<Self>;
fn to_vector_mask32x8(self, a: mask32x8<Self>) -> i32x8<Self>;
fn set_mask32x8(self, a: &mut mask32x8<Self>, index: usize, value: bool);
fn rotate_elements_left_mask32x8<const OFFSET: usize>(
self,
a: mask32x8<Self>,
) -> mask32x8<Self>;
fn rotate_elements_right_mask32x8<const OFFSET: usize>(
self,
a: mask32x8<Self>,
) -> mask32x8<Self>;
fn combine_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x16<Self>;
fn split_mask32x8(
self,
a: mask32x8<Self>,
) -> (mask32x4<Self>, mask32x4<Self>);
fn slide_f64x4<const SHIFT: usize>(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> f64x4<Self>;
fn compress_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
) -> f64x4<Self>;
fn compress_merge_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
merge: f64x4<Self>,
) -> f64x4<Self>;
fn expand_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
) -> f64x4<Self>;
fn expand_merge_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
merge: f64x4<Self>,
) -> f64x4<Self>;
fn is_nan_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn is_infinite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn is_finite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn is_subnormal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn is_normal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn is_sign_positive_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn is_sign_negative_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
fn combine_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x8<Self>;
fn split_f64x4(self, a: f64x4<Self>) -> (f64x2<Self>, f64x2<Self>);
fn slide_i64x4<const SHIFT: usize>(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> i64x4<Self>;
fn compress_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
) -> i64x4<Self>;
fn compress_merge_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
merge: i64x4<Self>,
) -> i64x4<Self>;
fn expand_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
) -> i64x4<Self>;
fn expand_merge_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
merge: i64x4<Self>,
) -> i64x4<Self>;
fn combine_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x8<Self>;
fn split_i64x4(self, a: i64x4<Self>) -> (i64x2<Self>, i64x2<Self>);
fn slide_u64x4<const SHIFT: usize>(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> u64x4<Self>;
fn compress_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
) -> u64x4<Self>;
fn compress_merge_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
merge: u64x4<Self>,
) -> u64x4<Self>;
fn expand_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
) -> u64x4<Self>;
fn expand_merge_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
merge: u64x4<Self>,
) -> u64x4<Self>;
fn combine_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x8<Self>;
fn split_u64x4(self, a: u64x4<Self>) -> (u64x2<Self>, u64x2<Self>);
fn from_vector_mask64x4(self, vector: i64x4<Self>) -> mask64x4<Self>;
fn to_vector_mask64x4(self, a: mask64x4<Self>) -> i64x4<Self>;
fn set_mask64x4(self, a: &mut mask64x4<Self>, index: usize, value: bool);
fn rotate_elements_left_mask64x4<const OFFSET: usize>(
self,
a: mask64x4<Self>,
) -> mask64x4<Self>;
fn rotate_elements_right_mask64x4<const OFFSET: usize>(
self,
a: mask64x4<Self>,
) -> mask64x4<Self>;
fn combine_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x8<Self>;
fn split_mask64x4(
self,
a: mask64x4<Self>,
) -> (mask64x2<Self>, mask64x2<Self>);
fn slide_f32x16<const SHIFT: usize>(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> f32x16<Self>;
fn compress_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
) -> f32x16<Self>;
fn compress_merge_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
merge: f32x16<Self>,
) -> f32x16<Self>;
fn expand_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
) -> f32x16<Self>;
fn expand_merge_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
merge: f32x16<Self>,
) -> f32x16<Self>;
fn is_nan_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn is_infinite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn is_finite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn is_subnormal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn is_normal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn is_sign_positive_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn is_sign_negative_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
fn split_f32x16(self, a: f32x16<Self>) -> (f32x8<Self>, f32x8<Self>);
fn slide_i8x64<const SHIFT: usize>(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> i8x64<Self>;
fn compress_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
) -> i8x64<Self>;
fn compress_merge_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
merge: i8x64<Self>,
) -> i8x64<Self>;
fn expand_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
) -> i8x64<Self>;
fn expand_merge_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
merge: i8x64<Self>,
) -> i8x64<Self>;
fn split_i8x64(self, a: i8x64<Self>) -> (i8x32<Self>, i8x32<Self>);
fn slide_u8x64<const SHIFT: usize>(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> u8x64<Self>;
fn swizzle_dyn_u8x64(
self,
a: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>;
fn swizzle_dyn_precise_u8x64(
self,
a: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>;
fn concat_swizzle_dyn_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>;
fn concat_swizzle_dyn_precise_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>;
fn compress_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
) -> u8x64<Self>;
fn compress_merge_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
merge: u8x64<Self>,
) -> u8x64<Self>;
fn expand_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
) -> u8x64<Self>;
fn expand_merge_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
merge: u8x64<Self>,
) -> u8x64<Self>;
fn split_u8x64(self, a: u8x64<Self>) -> (u8x32<Self>, u8x32<Self>);
fn from_vector_mask8x64(self, vector: i8x64<Self>) -> mask8x64<Self>;
fn to_vector_mask8x64(self, a: mask8x64<Self>) -> i8x64<Self>;
fn set_mask8x64(self, a: &mut mask8x64<Self>, index: usize, value: bool);
fn rotate_elements_left_mask8x64<const OFFSET: usize>(
self,
a: mask8x64<Self>,
) -> mask8x64<Self>;
fn rotate_elements_right_mask8x64<const OFFSET: usize>(
self,
a: mask8x64<Self>,
) -> mask8x64<Self>;
fn split_mask8x64(
self,
a: mask8x64<Self>,
) -> (mask8x32<Self>, mask8x32<Self>);
fn slide_i16x32<const SHIFT: usize>(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i16x32<Self>;
fn compress_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
) -> i16x32<Self>;
fn compress_merge_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
merge: i16x32<Self>,
) -> i16x32<Self>;
fn expand_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
) -> i16x32<Self>;
fn expand_merge_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
merge: i16x32<Self>,
) -> i16x32<Self>;
fn split_i16x32(self, a: i16x32<Self>) -> (i16x16<Self>, i16x16<Self>);
fn slide_u16x32<const SHIFT: usize>(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u16x32<Self>;
fn compress_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
) -> u16x32<Self>;
fn compress_merge_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
merge: u16x32<Self>,
) -> u16x32<Self>;
fn expand_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
) -> u16x32<Self>;
fn expand_merge_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
merge: u16x32<Self>,
) -> u16x32<Self>;
fn split_u16x32(self, a: u16x32<Self>) -> (u16x16<Self>, u16x16<Self>);
fn from_vector_mask16x32(self, vector: i16x32<Self>) -> mask16x32<Self>;
fn to_vector_mask16x32(self, a: mask16x32<Self>) -> i16x32<Self>;
fn set_mask16x32(self, a: &mut mask16x32<Self>, index: usize, value: bool);
fn rotate_elements_left_mask16x32<const OFFSET: usize>(
self,
a: mask16x32<Self>,
) -> mask16x32<Self>;
fn rotate_elements_right_mask16x32<const OFFSET: usize>(
self,
a: mask16x32<Self>,
) -> mask16x32<Self>;
fn split_mask16x32(
self,
a: mask16x32<Self>,
) -> (mask16x16<Self>, mask16x16<Self>);
fn slide_i32x16<const SHIFT: usize>(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i32x16<Self>;
fn compress_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
) -> i32x16<Self>;
fn compress_merge_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
merge: i32x16<Self>,
) -> i32x16<Self>;
fn expand_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
) -> i32x16<Self>;
fn expand_merge_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
merge: i32x16<Self>,
) -> i32x16<Self>;
fn split_i32x16(self, a: i32x16<Self>) -> (i32x8<Self>, i32x8<Self>);
fn slide_u32x16<const SHIFT: usize>(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u32x16<Self>;
fn compress_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
) -> u32x16<Self>;
fn compress_merge_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
merge: u32x16<Self>,
) -> u32x16<Self>;
fn expand_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
) -> u32x16<Self>;
fn expand_merge_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
merge: u32x16<Self>,
) -> u32x16<Self>;
fn split_u32x16(self, a: u32x16<Self>) -> (u32x8<Self>, u32x8<Self>);
fn from_vector_mask32x16(self, vector: i32x16<Self>) -> mask32x16<Self>;
fn to_vector_mask32x16(self, a: mask32x16<Self>) -> i32x16<Self>;
fn set_mask32x16(self, a: &mut mask32x16<Self>, index: usize, value: bool);
fn rotate_elements_left_mask32x16<const OFFSET: usize>(
self,
a: mask32x16<Self>,
) -> mask32x16<Self>;
fn rotate_elements_right_mask32x16<const OFFSET: usize>(
self,
a: mask32x16<Self>,
) -> mask32x16<Self>;
fn split_mask32x16(
self,
a: mask32x16<Self>,
) -> (mask32x8<Self>, mask32x8<Self>);
fn slide_f64x8<const SHIFT: usize>(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> f64x8<Self>;
fn compress_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
) -> f64x8<Self>;
fn compress_merge_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
merge: f64x8<Self>,
) -> f64x8<Self>;
fn expand_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
) -> f64x8<Self>;
fn expand_merge_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
merge: f64x8<Self>,
) -> f64x8<Self>;
fn is_nan_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn is_infinite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn is_finite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn is_subnormal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn is_normal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn is_sign_positive_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn is_sign_negative_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
fn split_f64x8(self, a: f64x8<Self>) -> (f64x4<Self>, f64x4<Self>);
fn slide_i64x8<const SHIFT: usize>(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> i64x8<Self>;
fn compress_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
) -> i64x8<Self>;
fn compress_merge_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
merge: i64x8<Self>,
) -> i64x8<Self>;
fn expand_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
) -> i64x8<Self>;
fn expand_merge_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
merge: i64x8<Self>,
) -> i64x8<Self>;
fn split_i64x8(self, a: i64x8<Self>) -> (i64x4<Self>, i64x4<Self>);
fn slide_u64x8<const SHIFT: usize>(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> u64x8<Self>;
fn compress_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
) -> u64x8<Self>;
fn compress_merge_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
merge: u64x8<Self>,
) -> u64x8<Self>;
fn expand_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
) -> u64x8<Self>;
fn expand_merge_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
merge: u64x8<Self>,
) -> u64x8<Self>;
fn split_u64x8(self, a: u64x8<Self>) -> (u64x4<Self>, u64x4<Self>);
fn from_vector_mask64x8(self, vector: i64x8<Self>) -> mask64x8<Self>;
fn to_vector_mask64x8(self, a: mask64x8<Self>) -> i64x8<Self>;
fn set_mask64x8(self, a: &mut mask64x8<Self>, index: usize, value: bool);
fn rotate_elements_left_mask64x8<const OFFSET: usize>(
self,
a: mask64x8<Self>,
) -> mask64x8<Self>;
fn rotate_elements_right_mask64x8<const OFFSET: usize>(
self,
a: mask64x8<Self>,
) -> mask64x8<Self>;
fn split_mask64x8(
self,
a: mask64x8<Self>,
) -> (mask64x4<Self>, mask64x4<Self>);
// Provided methods
fn slide_within_blocks_f32x4<const SHIFT: usize>(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> f32x4<Self> { ... }
fn swizzle_dyn_within_blocks_f32x4(
self,
a: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self> { ... }
fn swizzle_dyn_f32x4(
self,
a: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self> { ... }
fn swizzle_dyn_precise_f32x4(
self,
a: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self> { ... }
fn concat_swizzle_dyn_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self> { ... }
fn concat_swizzle_dyn_precise_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self> { ... }
fn simd_ne_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self> { ... }
fn simd_ge_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self> { ... }
fn simd_gt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self> { ... }
fn slide_within_blocks_i8x16<const SHIFT: usize>(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> i8x16<Self> { ... }
fn swizzle_dyn_within_blocks_i8x16(
self,
a: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self> { ... }
fn swizzle_dyn_i8x16(
self,
a: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self> { ... }
fn swizzle_dyn_precise_i8x16(
self,
a: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self> { ... }
fn concat_swizzle_dyn_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self> { ... }
fn concat_swizzle_dyn_precise_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self> { ... }
fn simd_ne_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self> { ... }
fn simd_ge_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self> { ... }
fn simd_gt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self> { ... }
fn abs_u8x16(self, a: u8x16<Self>) -> u8x16<Self> { ... }
fn slide_within_blocks_u8x16<const SHIFT: usize>(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> u8x16<Self> { ... }
fn simd_ne_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self> { ... }
fn simd_ge_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self> { ... }
fn simd_gt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self> { ... }
fn simd_ne_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x16<Self> { ... }
fn slide_within_blocks_i16x8<const SHIFT: usize>(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i16x8<Self> { ... }
fn swizzle_dyn_within_blocks_i16x8(
self,
a: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self> { ... }
fn swizzle_dyn_i16x8(
self,
a: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self> { ... }
fn swizzle_dyn_precise_i16x8(
self,
a: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self> { ... }
fn concat_swizzle_dyn_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self> { ... }
fn concat_swizzle_dyn_precise_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self> { ... }
fn simd_ne_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self> { ... }
fn simd_ge_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self> { ... }
fn simd_gt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self> { ... }
fn abs_u16x8(self, a: u16x8<Self>) -> u16x8<Self> { ... }
fn slide_within_blocks_u16x8<const SHIFT: usize>(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u16x8<Self> { ... }
fn swizzle_dyn_within_blocks_u16x8(
self,
a: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self> { ... }
fn swizzle_dyn_u16x8(
self,
a: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self> { ... }
fn swizzle_dyn_precise_u16x8(
self,
a: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self> { ... }
fn concat_swizzle_dyn_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self> { ... }
fn concat_swizzle_dyn_precise_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self> { ... }
fn simd_ne_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self> { ... }
fn simd_ge_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self> { ... }
fn simd_gt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self> { ... }
fn simd_ne_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x8<Self> { ... }
fn slide_within_blocks_i32x4<const SHIFT: usize>(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i32x4<Self> { ... }
fn swizzle_dyn_within_blocks_i32x4(
self,
a: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self> { ... }
fn swizzle_dyn_i32x4(
self,
a: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self> { ... }
fn swizzle_dyn_precise_i32x4(
self,
a: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self> { ... }
fn concat_swizzle_dyn_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self> { ... }
fn concat_swizzle_dyn_precise_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self> { ... }
fn simd_ne_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self> { ... }
fn simd_ge_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self> { ... }
fn simd_gt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self> { ... }
fn abs_u32x4(self, a: u32x4<Self>) -> u32x4<Self> { ... }
fn slide_within_blocks_u32x4<const SHIFT: usize>(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u32x4<Self> { ... }
fn swizzle_dyn_within_blocks_u32x4(
self,
a: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self> { ... }
fn swizzle_dyn_u32x4(
self,
a: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self> { ... }
fn swizzle_dyn_precise_u32x4(
self,
a: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self> { ... }
fn concat_swizzle_dyn_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self> { ... }
fn concat_swizzle_dyn_precise_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self> { ... }
fn simd_ne_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self> { ... }
fn simd_ge_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self> { ... }
fn simd_gt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self> { ... }
fn simd_ne_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x4<Self> { ... }
fn slide_within_blocks_f64x2<const SHIFT: usize>(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> f64x2<Self> { ... }
fn swizzle_dyn_within_blocks_f64x2(
self,
a: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self> { ... }
fn swizzle_dyn_f64x2(
self,
a: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self> { ... }
fn swizzle_dyn_precise_f64x2(
self,
a: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self> { ... }
fn concat_swizzle_dyn_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self> { ... }
fn concat_swizzle_dyn_precise_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self> { ... }
fn simd_ne_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self> { ... }
fn simd_ge_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self> { ... }
fn simd_gt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self> { ... }
fn slide_within_blocks_i64x2<const SHIFT: usize>(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> i64x2<Self> { ... }
fn swizzle_dyn_within_blocks_i64x2(
self,
a: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self> { ... }
fn swizzle_dyn_i64x2(
self,
a: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self> { ... }
fn swizzle_dyn_precise_i64x2(
self,
a: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self> { ... }
fn concat_swizzle_dyn_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self> { ... }
fn concat_swizzle_dyn_precise_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self> { ... }
fn simd_ne_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self> { ... }
fn simd_ge_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self> { ... }
fn simd_gt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self> { ... }
fn abs_u64x2(self, a: u64x2<Self>) -> u64x2<Self> { ... }
fn slide_within_blocks_u64x2<const SHIFT: usize>(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> u64x2<Self> { ... }
fn swizzle_dyn_within_blocks_u64x2(
self,
a: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self> { ... }
fn swizzle_dyn_u64x2(
self,
a: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self> { ... }
fn swizzle_dyn_precise_u64x2(
self,
a: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self> { ... }
fn concat_swizzle_dyn_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self> { ... }
fn concat_swizzle_dyn_precise_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self> { ... }
fn simd_ne_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self> { ... }
fn simd_ge_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self> { ... }
fn simd_gt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self> { ... }
fn simd_ne_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x2<Self> { ... }
fn abs_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn splat_f32x8(self, val: f32) -> f32x8<Self> { ... }
fn reverse_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn slide_within_blocks_f32x8<const SHIFT: usize>(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> f32x8<Self> { ... }
fn swizzle_dyn_within_blocks_f32x8(
self,
a: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self> { ... }
fn swizzle_dyn_f32x8(
self,
a: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self> { ... }
fn swizzle_dyn_precise_f32x8(
self,
a: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self> { ... }
fn concat_swizzle_dyn_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self> { ... }
fn concat_swizzle_dyn_precise_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self> { ... }
fn neg_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn sqrt_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn approximate_recip_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn add_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn sub_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn mul_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn div_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn copysign_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn reduce_max_f32x8(self, a: f32x8<Self>) -> f32 { ... }
fn reduce_min_f32x8(self, a: f32x8<Self>) -> f32 { ... }
fn reduce_max_precise_f32x8(self, a: f32x8<Self>) -> f32 { ... }
fn reduce_min_precise_f32x8(self, a: f32x8<Self>) -> f32 { ... }
fn reduce_sum_f32x8(self, a: f32x8<Self>) -> f32 { ... }
fn reduce_product_f32x8(self, a: f32x8<Self>) -> f32 { ... }
fn max_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn min_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn max_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn min_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn clamp_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self> { ... }
fn simd_eq_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> { ... }
fn simd_ne_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> { ... }
fn simd_lt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> { ... }
fn simd_le_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> { ... }
fn simd_ge_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> { ... }
fn simd_gt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> { ... }
fn zip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn zip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn unzip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn unzip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> { ... }
fn interleave_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> (f32x8<Self>, f32x8<Self>) { ... }
fn deinterleave_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> (f32x8<Self>, f32x8<Self>) { ... }
fn mul_add_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self> { ... }
fn mul_add_precise_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self> { ... }
fn mul_sub_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self> { ... }
fn mul_sub_precise_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self> { ... }
fn floor_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn ceil_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn round_ties_even_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn round_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn fract_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn trunc_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn to_degrees_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn to_radians_f32x8(self, a: f32x8<Self>) -> f32x8<Self> { ... }
fn select_f32x8(
self,
a: mask32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self> { ... }
fn widen_f32x8(self, a: f32x8<Self>) -> (f64x4<Self>, f64x4<Self>) { ... }
fn cvt_u32_f32x8(self, a: f32x8<Self>) -> u32x8<Self> { ... }
fn cvt_u32_precise_f32x8(self, a: f32x8<Self>) -> u32x8<Self> { ... }
fn cvt_i32_f32x8(self, a: f32x8<Self>) -> i32x8<Self> { ... }
fn cvt_i32_precise_f32x8(self, a: f32x8<Self>) -> i32x8<Self> { ... }
fn abs_i8x32(self, a: i8x32<Self>) -> i8x32<Self> { ... }
fn splat_i8x32(self, val: i8) -> i8x32<Self> { ... }
fn reverse_i8x32(self, a: i8x32<Self>) -> i8x32<Self> { ... }
fn slide_within_blocks_i8x32<const SHIFT: usize>(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> i8x32<Self> { ... }
fn swizzle_dyn_within_blocks_i8x32(
self,
a: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self> { ... }
fn swizzle_dyn_i8x32(
self,
a: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self> { ... }
fn swizzle_dyn_precise_i8x32(
self,
a: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self> { ... }
fn concat_swizzle_dyn_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self> { ... }
fn concat_swizzle_dyn_precise_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self> { ... }
fn count_ones_i8x32(self, a: i8x32<Self>) -> i8x32<Self> { ... }
fn count_zeros_i8x32(self, a: i8x32<Self>) -> i8x32<Self> { ... }
fn add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn saturating_add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn saturating_sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn mul_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn and_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn or_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn xor_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn not_i8x32(self, a: i8x32<Self>) -> i8x32<Self> { ... }
fn shl_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self> { ... }
fn shlv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn shr_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self> { ... }
fn shrv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn reduce_max_i8x32(self, a: i8x32<Self>) -> i8 { ... }
fn reduce_min_i8x32(self, a: i8x32<Self>) -> i8 { ... }
fn reduce_sum_i8x32(self, a: i8x32<Self>) -> i8 { ... }
fn reduce_product_i8x32(self, a: i8x32<Self>) -> i8 { ... }
fn max_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn min_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn clamp_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
c: i8x32<Self>,
) -> i8x32<Self> { ... }
fn simd_eq_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> { ... }
fn simd_ne_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> { ... }
fn simd_lt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> { ... }
fn simd_le_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> { ... }
fn simd_ge_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> { ... }
fn simd_gt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> { ... }
fn zip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn zip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn unzip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn unzip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> { ... }
fn interleave_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i8x32<Self>, i8x32<Self>) { ... }
fn deinterleave_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i8x32<Self>, i8x32<Self>) { ... }
fn select_i8x32(
self,
a: mask8x32<Self>,
b: i8x32<Self>,
c: i8x32<Self>,
) -> i8x32<Self> { ... }
fn neg_i8x32(self, a: i8x32<Self>) -> i8x32<Self> { ... }
fn widen_i8x32(self, a: i8x32<Self>) -> (i16x16<Self>, i16x16<Self>) { ... }
fn widening_mul_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i16x16<Self>, i16x16<Self>) { ... }
fn widening_add_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i16x16<Self>, i16x16<Self>) { ... }
fn pairwise_widening_add_i8x32(self, a: i8x32<Self>) -> i16x16<Self> { ... }
fn pairwise_dot_product_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> i16x16<Self> { ... }
fn abs_u8x32(self, a: u8x32<Self>) -> u8x32<Self> { ... }
fn splat_u8x32(self, val: u8) -> u8x32<Self> { ... }
fn reverse_u8x32(self, a: u8x32<Self>) -> u8x32<Self> { ... }
fn slide_within_blocks_u8x32<const SHIFT: usize>(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> u8x32<Self> { ... }
fn swizzle_dyn_within_blocks_u8x32(
self,
a: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self> { ... }
fn count_ones_u8x32(self, a: u8x32<Self>) -> u8x32<Self> { ... }
fn count_zeros_u8x32(self, a: u8x32<Self>) -> u8x32<Self> { ... }
fn add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn saturating_add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn saturating_sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn mul_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn and_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn or_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn xor_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn not_u8x32(self, a: u8x32<Self>) -> u8x32<Self> { ... }
fn shl_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self> { ... }
fn shlv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn shr_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self> { ... }
fn shrv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn reduce_max_u8x32(self, a: u8x32<Self>) -> u8 { ... }
fn reduce_min_u8x32(self, a: u8x32<Self>) -> u8 { ... }
fn reduce_sum_u8x32(self, a: u8x32<Self>) -> u8 { ... }
fn reduce_product_u8x32(self, a: u8x32<Self>) -> u8 { ... }
fn max_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn min_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn clamp_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
c: u8x32<Self>,
) -> u8x32<Self> { ... }
fn simd_eq_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> { ... }
fn simd_ne_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> { ... }
fn simd_lt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> { ... }
fn simd_le_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> { ... }
fn simd_ge_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> { ... }
fn simd_gt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> { ... }
fn zip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn zip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn unzip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn unzip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> { ... }
fn interleave_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u8x32<Self>, u8x32<Self>) { ... }
fn deinterleave_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u8x32<Self>, u8x32<Self>) { ... }
fn select_u8x32(
self,
a: mask8x32<Self>,
b: u8x32<Self>,
c: u8x32<Self>,
) -> u8x32<Self> { ... }
fn widen_u8x32(self, a: u8x32<Self>) -> (u16x16<Self>, u16x16<Self>) { ... }
fn widening_mul_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u16x16<Self>, u16x16<Self>) { ... }
fn widening_add_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u16x16<Self>, u16x16<Self>) { ... }
fn pairwise_widening_add_u8x32(self, a: u8x32<Self>) -> u16x16<Self> { ... }
fn pairwise_dot_product_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> u16x16<Self> { ... }
fn splat_mask8x32(self, val: bool) -> mask8x32<Self> { ... }
fn from_bitmask_mask8x32(self, bits: u64) -> mask8x32<Self> { ... }
fn to_bitmask_mask8x32(self, a: mask8x32<Self>) -> u64 { ... }
fn and_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x32<Self> { ... }
fn or_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self> { ... }
fn xor_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x32<Self> { ... }
fn not_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self> { ... }
fn reverse_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self> { ... }
fn select_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
c: mask8x32<Self>,
) -> mask8x32<Self> { ... }
fn simd_eq_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x32<Self> { ... }
fn simd_ne_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x32<Self> { ... }
fn any_true_mask8x32(self, a: mask8x32<Self>) -> bool { ... }
fn all_true_mask8x32(self, a: mask8x32<Self>) -> bool { ... }
fn any_false_mask8x32(self, a: mask8x32<Self>) -> bool { ... }
fn all_false_mask8x32(self, a: mask8x32<Self>) -> bool { ... }
fn widen_mask8x32(
self,
a: mask8x32<Self>,
) -> (mask16x16<Self>, mask16x16<Self>) { ... }
fn abs_i16x16(self, a: i16x16<Self>) -> i16x16<Self> { ... }
fn splat_i16x16(self, val: i16) -> i16x16<Self> { ... }
fn reverse_i16x16(self, a: i16x16<Self>) -> i16x16<Self> { ... }
fn slide_within_blocks_i16x16<const SHIFT: usize>(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i16x16<Self> { ... }
fn swizzle_dyn_within_blocks_i16x16(
self,
a: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self> { ... }
fn swizzle_dyn_i16x16(
self,
a: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self> { ... }
fn swizzle_dyn_precise_i16x16(
self,
a: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self> { ... }
fn concat_swizzle_dyn_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self> { ... }
fn concat_swizzle_dyn_precise_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self> { ... }
fn count_ones_i16x16(self, a: i16x16<Self>) -> i16x16<Self> { ... }
fn count_zeros_i16x16(self, a: i16x16<Self>) -> i16x16<Self> { ... }
fn add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn saturating_add_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i16x16<Self> { ... }
fn sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn saturating_sub_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i16x16<Self> { ... }
fn mul_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn and_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn or_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn xor_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn not_i16x16(self, a: i16x16<Self>) -> i16x16<Self> { ... }
fn shl_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self> { ... }
fn shlv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn shr_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self> { ... }
fn shrv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn reduce_max_i16x16(self, a: i16x16<Self>) -> i16 { ... }
fn reduce_min_i16x16(self, a: i16x16<Self>) -> i16 { ... }
fn reduce_sum_i16x16(self, a: i16x16<Self>) -> i16 { ... }
fn reduce_product_i16x16(self, a: i16x16<Self>) -> i16 { ... }
fn max_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn min_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn clamp_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
c: i16x16<Self>,
) -> i16x16<Self> { ... }
fn simd_eq_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> { ... }
fn simd_ne_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> { ... }
fn simd_lt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> { ... }
fn simd_le_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> { ... }
fn simd_ge_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> { ... }
fn simd_gt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> { ... }
fn zip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn zip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn unzip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn unzip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> { ... }
fn interleave_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i16x16<Self>, i16x16<Self>) { ... }
fn deinterleave_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i16x16<Self>, i16x16<Self>) { ... }
fn select_i16x16(
self,
a: mask16x16<Self>,
b: i16x16<Self>,
c: i16x16<Self>,
) -> i16x16<Self> { ... }
fn neg_i16x16(self, a: i16x16<Self>) -> i16x16<Self> { ... }
fn widen_i16x16(self, a: i16x16<Self>) -> (i32x8<Self>, i32x8<Self>) { ... }
fn widening_mul_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i32x8<Self>, i32x8<Self>) { ... }
fn widening_add_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i32x8<Self>, i32x8<Self>) { ... }
fn pairwise_widening_add_i16x16(self, a: i16x16<Self>) -> i32x8<Self> { ... }
fn pairwise_dot_product_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i32x8<Self> { ... }
fn narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self> { ... }
fn saturating_narrow_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i8x32<Self> { ... }
fn relaxed_narrow_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i8x32<Self> { ... }
fn abs_u16x16(self, a: u16x16<Self>) -> u16x16<Self> { ... }
fn splat_u16x16(self, val: u16) -> u16x16<Self> { ... }
fn reverse_u16x16(self, a: u16x16<Self>) -> u16x16<Self> { ... }
fn slide_within_blocks_u16x16<const SHIFT: usize>(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u16x16<Self> { ... }
fn swizzle_dyn_within_blocks_u16x16(
self,
a: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self> { ... }
fn swizzle_dyn_u16x16(
self,
a: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self> { ... }
fn swizzle_dyn_precise_u16x16(
self,
a: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self> { ... }
fn concat_swizzle_dyn_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self> { ... }
fn concat_swizzle_dyn_precise_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self> { ... }
fn count_ones_u16x16(self, a: u16x16<Self>) -> u16x16<Self> { ... }
fn count_zeros_u16x16(self, a: u16x16<Self>) -> u16x16<Self> { ... }
fn add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn saturating_add_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u16x16<Self> { ... }
fn sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn saturating_sub_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u16x16<Self> { ... }
fn mul_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn and_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn or_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn xor_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn not_u16x16(self, a: u16x16<Self>) -> u16x16<Self> { ... }
fn shl_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self> { ... }
fn shlv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn shr_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self> { ... }
fn shrv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn reduce_max_u16x16(self, a: u16x16<Self>) -> u16 { ... }
fn reduce_min_u16x16(self, a: u16x16<Self>) -> u16 { ... }
fn reduce_sum_u16x16(self, a: u16x16<Self>) -> u16 { ... }
fn reduce_product_u16x16(self, a: u16x16<Self>) -> u16 { ... }
fn max_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn min_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn clamp_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
c: u16x16<Self>,
) -> u16x16<Self> { ... }
fn simd_eq_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> { ... }
fn simd_ne_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> { ... }
fn simd_lt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> { ... }
fn simd_le_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> { ... }
fn simd_ge_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> { ... }
fn simd_gt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> { ... }
fn zip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn zip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn unzip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn unzip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> { ... }
fn interleave_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u16x16<Self>, u16x16<Self>) { ... }
fn deinterleave_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u16x16<Self>, u16x16<Self>) { ... }
fn select_u16x16(
self,
a: mask16x16<Self>,
b: u16x16<Self>,
c: u16x16<Self>,
) -> u16x16<Self> { ... }
fn widen_u16x16(self, a: u16x16<Self>) -> (u32x8<Self>, u32x8<Self>) { ... }
fn widening_mul_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u32x8<Self>, u32x8<Self>) { ... }
fn widening_add_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u32x8<Self>, u32x8<Self>) { ... }
fn pairwise_widening_add_u16x16(self, a: u16x16<Self>) -> u32x8<Self> { ... }
fn pairwise_dot_product_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u32x8<Self> { ... }
fn narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self> { ... }
fn saturating_narrow_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u8x32<Self> { ... }
fn relaxed_narrow_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u8x32<Self> { ... }
fn splat_mask16x16(self, val: bool) -> mask16x16<Self> { ... }
fn from_bitmask_mask16x16(self, bits: u64) -> mask16x16<Self> { ... }
fn to_bitmask_mask16x16(self, a: mask16x16<Self>) -> u64 { ... }
fn and_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self> { ... }
fn or_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self> { ... }
fn xor_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self> { ... }
fn not_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self> { ... }
fn reverse_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self> { ... }
fn select_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
c: mask16x16<Self>,
) -> mask16x16<Self> { ... }
fn simd_eq_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self> { ... }
fn simd_ne_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self> { ... }
fn any_true_mask16x16(self, a: mask16x16<Self>) -> bool { ... }
fn all_true_mask16x16(self, a: mask16x16<Self>) -> bool { ... }
fn any_false_mask16x16(self, a: mask16x16<Self>) -> bool { ... }
fn all_false_mask16x16(self, a: mask16x16<Self>) -> bool { ... }
fn widen_mask16x16(
self,
a: mask16x16<Self>,
) -> (mask32x8<Self>, mask32x8<Self>) { ... }
fn narrow_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask8x32<Self> { ... }
fn abs_i32x8(self, a: i32x8<Self>) -> i32x8<Self> { ... }
fn splat_i32x8(self, val: i32) -> i32x8<Self> { ... }
fn reverse_i32x8(self, a: i32x8<Self>) -> i32x8<Self> { ... }
fn slide_within_blocks_i32x8<const SHIFT: usize>(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i32x8<Self> { ... }
fn swizzle_dyn_within_blocks_i32x8(
self,
a: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self> { ... }
fn swizzle_dyn_i32x8(
self,
a: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self> { ... }
fn swizzle_dyn_precise_i32x8(
self,
a: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self> { ... }
fn concat_swizzle_dyn_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self> { ... }
fn concat_swizzle_dyn_precise_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self> { ... }
fn count_ones_i32x8(self, a: i32x8<Self>) -> i32x8<Self> { ... }
fn count_zeros_i32x8(self, a: i32x8<Self>) -> i32x8<Self> { ... }
fn add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn saturating_add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn saturating_sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn mul_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn and_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn or_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn xor_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn not_i32x8(self, a: i32x8<Self>) -> i32x8<Self> { ... }
fn shl_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self> { ... }
fn shlv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn shr_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self> { ... }
fn shrv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn reduce_max_i32x8(self, a: i32x8<Self>) -> i32 { ... }
fn reduce_min_i32x8(self, a: i32x8<Self>) -> i32 { ... }
fn reduce_sum_i32x8(self, a: i32x8<Self>) -> i32 { ... }
fn reduce_product_i32x8(self, a: i32x8<Self>) -> i32 { ... }
fn max_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn min_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn clamp_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
c: i32x8<Self>,
) -> i32x8<Self> { ... }
fn simd_eq_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> { ... }
fn simd_ne_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> { ... }
fn simd_lt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> { ... }
fn simd_le_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> { ... }
fn simd_ge_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> { ... }
fn simd_gt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> { ... }
fn zip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn zip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn unzip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn unzip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> { ... }
fn interleave_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i32x8<Self>, i32x8<Self>) { ... }
fn deinterleave_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i32x8<Self>, i32x8<Self>) { ... }
fn select_i32x8(
self,
a: mask32x8<Self>,
b: i32x8<Self>,
c: i32x8<Self>,
) -> i32x8<Self> { ... }
fn neg_i32x8(self, a: i32x8<Self>) -> i32x8<Self> { ... }
fn widen_i32x8(self, a: i32x8<Self>) -> (i64x4<Self>, i64x4<Self>) { ... }
fn widening_mul_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i64x4<Self>, i64x4<Self>) { ... }
fn widening_add_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i64x4<Self>, i64x4<Self>) { ... }
fn pairwise_widening_add_i32x8(self, a: i32x8<Self>) -> i64x4<Self> { ... }
fn pairwise_dot_product_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i64x4<Self> { ... }
fn narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self> { ... }
fn saturating_narrow_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i16x16<Self> { ... }
fn relaxed_narrow_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i16x16<Self> { ... }
fn cvt_f32_i32x8(self, a: i32x8<Self>) -> f32x8<Self> { ... }
fn abs_u32x8(self, a: u32x8<Self>) -> u32x8<Self> { ... }
fn splat_u32x8(self, val: u32) -> u32x8<Self> { ... }
fn reverse_u32x8(self, a: u32x8<Self>) -> u32x8<Self> { ... }
fn slide_within_blocks_u32x8<const SHIFT: usize>(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u32x8<Self> { ... }
fn swizzle_dyn_within_blocks_u32x8(
self,
a: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self> { ... }
fn swizzle_dyn_u32x8(
self,
a: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self> { ... }
fn swizzle_dyn_precise_u32x8(
self,
a: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self> { ... }
fn concat_swizzle_dyn_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self> { ... }
fn concat_swizzle_dyn_precise_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self> { ... }
fn count_ones_u32x8(self, a: u32x8<Self>) -> u32x8<Self> { ... }
fn count_zeros_u32x8(self, a: u32x8<Self>) -> u32x8<Self> { ... }
fn add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn saturating_add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn saturating_sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn mul_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn and_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn or_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn xor_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn not_u32x8(self, a: u32x8<Self>) -> u32x8<Self> { ... }
fn shl_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self> { ... }
fn shlv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn shr_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self> { ... }
fn shrv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn reduce_max_u32x8(self, a: u32x8<Self>) -> u32 { ... }
fn reduce_min_u32x8(self, a: u32x8<Self>) -> u32 { ... }
fn reduce_sum_u32x8(self, a: u32x8<Self>) -> u32 { ... }
fn reduce_product_u32x8(self, a: u32x8<Self>) -> u32 { ... }
fn max_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn min_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn clamp_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
c: u32x8<Self>,
) -> u32x8<Self> { ... }
fn simd_eq_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> { ... }
fn simd_ne_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> { ... }
fn simd_lt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> { ... }
fn simd_le_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> { ... }
fn simd_ge_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> { ... }
fn simd_gt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> { ... }
fn zip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn zip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn unzip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn unzip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> { ... }
fn interleave_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u32x8<Self>, u32x8<Self>) { ... }
fn deinterleave_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u32x8<Self>, u32x8<Self>) { ... }
fn select_u32x8(
self,
a: mask32x8<Self>,
b: u32x8<Self>,
c: u32x8<Self>,
) -> u32x8<Self> { ... }
fn widen_u32x8(self, a: u32x8<Self>) -> (u64x4<Self>, u64x4<Self>) { ... }
fn widening_mul_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u64x4<Self>, u64x4<Self>) { ... }
fn widening_add_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u64x4<Self>, u64x4<Self>) { ... }
fn pairwise_widening_add_u32x8(self, a: u32x8<Self>) -> u64x4<Self> { ... }
fn pairwise_dot_product_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u64x4<Self> { ... }
fn narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self> { ... }
fn saturating_narrow_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u16x16<Self> { ... }
fn relaxed_narrow_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u16x16<Self> { ... }
fn cvt_f32_u32x8(self, a: u32x8<Self>) -> f32x8<Self> { ... }
fn splat_mask32x8(self, val: bool) -> mask32x8<Self> { ... }
fn from_bitmask_mask32x8(self, bits: u64) -> mask32x8<Self> { ... }
fn to_bitmask_mask32x8(self, a: mask32x8<Self>) -> u64 { ... }
fn and_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x8<Self> { ... }
fn or_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self> { ... }
fn xor_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x8<Self> { ... }
fn not_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self> { ... }
fn reverse_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self> { ... }
fn select_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
c: mask32x8<Self>,
) -> mask32x8<Self> { ... }
fn simd_eq_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x8<Self> { ... }
fn simd_ne_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x8<Self> { ... }
fn any_true_mask32x8(self, a: mask32x8<Self>) -> bool { ... }
fn all_true_mask32x8(self, a: mask32x8<Self>) -> bool { ... }
fn any_false_mask32x8(self, a: mask32x8<Self>) -> bool { ... }
fn all_false_mask32x8(self, a: mask32x8<Self>) -> bool { ... }
fn widen_mask32x8(
self,
a: mask32x8<Self>,
) -> (mask64x4<Self>, mask64x4<Self>) { ... }
fn narrow_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask16x16<Self> { ... }
fn abs_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn splat_f64x4(self, val: f64) -> f64x4<Self> { ... }
fn reverse_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn slide_within_blocks_f64x4<const SHIFT: usize>(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> f64x4<Self> { ... }
fn swizzle_dyn_within_blocks_f64x4(
self,
a: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self> { ... }
fn swizzle_dyn_f64x4(
self,
a: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self> { ... }
fn swizzle_dyn_precise_f64x4(
self,
a: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self> { ... }
fn concat_swizzle_dyn_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self> { ... }
fn concat_swizzle_dyn_precise_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self> { ... }
fn neg_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn sqrt_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn approximate_recip_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn add_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn sub_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn mul_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn div_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn copysign_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn reduce_max_f64x4(self, a: f64x4<Self>) -> f64 { ... }
fn reduce_min_f64x4(self, a: f64x4<Self>) -> f64 { ... }
fn reduce_max_precise_f64x4(self, a: f64x4<Self>) -> f64 { ... }
fn reduce_min_precise_f64x4(self, a: f64x4<Self>) -> f64 { ... }
fn reduce_sum_f64x4(self, a: f64x4<Self>) -> f64 { ... }
fn reduce_product_f64x4(self, a: f64x4<Self>) -> f64 { ... }
fn max_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn min_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn max_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn min_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn clamp_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self> { ... }
fn simd_eq_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> { ... }
fn simd_ne_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> { ... }
fn simd_lt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> { ... }
fn simd_le_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> { ... }
fn simd_ge_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> { ... }
fn simd_gt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> { ... }
fn zip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn zip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn unzip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn unzip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> { ... }
fn interleave_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> (f64x4<Self>, f64x4<Self>) { ... }
fn deinterleave_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> (f64x4<Self>, f64x4<Self>) { ... }
fn mul_add_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self> { ... }
fn mul_add_precise_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self> { ... }
fn mul_sub_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self> { ... }
fn mul_sub_precise_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self> { ... }
fn floor_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn ceil_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn round_ties_even_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn round_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn fract_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn trunc_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn to_degrees_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn to_radians_f64x4(self, a: f64x4<Self>) -> f64x4<Self> { ... }
fn select_f64x4(
self,
a: mask64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self> { ... }
fn narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self> { ... }
fn saturating_narrow_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> f32x8<Self> { ... }
fn relaxed_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self> { ... }
fn cvt_u64_f64x4(self, a: f64x4<Self>) -> u64x4<Self> { ... }
fn cvt_u64_precise_f64x4(self, a: f64x4<Self>) -> u64x4<Self> { ... }
fn cvt_i64_f64x4(self, a: f64x4<Self>) -> i64x4<Self> { ... }
fn cvt_i64_precise_f64x4(self, a: f64x4<Self>) -> i64x4<Self> { ... }
fn abs_i64x4(self, a: i64x4<Self>) -> i64x4<Self> { ... }
fn splat_i64x4(self, val: i64) -> i64x4<Self> { ... }
fn reverse_i64x4(self, a: i64x4<Self>) -> i64x4<Self> { ... }
fn slide_within_blocks_i64x4<const SHIFT: usize>(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> i64x4<Self> { ... }
fn swizzle_dyn_within_blocks_i64x4(
self,
a: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self> { ... }
fn swizzle_dyn_i64x4(
self,
a: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self> { ... }
fn swizzle_dyn_precise_i64x4(
self,
a: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self> { ... }
fn concat_swizzle_dyn_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self> { ... }
fn concat_swizzle_dyn_precise_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self> { ... }
fn count_ones_i64x4(self, a: i64x4<Self>) -> i64x4<Self> { ... }
fn count_zeros_i64x4(self, a: i64x4<Self>) -> i64x4<Self> { ... }
fn add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn saturating_add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn saturating_sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn mul_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn and_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn or_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn xor_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn not_i64x4(self, a: i64x4<Self>) -> i64x4<Self> { ... }
fn shl_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self> { ... }
fn shlv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn shr_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self> { ... }
fn shrv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn reduce_max_i64x4(self, a: i64x4<Self>) -> i64 { ... }
fn reduce_min_i64x4(self, a: i64x4<Self>) -> i64 { ... }
fn reduce_sum_i64x4(self, a: i64x4<Self>) -> i64 { ... }
fn reduce_product_i64x4(self, a: i64x4<Self>) -> i64 { ... }
fn max_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn min_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn clamp_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
c: i64x4<Self>,
) -> i64x4<Self> { ... }
fn simd_eq_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> { ... }
fn simd_ne_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> { ... }
fn simd_lt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> { ... }
fn simd_le_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> { ... }
fn simd_ge_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> { ... }
fn simd_gt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> { ... }
fn zip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn zip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn unzip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn unzip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> { ... }
fn interleave_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> (i64x4<Self>, i64x4<Self>) { ... }
fn deinterleave_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> (i64x4<Self>, i64x4<Self>) { ... }
fn select_i64x4(
self,
a: mask64x4<Self>,
b: i64x4<Self>,
c: i64x4<Self>,
) -> i64x4<Self> { ... }
fn neg_i64x4(self, a: i64x4<Self>) -> i64x4<Self> { ... }
fn narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self> { ... }
fn saturating_narrow_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> i32x8<Self> { ... }
fn relaxed_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self> { ... }
fn cvt_f64_i64x4(self, a: i64x4<Self>) -> f64x4<Self> { ... }
fn abs_u64x4(self, a: u64x4<Self>) -> u64x4<Self> { ... }
fn splat_u64x4(self, val: u64) -> u64x4<Self> { ... }
fn reverse_u64x4(self, a: u64x4<Self>) -> u64x4<Self> { ... }
fn slide_within_blocks_u64x4<const SHIFT: usize>(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> u64x4<Self> { ... }
fn swizzle_dyn_within_blocks_u64x4(
self,
a: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self> { ... }
fn swizzle_dyn_u64x4(
self,
a: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self> { ... }
fn swizzle_dyn_precise_u64x4(
self,
a: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self> { ... }
fn concat_swizzle_dyn_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self> { ... }
fn concat_swizzle_dyn_precise_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self> { ... }
fn count_ones_u64x4(self, a: u64x4<Self>) -> u64x4<Self> { ... }
fn count_zeros_u64x4(self, a: u64x4<Self>) -> u64x4<Self> { ... }
fn add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn saturating_add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn saturating_sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn mul_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn and_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn or_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn xor_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn not_u64x4(self, a: u64x4<Self>) -> u64x4<Self> { ... }
fn shl_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self> { ... }
fn shlv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn shr_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self> { ... }
fn shrv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn reduce_max_u64x4(self, a: u64x4<Self>) -> u64 { ... }
fn reduce_min_u64x4(self, a: u64x4<Self>) -> u64 { ... }
fn reduce_sum_u64x4(self, a: u64x4<Self>) -> u64 { ... }
fn reduce_product_u64x4(self, a: u64x4<Self>) -> u64 { ... }
fn max_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn min_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn clamp_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
c: u64x4<Self>,
) -> u64x4<Self> { ... }
fn simd_eq_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> { ... }
fn simd_ne_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> { ... }
fn simd_lt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> { ... }
fn simd_le_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> { ... }
fn simd_ge_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> { ... }
fn simd_gt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> { ... }
fn zip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn zip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn unzip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn unzip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> { ... }
fn interleave_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> (u64x4<Self>, u64x4<Self>) { ... }
fn deinterleave_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> (u64x4<Self>, u64x4<Self>) { ... }
fn select_u64x4(
self,
a: mask64x4<Self>,
b: u64x4<Self>,
c: u64x4<Self>,
) -> u64x4<Self> { ... }
fn narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self> { ... }
fn saturating_narrow_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> u32x8<Self> { ... }
fn relaxed_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self> { ... }
fn cvt_f64_u64x4(self, a: u64x4<Self>) -> f64x4<Self> { ... }
fn splat_mask64x4(self, val: bool) -> mask64x4<Self> { ... }
fn from_bitmask_mask64x4(self, bits: u64) -> mask64x4<Self> { ... }
fn to_bitmask_mask64x4(self, a: mask64x4<Self>) -> u64 { ... }
fn and_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x4<Self> { ... }
fn or_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self> { ... }
fn xor_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x4<Self> { ... }
fn not_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self> { ... }
fn reverse_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self> { ... }
fn select_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
c: mask64x4<Self>,
) -> mask64x4<Self> { ... }
fn simd_eq_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x4<Self> { ... }
fn simd_ne_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x4<Self> { ... }
fn any_true_mask64x4(self, a: mask64x4<Self>) -> bool { ... }
fn all_true_mask64x4(self, a: mask64x4<Self>) -> bool { ... }
fn any_false_mask64x4(self, a: mask64x4<Self>) -> bool { ... }
fn all_false_mask64x4(self, a: mask64x4<Self>) -> bool { ... }
fn narrow_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask32x8<Self> { ... }
fn abs_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn splat_f32x16(self, val: f32) -> f32x16<Self> { ... }
fn reverse_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn slide_within_blocks_f32x16<const SHIFT: usize>(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> f32x16<Self> { ... }
fn swizzle_dyn_within_blocks_f32x16(
self,
a: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self> { ... }
fn swizzle_dyn_f32x16(
self,
a: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self> { ... }
fn swizzle_dyn_precise_f32x16(
self,
a: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self> { ... }
fn concat_swizzle_dyn_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self> { ... }
fn concat_swizzle_dyn_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self> { ... }
fn neg_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn sqrt_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn approximate_recip_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn add_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn sub_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn mul_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn div_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn copysign_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn reduce_max_f32x16(self, a: f32x16<Self>) -> f32 { ... }
fn reduce_min_f32x16(self, a: f32x16<Self>) -> f32 { ... }
fn reduce_max_precise_f32x16(self, a: f32x16<Self>) -> f32 { ... }
fn reduce_min_precise_f32x16(self, a: f32x16<Self>) -> f32 { ... }
fn reduce_sum_f32x16(self, a: f32x16<Self>) -> f32 { ... }
fn reduce_product_f32x16(self, a: f32x16<Self>) -> f32 { ... }
fn max_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn min_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn max_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> f32x16<Self> { ... }
fn min_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> f32x16<Self> { ... }
fn clamp_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self> { ... }
fn simd_eq_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> { ... }
fn simd_ne_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> { ... }
fn simd_lt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> { ... }
fn simd_le_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> { ... }
fn simd_ge_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> { ... }
fn simd_gt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> { ... }
fn zip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn zip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn unzip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn unzip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> { ... }
fn interleave_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> (f32x16<Self>, f32x16<Self>) { ... }
fn deinterleave_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> (f32x16<Self>, f32x16<Self>) { ... }
fn mul_add_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self> { ... }
fn mul_add_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self> { ... }
fn mul_sub_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self> { ... }
fn mul_sub_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self> { ... }
fn floor_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn ceil_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn round_ties_even_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn round_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn fract_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn trunc_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn to_degrees_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn to_radians_f32x16(self, a: f32x16<Self>) -> f32x16<Self> { ... }
fn select_f32x16(
self,
a: mask32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self> { ... }
fn widen_f32x16(self, a: f32x16<Self>) -> (f64x8<Self>, f64x8<Self>) { ... }
fn cvt_u32_f32x16(self, a: f32x16<Self>) -> u32x16<Self> { ... }
fn cvt_u32_precise_f32x16(self, a: f32x16<Self>) -> u32x16<Self> { ... }
fn cvt_i32_f32x16(self, a: f32x16<Self>) -> i32x16<Self> { ... }
fn cvt_i32_precise_f32x16(self, a: f32x16<Self>) -> i32x16<Self> { ... }
fn abs_i8x64(self, a: i8x64<Self>) -> i8x64<Self> { ... }
fn splat_i8x64(self, val: i8) -> i8x64<Self> { ... }
fn reverse_i8x64(self, a: i8x64<Self>) -> i8x64<Self> { ... }
fn slide_within_blocks_i8x64<const SHIFT: usize>(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> i8x64<Self> { ... }
fn swizzle_dyn_within_blocks_i8x64(
self,
a: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self> { ... }
fn swizzle_dyn_i8x64(
self,
a: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self> { ... }
fn swizzle_dyn_precise_i8x64(
self,
a: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self> { ... }
fn concat_swizzle_dyn_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self> { ... }
fn concat_swizzle_dyn_precise_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self> { ... }
fn count_ones_i8x64(self, a: i8x64<Self>) -> i8x64<Self> { ... }
fn count_zeros_i8x64(self, a: i8x64<Self>) -> i8x64<Self> { ... }
fn add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn saturating_add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn saturating_sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn mul_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn and_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn or_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn xor_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn not_i8x64(self, a: i8x64<Self>) -> i8x64<Self> { ... }
fn shl_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self> { ... }
fn shlv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn shr_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self> { ... }
fn shrv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn reduce_max_i8x64(self, a: i8x64<Self>) -> i8 { ... }
fn reduce_min_i8x64(self, a: i8x64<Self>) -> i8 { ... }
fn reduce_sum_i8x64(self, a: i8x64<Self>) -> i8 { ... }
fn reduce_product_i8x64(self, a: i8x64<Self>) -> i8 { ... }
fn max_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn min_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn clamp_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
c: i8x64<Self>,
) -> i8x64<Self> { ... }
fn simd_eq_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> { ... }
fn simd_ne_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> { ... }
fn simd_lt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> { ... }
fn simd_le_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> { ... }
fn simd_ge_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> { ... }
fn simd_gt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> { ... }
fn zip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn zip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn unzip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn unzip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> { ... }
fn interleave_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i8x64<Self>, i8x64<Self>) { ... }
fn deinterleave_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i8x64<Self>, i8x64<Self>) { ... }
fn select_i8x64(
self,
a: mask8x64<Self>,
b: i8x64<Self>,
c: i8x64<Self>,
) -> i8x64<Self> { ... }
fn neg_i8x64(self, a: i8x64<Self>) -> i8x64<Self> { ... }
fn widen_i8x64(self, a: i8x64<Self>) -> (i16x32<Self>, i16x32<Self>) { ... }
fn widening_mul_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i16x32<Self>, i16x32<Self>) { ... }
fn widening_add_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i16x32<Self>, i16x32<Self>) { ... }
fn pairwise_widening_add_i8x64(self, a: i8x64<Self>) -> i16x32<Self> { ... }
fn pairwise_dot_product_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> i16x32<Self> { ... }
fn abs_u8x64(self, a: u8x64<Self>) -> u8x64<Self> { ... }
fn splat_u8x64(self, val: u8) -> u8x64<Self> { ... }
fn reverse_u8x64(self, a: u8x64<Self>) -> u8x64<Self> { ... }
fn slide_within_blocks_u8x64<const SHIFT: usize>(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> u8x64<Self> { ... }
fn swizzle_dyn_within_blocks_u8x64(
self,
a: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self> { ... }
fn count_ones_u8x64(self, a: u8x64<Self>) -> u8x64<Self> { ... }
fn count_zeros_u8x64(self, a: u8x64<Self>) -> u8x64<Self> { ... }
fn add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn saturating_add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn saturating_sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn mul_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn and_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn or_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn xor_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn not_u8x64(self, a: u8x64<Self>) -> u8x64<Self> { ... }
fn shl_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self> { ... }
fn shlv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn shr_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self> { ... }
fn shrv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn reduce_max_u8x64(self, a: u8x64<Self>) -> u8 { ... }
fn reduce_min_u8x64(self, a: u8x64<Self>) -> u8 { ... }
fn reduce_sum_u8x64(self, a: u8x64<Self>) -> u8 { ... }
fn reduce_product_u8x64(self, a: u8x64<Self>) -> u8 { ... }
fn max_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn min_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn clamp_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
c: u8x64<Self>,
) -> u8x64<Self> { ... }
fn simd_eq_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> { ... }
fn simd_ne_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> { ... }
fn simd_lt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> { ... }
fn simd_le_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> { ... }
fn simd_ge_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> { ... }
fn simd_gt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> { ... }
fn zip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn zip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn unzip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn unzip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> { ... }
fn interleave_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u8x64<Self>, u8x64<Self>) { ... }
fn deinterleave_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u8x64<Self>, u8x64<Self>) { ... }
fn select_u8x64(
self,
a: mask8x64<Self>,
b: u8x64<Self>,
c: u8x64<Self>,
) -> u8x64<Self> { ... }
fn widen_u8x64(self, a: u8x64<Self>) -> (u16x32<Self>, u16x32<Self>) { ... }
fn widening_mul_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u16x32<Self>, u16x32<Self>) { ... }
fn widening_add_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u16x32<Self>, u16x32<Self>) { ... }
fn pairwise_widening_add_u8x64(self, a: u8x64<Self>) -> u16x32<Self> { ... }
fn pairwise_dot_product_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> u16x32<Self> { ... }
fn splat_mask8x64(self, val: bool) -> mask8x64<Self> { ... }
fn from_bitmask_mask8x64(self, bits: u64) -> mask8x64<Self> { ... }
fn to_bitmask_mask8x64(self, a: mask8x64<Self>) -> u64 { ... }
fn and_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
) -> mask8x64<Self> { ... }
fn or_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self> { ... }
fn xor_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
) -> mask8x64<Self> { ... }
fn not_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self> { ... }
fn reverse_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self> { ... }
fn select_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
c: mask8x64<Self>,
) -> mask8x64<Self> { ... }
fn simd_eq_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
) -> mask8x64<Self> { ... }
fn simd_ne_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
) -> mask8x64<Self> { ... }
fn any_true_mask8x64(self, a: mask8x64<Self>) -> bool { ... }
fn all_true_mask8x64(self, a: mask8x64<Self>) -> bool { ... }
fn any_false_mask8x64(self, a: mask8x64<Self>) -> bool { ... }
fn all_false_mask8x64(self, a: mask8x64<Self>) -> bool { ... }
fn widen_mask8x64(
self,
a: mask8x64<Self>,
) -> (mask16x32<Self>, mask16x32<Self>) { ... }
fn abs_i16x32(self, a: i16x32<Self>) -> i16x32<Self> { ... }
fn splat_i16x32(self, val: i16) -> i16x32<Self> { ... }
fn reverse_i16x32(self, a: i16x32<Self>) -> i16x32<Self> { ... }
fn slide_within_blocks_i16x32<const SHIFT: usize>(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i16x32<Self> { ... }
fn swizzle_dyn_within_blocks_i16x32(
self,
a: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self> { ... }
fn swizzle_dyn_i16x32(
self,
a: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self> { ... }
fn swizzle_dyn_precise_i16x32(
self,
a: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self> { ... }
fn concat_swizzle_dyn_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self> { ... }
fn concat_swizzle_dyn_precise_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self> { ... }
fn count_ones_i16x32(self, a: i16x32<Self>) -> i16x32<Self> { ... }
fn count_zeros_i16x32(self, a: i16x32<Self>) -> i16x32<Self> { ... }
fn add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn saturating_add_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i16x32<Self> { ... }
fn sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn saturating_sub_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i16x32<Self> { ... }
fn mul_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn and_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn or_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn xor_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn not_i16x32(self, a: i16x32<Self>) -> i16x32<Self> { ... }
fn shl_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self> { ... }
fn shlv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn shr_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self> { ... }
fn shrv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn reduce_max_i16x32(self, a: i16x32<Self>) -> i16 { ... }
fn reduce_min_i16x32(self, a: i16x32<Self>) -> i16 { ... }
fn reduce_sum_i16x32(self, a: i16x32<Self>) -> i16 { ... }
fn reduce_product_i16x32(self, a: i16x32<Self>) -> i16 { ... }
fn max_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn min_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn clamp_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
c: i16x32<Self>,
) -> i16x32<Self> { ... }
fn simd_eq_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> { ... }
fn simd_ne_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> { ... }
fn simd_lt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> { ... }
fn simd_le_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> { ... }
fn simd_ge_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> { ... }
fn simd_gt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> { ... }
fn zip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn zip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn unzip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn unzip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> { ... }
fn interleave_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i16x32<Self>, i16x32<Self>) { ... }
fn deinterleave_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i16x32<Self>, i16x32<Self>) { ... }
fn select_i16x32(
self,
a: mask16x32<Self>,
b: i16x32<Self>,
c: i16x32<Self>,
) -> i16x32<Self> { ... }
fn neg_i16x32(self, a: i16x32<Self>) -> i16x32<Self> { ... }
fn widen_i16x32(self, a: i16x32<Self>) -> (i32x16<Self>, i32x16<Self>) { ... }
fn widening_mul_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i32x16<Self>, i32x16<Self>) { ... }
fn widening_add_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i32x16<Self>, i32x16<Self>) { ... }
fn pairwise_widening_add_i16x32(self, a: i16x32<Self>) -> i32x16<Self> { ... }
fn pairwise_dot_product_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i32x16<Self> { ... }
fn narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self> { ... }
fn saturating_narrow_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i8x64<Self> { ... }
fn relaxed_narrow_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i8x64<Self> { ... }
fn abs_u16x32(self, a: u16x32<Self>) -> u16x32<Self> { ... }
fn splat_u16x32(self, val: u16) -> u16x32<Self> { ... }
fn reverse_u16x32(self, a: u16x32<Self>) -> u16x32<Self> { ... }
fn slide_within_blocks_u16x32<const SHIFT: usize>(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u16x32<Self> { ... }
fn swizzle_dyn_within_blocks_u16x32(
self,
a: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self> { ... }
fn swizzle_dyn_u16x32(
self,
a: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self> { ... }
fn swizzle_dyn_precise_u16x32(
self,
a: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self> { ... }
fn concat_swizzle_dyn_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self> { ... }
fn concat_swizzle_dyn_precise_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self> { ... }
fn count_ones_u16x32(self, a: u16x32<Self>) -> u16x32<Self> { ... }
fn count_zeros_u16x32(self, a: u16x32<Self>) -> u16x32<Self> { ... }
fn add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn saturating_add_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u16x32<Self> { ... }
fn sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn saturating_sub_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u16x32<Self> { ... }
fn mul_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn and_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn or_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn xor_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn not_u16x32(self, a: u16x32<Self>) -> u16x32<Self> { ... }
fn shl_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self> { ... }
fn shlv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn shr_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self> { ... }
fn shrv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn reduce_max_u16x32(self, a: u16x32<Self>) -> u16 { ... }
fn reduce_min_u16x32(self, a: u16x32<Self>) -> u16 { ... }
fn reduce_sum_u16x32(self, a: u16x32<Self>) -> u16 { ... }
fn reduce_product_u16x32(self, a: u16x32<Self>) -> u16 { ... }
fn max_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn min_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn clamp_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
c: u16x32<Self>,
) -> u16x32<Self> { ... }
fn simd_eq_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> { ... }
fn simd_ne_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> { ... }
fn simd_lt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> { ... }
fn simd_le_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> { ... }
fn simd_ge_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> { ... }
fn simd_gt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> { ... }
fn zip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn zip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn unzip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn unzip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> { ... }
fn interleave_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u16x32<Self>, u16x32<Self>) { ... }
fn deinterleave_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u16x32<Self>, u16x32<Self>) { ... }
fn select_u16x32(
self,
a: mask16x32<Self>,
b: u16x32<Self>,
c: u16x32<Self>,
) -> u16x32<Self> { ... }
fn widen_u16x32(self, a: u16x32<Self>) -> (u32x16<Self>, u32x16<Self>) { ... }
fn widening_mul_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u32x16<Self>, u32x16<Self>) { ... }
fn widening_add_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u32x16<Self>, u32x16<Self>) { ... }
fn pairwise_widening_add_u16x32(self, a: u16x32<Self>) -> u32x16<Self> { ... }
fn pairwise_dot_product_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u32x16<Self> { ... }
fn narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self> { ... }
fn saturating_narrow_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u8x64<Self> { ... }
fn relaxed_narrow_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u8x64<Self> { ... }
fn splat_mask16x32(self, val: bool) -> mask16x32<Self> { ... }
fn from_bitmask_mask16x32(self, bits: u64) -> mask16x32<Self> { ... }
fn to_bitmask_mask16x32(self, a: mask16x32<Self>) -> u64 { ... }
fn and_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self> { ... }
fn or_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self> { ... }
fn xor_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self> { ... }
fn not_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self> { ... }
fn reverse_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self> { ... }
fn select_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
c: mask16x32<Self>,
) -> mask16x32<Self> { ... }
fn simd_eq_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self> { ... }
fn simd_ne_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self> { ... }
fn any_true_mask16x32(self, a: mask16x32<Self>) -> bool { ... }
fn all_true_mask16x32(self, a: mask16x32<Self>) -> bool { ... }
fn any_false_mask16x32(self, a: mask16x32<Self>) -> bool { ... }
fn all_false_mask16x32(self, a: mask16x32<Self>) -> bool { ... }
fn widen_mask16x32(
self,
a: mask16x32<Self>,
) -> (mask32x16<Self>, mask32x16<Self>) { ... }
fn narrow_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask8x64<Self> { ... }
fn abs_i32x16(self, a: i32x16<Self>) -> i32x16<Self> { ... }
fn splat_i32x16(self, val: i32) -> i32x16<Self> { ... }
fn reverse_i32x16(self, a: i32x16<Self>) -> i32x16<Self> { ... }
fn slide_within_blocks_i32x16<const SHIFT: usize>(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i32x16<Self> { ... }
fn swizzle_dyn_within_blocks_i32x16(
self,
a: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self> { ... }
fn swizzle_dyn_i32x16(
self,
a: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self> { ... }
fn swizzle_dyn_precise_i32x16(
self,
a: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self> { ... }
fn concat_swizzle_dyn_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self> { ... }
fn concat_swizzle_dyn_precise_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self> { ... }
fn count_ones_i32x16(self, a: i32x16<Self>) -> i32x16<Self> { ... }
fn count_zeros_i32x16(self, a: i32x16<Self>) -> i32x16<Self> { ... }
fn add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn saturating_add_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i32x16<Self> { ... }
fn sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn saturating_sub_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i32x16<Self> { ... }
fn mul_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn and_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn or_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn xor_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn not_i32x16(self, a: i32x16<Self>) -> i32x16<Self> { ... }
fn shl_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self> { ... }
fn shlv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn shr_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self> { ... }
fn shrv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn reduce_max_i32x16(self, a: i32x16<Self>) -> i32 { ... }
fn reduce_min_i32x16(self, a: i32x16<Self>) -> i32 { ... }
fn reduce_sum_i32x16(self, a: i32x16<Self>) -> i32 { ... }
fn reduce_product_i32x16(self, a: i32x16<Self>) -> i32 { ... }
fn max_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn min_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn clamp_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
c: i32x16<Self>,
) -> i32x16<Self> { ... }
fn simd_eq_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> { ... }
fn simd_ne_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> { ... }
fn simd_lt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> { ... }
fn simd_le_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> { ... }
fn simd_ge_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> { ... }
fn simd_gt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> { ... }
fn zip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn zip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn unzip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn unzip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> { ... }
fn interleave_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i32x16<Self>, i32x16<Self>) { ... }
fn deinterleave_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i32x16<Self>, i32x16<Self>) { ... }
fn select_i32x16(
self,
a: mask32x16<Self>,
b: i32x16<Self>,
c: i32x16<Self>,
) -> i32x16<Self> { ... }
fn neg_i32x16(self, a: i32x16<Self>) -> i32x16<Self> { ... }
fn widen_i32x16(self, a: i32x16<Self>) -> (i64x8<Self>, i64x8<Self>) { ... }
fn widening_mul_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i64x8<Self>, i64x8<Self>) { ... }
fn widening_add_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i64x8<Self>, i64x8<Self>) { ... }
fn pairwise_widening_add_i32x16(self, a: i32x16<Self>) -> i64x8<Self> { ... }
fn pairwise_dot_product_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i64x8<Self> { ... }
fn narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self> { ... }
fn saturating_narrow_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i16x32<Self> { ... }
fn relaxed_narrow_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i16x32<Self> { ... }
fn cvt_f32_i32x16(self, a: i32x16<Self>) -> f32x16<Self> { ... }
fn abs_u32x16(self, a: u32x16<Self>) -> u32x16<Self> { ... }
fn splat_u32x16(self, val: u32) -> u32x16<Self> { ... }
fn reverse_u32x16(self, a: u32x16<Self>) -> u32x16<Self> { ... }
fn slide_within_blocks_u32x16<const SHIFT: usize>(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u32x16<Self> { ... }
fn swizzle_dyn_within_blocks_u32x16(
self,
a: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self> { ... }
fn swizzle_dyn_u32x16(
self,
a: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self> { ... }
fn swizzle_dyn_precise_u32x16(
self,
a: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self> { ... }
fn concat_swizzle_dyn_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self> { ... }
fn concat_swizzle_dyn_precise_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self> { ... }
fn count_ones_u32x16(self, a: u32x16<Self>) -> u32x16<Self> { ... }
fn count_zeros_u32x16(self, a: u32x16<Self>) -> u32x16<Self> { ... }
fn add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn saturating_add_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u32x16<Self> { ... }
fn sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn saturating_sub_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u32x16<Self> { ... }
fn mul_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn and_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn or_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn xor_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn not_u32x16(self, a: u32x16<Self>) -> u32x16<Self> { ... }
fn shl_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self> { ... }
fn shlv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn shr_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self> { ... }
fn shrv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn reduce_max_u32x16(self, a: u32x16<Self>) -> u32 { ... }
fn reduce_min_u32x16(self, a: u32x16<Self>) -> u32 { ... }
fn reduce_sum_u32x16(self, a: u32x16<Self>) -> u32 { ... }
fn reduce_product_u32x16(self, a: u32x16<Self>) -> u32 { ... }
fn max_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn min_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn clamp_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
c: u32x16<Self>,
) -> u32x16<Self> { ... }
fn simd_eq_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> { ... }
fn simd_ne_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> { ... }
fn simd_lt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> { ... }
fn simd_le_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> { ... }
fn simd_ge_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> { ... }
fn simd_gt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> { ... }
fn zip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn zip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn unzip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn unzip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> { ... }
fn interleave_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u32x16<Self>, u32x16<Self>) { ... }
fn deinterleave_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u32x16<Self>, u32x16<Self>) { ... }
fn select_u32x16(
self,
a: mask32x16<Self>,
b: u32x16<Self>,
c: u32x16<Self>,
) -> u32x16<Self> { ... }
fn widen_u32x16(self, a: u32x16<Self>) -> (u64x8<Self>, u64x8<Self>) { ... }
fn widening_mul_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u64x8<Self>, u64x8<Self>) { ... }
fn widening_add_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u64x8<Self>, u64x8<Self>) { ... }
fn pairwise_widening_add_u32x16(self, a: u32x16<Self>) -> u64x8<Self> { ... }
fn pairwise_dot_product_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u64x8<Self> { ... }
fn narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self> { ... }
fn saturating_narrow_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u16x32<Self> { ... }
fn relaxed_narrow_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u16x32<Self> { ... }
fn cvt_f32_u32x16(self, a: u32x16<Self>) -> f32x16<Self> { ... }
fn splat_mask32x16(self, val: bool) -> mask32x16<Self> { ... }
fn from_bitmask_mask32x16(self, bits: u64) -> mask32x16<Self> { ... }
fn to_bitmask_mask32x16(self, a: mask32x16<Self>) -> u64 { ... }
fn and_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self> { ... }
fn or_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self> { ... }
fn xor_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self> { ... }
fn not_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self> { ... }
fn reverse_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self> { ... }
fn select_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
c: mask32x16<Self>,
) -> mask32x16<Self> { ... }
fn simd_eq_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self> { ... }
fn simd_ne_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self> { ... }
fn any_true_mask32x16(self, a: mask32x16<Self>) -> bool { ... }
fn all_true_mask32x16(self, a: mask32x16<Self>) -> bool { ... }
fn any_false_mask32x16(self, a: mask32x16<Self>) -> bool { ... }
fn all_false_mask32x16(self, a: mask32x16<Self>) -> bool { ... }
fn widen_mask32x16(
self,
a: mask32x16<Self>,
) -> (mask64x8<Self>, mask64x8<Self>) { ... }
fn narrow_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask16x32<Self> { ... }
fn abs_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn splat_f64x8(self, val: f64) -> f64x8<Self> { ... }
fn reverse_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn slide_within_blocks_f64x8<const SHIFT: usize>(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> f64x8<Self> { ... }
fn swizzle_dyn_within_blocks_f64x8(
self,
a: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self> { ... }
fn swizzle_dyn_f64x8(
self,
a: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self> { ... }
fn swizzle_dyn_precise_f64x8(
self,
a: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self> { ... }
fn concat_swizzle_dyn_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self> { ... }
fn concat_swizzle_dyn_precise_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self> { ... }
fn neg_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn sqrt_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn approximate_recip_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn add_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn sub_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn mul_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn div_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn copysign_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn reduce_max_f64x8(self, a: f64x8<Self>) -> f64 { ... }
fn reduce_min_f64x8(self, a: f64x8<Self>) -> f64 { ... }
fn reduce_max_precise_f64x8(self, a: f64x8<Self>) -> f64 { ... }
fn reduce_min_precise_f64x8(self, a: f64x8<Self>) -> f64 { ... }
fn reduce_sum_f64x8(self, a: f64x8<Self>) -> f64 { ... }
fn reduce_product_f64x8(self, a: f64x8<Self>) -> f64 { ... }
fn max_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn min_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn max_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn min_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn clamp_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self> { ... }
fn simd_eq_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> { ... }
fn simd_ne_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> { ... }
fn simd_lt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> { ... }
fn simd_le_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> { ... }
fn simd_ge_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> { ... }
fn simd_gt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> { ... }
fn zip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn zip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn unzip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn unzip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> { ... }
fn interleave_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> (f64x8<Self>, f64x8<Self>) { ... }
fn deinterleave_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> (f64x8<Self>, f64x8<Self>) { ... }
fn mul_add_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self> { ... }
fn mul_add_precise_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self> { ... }
fn mul_sub_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self> { ... }
fn mul_sub_precise_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self> { ... }
fn floor_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn ceil_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn round_ties_even_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn round_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn fract_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn trunc_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn to_degrees_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn to_radians_f64x8(self, a: f64x8<Self>) -> f64x8<Self> { ... }
fn select_f64x8(
self,
a: mask64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self> { ... }
fn narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self> { ... }
fn saturating_narrow_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> f32x16<Self> { ... }
fn relaxed_narrow_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> f32x16<Self> { ... }
fn cvt_u64_f64x8(self, a: f64x8<Self>) -> u64x8<Self> { ... }
fn cvt_u64_precise_f64x8(self, a: f64x8<Self>) -> u64x8<Self> { ... }
fn cvt_i64_f64x8(self, a: f64x8<Self>) -> i64x8<Self> { ... }
fn cvt_i64_precise_f64x8(self, a: f64x8<Self>) -> i64x8<Self> { ... }
fn abs_i64x8(self, a: i64x8<Self>) -> i64x8<Self> { ... }
fn splat_i64x8(self, val: i64) -> i64x8<Self> { ... }
fn reverse_i64x8(self, a: i64x8<Self>) -> i64x8<Self> { ... }
fn slide_within_blocks_i64x8<const SHIFT: usize>(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> i64x8<Self> { ... }
fn swizzle_dyn_within_blocks_i64x8(
self,
a: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self> { ... }
fn swizzle_dyn_i64x8(
self,
a: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self> { ... }
fn swizzle_dyn_precise_i64x8(
self,
a: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self> { ... }
fn concat_swizzle_dyn_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self> { ... }
fn concat_swizzle_dyn_precise_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self> { ... }
fn count_ones_i64x8(self, a: i64x8<Self>) -> i64x8<Self> { ... }
fn count_zeros_i64x8(self, a: i64x8<Self>) -> i64x8<Self> { ... }
fn add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn saturating_add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn saturating_sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn mul_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn and_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn or_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn xor_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn not_i64x8(self, a: i64x8<Self>) -> i64x8<Self> { ... }
fn shl_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self> { ... }
fn shlv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn shr_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self> { ... }
fn shrv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn reduce_max_i64x8(self, a: i64x8<Self>) -> i64 { ... }
fn reduce_min_i64x8(self, a: i64x8<Self>) -> i64 { ... }
fn reduce_sum_i64x8(self, a: i64x8<Self>) -> i64 { ... }
fn reduce_product_i64x8(self, a: i64x8<Self>) -> i64 { ... }
fn max_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn min_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn clamp_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
c: i64x8<Self>,
) -> i64x8<Self> { ... }
fn simd_eq_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> { ... }
fn simd_ne_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> { ... }
fn simd_lt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> { ... }
fn simd_le_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> { ... }
fn simd_ge_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> { ... }
fn simd_gt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> { ... }
fn zip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn zip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn unzip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn unzip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> { ... }
fn interleave_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> (i64x8<Self>, i64x8<Self>) { ... }
fn deinterleave_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> (i64x8<Self>, i64x8<Self>) { ... }
fn select_i64x8(
self,
a: mask64x8<Self>,
b: i64x8<Self>,
c: i64x8<Self>,
) -> i64x8<Self> { ... }
fn neg_i64x8(self, a: i64x8<Self>) -> i64x8<Self> { ... }
fn narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self> { ... }
fn saturating_narrow_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> i32x16<Self> { ... }
fn relaxed_narrow_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> i32x16<Self> { ... }
fn cvt_f64_i64x8(self, a: i64x8<Self>) -> f64x8<Self> { ... }
fn abs_u64x8(self, a: u64x8<Self>) -> u64x8<Self> { ... }
fn splat_u64x8(self, val: u64) -> u64x8<Self> { ... }
fn reverse_u64x8(self, a: u64x8<Self>) -> u64x8<Self> { ... }
fn slide_within_blocks_u64x8<const SHIFT: usize>(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> u64x8<Self> { ... }
fn swizzle_dyn_within_blocks_u64x8(
self,
a: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self> { ... }
fn swizzle_dyn_u64x8(
self,
a: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self> { ... }
fn swizzle_dyn_precise_u64x8(
self,
a: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self> { ... }
fn concat_swizzle_dyn_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self> { ... }
fn concat_swizzle_dyn_precise_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self> { ... }
fn count_ones_u64x8(self, a: u64x8<Self>) -> u64x8<Self> { ... }
fn count_zeros_u64x8(self, a: u64x8<Self>) -> u64x8<Self> { ... }
fn add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn saturating_add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn saturating_sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn mul_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn and_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn or_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn xor_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn not_u64x8(self, a: u64x8<Self>) -> u64x8<Self> { ... }
fn shl_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self> { ... }
fn shlv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn shr_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self> { ... }
fn shrv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn reduce_max_u64x8(self, a: u64x8<Self>) -> u64 { ... }
fn reduce_min_u64x8(self, a: u64x8<Self>) -> u64 { ... }
fn reduce_sum_u64x8(self, a: u64x8<Self>) -> u64 { ... }
fn reduce_product_u64x8(self, a: u64x8<Self>) -> u64 { ... }
fn max_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn min_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn clamp_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
c: u64x8<Self>,
) -> u64x8<Self> { ... }
fn simd_eq_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> { ... }
fn simd_ne_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> { ... }
fn simd_lt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> { ... }
fn simd_le_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> { ... }
fn simd_ge_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> { ... }
fn simd_gt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> { ... }
fn zip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn zip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn unzip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn unzip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> { ... }
fn interleave_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> (u64x8<Self>, u64x8<Self>) { ... }
fn deinterleave_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> (u64x8<Self>, u64x8<Self>) { ... }
fn select_u64x8(
self,
a: mask64x8<Self>,
b: u64x8<Self>,
c: u64x8<Self>,
) -> u64x8<Self> { ... }
fn narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self> { ... }
fn saturating_narrow_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> u32x16<Self> { ... }
fn relaxed_narrow_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> u32x16<Self> { ... }
fn cvt_f64_u64x8(self, a: u64x8<Self>) -> f64x8<Self> { ... }
fn splat_mask64x8(self, val: bool) -> mask64x8<Self> { ... }
fn from_bitmask_mask64x8(self, bits: u64) -> mask64x8<Self> { ... }
fn to_bitmask_mask64x8(self, a: mask64x8<Self>) -> u64 { ... }
fn and_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask64x8<Self> { ... }
fn or_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self> { ... }
fn xor_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask64x8<Self> { ... }
fn not_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self> { ... }
fn reverse_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self> { ... }
fn select_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
c: mask64x8<Self>,
) -> mask64x8<Self> { ... }
fn simd_eq_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask64x8<Self> { ... }
fn simd_ne_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask64x8<Self> { ... }
fn any_true_mask64x8(self, a: mask64x8<Self>) -> bool { ... }
fn all_true_mask64x8(self, a: mask64x8<Self>) -> bool { ... }
fn any_false_mask64x8(self, a: mask64x8<Self>) -> bool { ... }
fn all_false_mask64x8(self, a: mask64x8<Self>) -> bool { ... }
fn narrow_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask32x16<Self> { ... }
}Expand description
The main SIMD trait, implemented by all SIMD token types.
Each implementor of this trait (e.g. Avx2, Sse4_2, Sse2, Neon, Fallback) is a zero-sized “token” type
representing a specific SIMD instruction set. These tokens are obtained at runtime via Level and the
dispatch! macro, which selects the best available backend for the current CPU.
This trait defines all the low-level SIMD operations (e.g. add_f32x4,
mul_u32x4) that are implemented by each token type using platform-specific intrinsics.
However, you typically won’t call these methods directly. Instead, you’ll probably be using the methods
defined on the vector types themselves, such as f32x4 or u32x4.
§Associated Types
The trait defines associated types for the highest “native” vector width of each scalar type (e.g. f32s,
u32s). These are always at least 128 bits, but may be larger. Currently, they are 128 bits on the
fallback, NEON, WASM, SSE2, and SSE4.2 backends, 256 bits on AVX2, and 512 bits on AVX-512.
§Example
#[inline(always)]
fn add_vectors<S: Simd>(simd: S, a: f32x4<S>, b: f32x4<S>) -> f32x4<S> {
a + b // Uses operator overloading, which calls simd.add_f32x4 internally
}
let level = Level::new();
dispatch!(level, simd => {
let a = [1.0, 2.0, 3.0, 4.0].simd_into(simd);
let b = [5.0, 6.0, 7.0, 8.0].simd_into(simd);
let result = add_vectors(simd, a, b);
});Required Associated Types§
Sourcetype f32s: SimdFloat<Self, Element = f32, Block = f32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtFloat<Self::u32s> + SimdCvtFloat<Self::i32s> + SimdWiden<Self, Widened = Self::f64s>
type f32s: SimdFloat<Self, Element = f32, Block = f32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtFloat<Self::u32s> + SimdCvtFloat<Self::i32s> + SimdWiden<Self, Widened = Self::f64s>
A native-width SIMD vector of f32s.
Sourcetype f64s: SimdFloat<Self, Element = f64, Block = f64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtFloat<Self::u64s> + SimdCvtFloat<Self::i64s> + SimdNarrow<Self, Narrowed = Self::f32s>
type f64s: SimdFloat<Self, Element = f64, Block = f64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtFloat<Self::u64s> + SimdCvtFloat<Self::i64s> + SimdNarrow<Self, Narrowed = Self::f32s>
A native-width SIMD vector of f64s.
Sourcetype u8s: SimdInt<Self, Element = u8, Block = u8x16<Self>, Mask = Self::mask8s, ByteVector = Self::u8s> + SimdIntWiden<Self, Widened = Self::u16s>
type u8s: SimdInt<Self, Element = u8, Block = u8x16<Self>, Mask = Self::mask8s, ByteVector = Self::u8s> + SimdIntWiden<Self, Widened = Self::u16s>
A native-width SIMD vector of u8s.
Sourcetype i8s: SimdInt<Self, Element = i8, Block = i8x16<Self>, Mask = Self::mask8s, ByteVector = Self::u8s> + SimdIntWiden<Self, Widened = Self::i16s> + Neg<Output = Self::i8s>
type i8s: SimdInt<Self, Element = i8, Block = i8x16<Self>, Mask = Self::mask8s, ByteVector = Self::u8s> + SimdIntWiden<Self, Widened = Self::i16s> + Neg<Output = Self::i8s>
A native-width SIMD vector of i8s.
Sourcetype u16s: SimdInt<Self, Element = u16, Block = u16x8<Self>, Mask = Self::mask16s, ByteVector = Self::u8s> + SimdNarrow<Self, Narrowed = Self::u8s> + SimdIntWiden<Self, Widened = Self::u32s>
type u16s: SimdInt<Self, Element = u16, Block = u16x8<Self>, Mask = Self::mask16s, ByteVector = Self::u8s> + SimdNarrow<Self, Narrowed = Self::u8s> + SimdIntWiden<Self, Widened = Self::u32s>
A native-width SIMD vector of u16s.
Sourcetype i16s: SimdInt<Self, Element = i16, Block = i16x8<Self>, Mask = Self::mask16s, ByteVector = Self::u8s> + SimdNarrow<Self, Narrowed = Self::i8s> + SimdIntWiden<Self, Widened = Self::i32s> + Neg<Output = Self::i16s>
type i16s: SimdInt<Self, Element = i16, Block = i16x8<Self>, Mask = Self::mask16s, ByteVector = Self::u8s> + SimdNarrow<Self, Narrowed = Self::i8s> + SimdIntWiden<Self, Widened = Self::i32s> + Neg<Output = Self::i16s>
A native-width SIMD vector of i16s.
Sourcetype u32s: SimdInt<Self, Element = u32, Block = u32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f32s> + SimdNarrow<Self, Narrowed = Self::u16s> + SimdIntWiden<Self, Widened = Self::u64s>
type u32s: SimdInt<Self, Element = u32, Block = u32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f32s> + SimdNarrow<Self, Narrowed = Self::u16s> + SimdIntWiden<Self, Widened = Self::u64s>
A native-width SIMD vector of u32s.
Sourcetype i32s: SimdInt<Self, Element = i32, Block = i32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f32s> + SimdNarrow<Self, Narrowed = Self::i16s> + SimdIntWiden<Self, Widened = Self::i64s> + Neg<Output = Self::i32s>
type i32s: SimdInt<Self, Element = i32, Block = i32x4<Self>, Mask = Self::mask32s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f32s> + SimdNarrow<Self, Narrowed = Self::i16s> + SimdIntWiden<Self, Widened = Self::i64s> + Neg<Output = Self::i32s>
A native-width SIMD vector of i32s.
Sourcetype u64s: SimdInt<Self, Element = u64, Block = u64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f64s> + SimdNarrow<Self, Narrowed = Self::u32s>
type u64s: SimdInt<Self, Element = u64, Block = u64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f64s> + SimdNarrow<Self, Narrowed = Self::u32s>
A native-width SIMD vector of u64s.
Sourcetype i64s: SimdInt<Self, Element = i64, Block = i64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f64s> + SimdNarrow<Self, Narrowed = Self::i32s> + Neg<Output = Self::i64s>
type i64s: SimdInt<Self, Element = i64, Block = i64x2<Self>, Mask = Self::mask64s, ByteVector = Self::u8s> + SimdCvtTruncate<Self::f64s> + SimdNarrow<Self, Narrowed = Self::i32s> + Neg<Output = Self::i64s>
A native-width SIMD vector of i64s.
Sourcetype mask8s: SimdMask<Self, Element = i8, Ints = Self::i8s> + Select<Self::u8s> + Select<Self::i8s> + Select<Self::mask8s> + MaskWiden<Self, Widened = Self::mask16s>
type mask8s: SimdMask<Self, Element = i8, Ints = Self::i8s> + Select<Self::u8s> + Select<Self::i8s> + Select<Self::mask8s> + MaskWiden<Self, Widened = Self::mask16s>
A native-width SIMD mask with 8-bit lanes.
Sourcetype mask16s: SimdMask<Self, Element = i16, Ints = Self::i16s> + Select<Self::u16s> + Select<Self::i16s> + Select<Self::mask16s> + MaskNarrow<Self, Narrowed = Self::mask8s> + MaskWiden<Self, Widened = Self::mask32s>
type mask16s: SimdMask<Self, Element = i16, Ints = Self::i16s> + Select<Self::u16s> + Select<Self::i16s> + Select<Self::mask16s> + MaskNarrow<Self, Narrowed = Self::mask8s> + MaskWiden<Self, Widened = Self::mask32s>
A native-width SIMD mask with 16-bit lanes.
Required Methods§
Sourcefn vectorize<F: FnOnce() -> R, R>(self, f: F) -> R
fn vectorize<F: FnOnce() -> R, R>(self, f: F) -> R
Call a closure with the instructions for this SIMD level enabled.
vectorize() establishes the correct #[target_feature] context. The provided
closure should be #[inline(always)] so that its body is incorporated into that
context and can use all instructions supported by this SIMD level.
The small wrappers used by vectorize() are eligible for inlining when the caller
has a compatible target-feature context. A function containing the call does not
itself need an #[inline(always)] annotation; a target-feature boundary is retained
whenever one is required.
The #[simd]
attribute from the separate fearless_simd_macros crate establishes this context
automatically, passing ordinary function arguments separately to reduce capture
overhead. Calling vectorize() manually avoids the procedural-macro dependency.
§Example
double_u32s does not need to be marked #[inline(always)]; only the closure passed
to vectorize() does.
use fearless_simd::{dispatch, prelude::*, Level};
fn double_u32s<S: Simd>(simd: S, values: &mut [u32]) {
simd.vectorize(
#[inline(always)]
|| {
let mut chunks = values.chunks_exact_mut(S::u32s::LEN);
for chunk in &mut chunks {
let value = S::u32s::from_slice(simd, chunk);
(value * 2).store_slice(chunk);
}
for value in chunks.into_remainder() {
*value *= 2;
}
},
);
}
let mut values = [1, 2, 3, 4, 5];
let level = Level::new();
dispatch!(level, simd => double_u32s(simd, &mut values));
assert_eq!(values, [2, 4, 6, 8, 10]);Sourcefn abs_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn abs_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_f32x4(self, val: f32) -> f32x4<Self>
fn splat_f32x4(self, val: f32) -> f32x4<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn reverse_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_f32x4<const SHIFT: usize>(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> f32x4<Self>
fn slide_f32x4<const SHIFT: usize>( self, a: f32x4<Self>, b: f32x4<Self>, ) -> f32x4<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
) -> f32x4<Self>
fn compress_f32x4( self, values: f32x4<Self>, mask: mask32x4<Self>, ) -> f32x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
merge: f32x4<Self>,
) -> f32x4<Self>
fn compress_merge_f32x4( self, values: f32x4<Self>, mask: mask32x4<Self>, merge: f32x4<Self>, ) -> f32x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_f32x4(self, values: f32x4<Self>, mask: mask32x4<Self>) -> f32x4<Self>
fn expand_f32x4(self, values: f32x4<Self>, mask: mask32x4<Self>) -> f32x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_f32x4(
self,
values: f32x4<Self>,
mask: mask32x4<Self>,
merge: f32x4<Self>,
) -> f32x4<Self>
fn expand_merge_f32x4( self, values: f32x4<Self>, mask: mask32x4<Self>, merge: f32x4<Self>, ) -> f32x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn sqrt_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn sqrt_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Compute the square root of each element.
Negative elements other than -0.0 will become NaN.
Sourcefn approximate_recip_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn approximate_recip_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Compute an approximate reciprocal (1. / x) for each element.
This uses a fast hardware estimate where available, and falls back to exact division otherwise.
On x86 for f32, this has a relative error less than 1.5 × 2^-12. On AArch64 (f32 and f64), this has a relative error less than 2^-8. The precision of this operation may change as new platform support is added.
Sourcefn add_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn add_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Add two vectors element-wise.
Sourcefn sub_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn sub_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Subtract two vectors element-wise.
Sourcefn mul_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn mul_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Multiply two vectors element-wise.
Sourcefn div_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn div_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Divide two vectors element-wise.
Sourcefn copysign_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn copysign_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Return a vector with the magnitude of a and the sign of b for each element.
This operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit.
Sourcefn reduce_max_f32x4(self, a: f32x4<Self>) -> f32
fn reduce_max_f32x4(self, a: f32x4<Self>) -> f32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_f32x4(self, a: f32x4<Self>) -> f32
fn reduce_min_f32x4(self, a: f32x4<Self>) -> f32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_max_precise_f32x4(self, a: f32x4<Self>) -> f32
fn reduce_max_precise_f32x4(self, a: f32x4<Self>) -> f32
Return the maximum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_max.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_min_precise_f32x4(self, a: f32x4<Self>) -> f32
fn reduce_min_precise_f32x4(self, a: f32x4<Self>) -> f32
Return the minimum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_min.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_sum_f32x4(self, a: f32x4<Self>) -> f32
fn reduce_sum_f32x4(self, a: f32x4<Self>) -> f32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_f32x4(self, a: f32x4<Self>) -> f32
fn reduce_product_f32x4(self, a: f32x4<Self>) -> f32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn max_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn min_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn max_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn max_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Return the element-wise maximum of two vectors.
For integer vectors, this operation is the same as max.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn min_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn min_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Return the element-wise minimum of two vectors.
For integer vectors, this operation is the same as min.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn clamp_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>
fn clamp_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>, ) -> f32x4<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
fn simd_eq_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
fn simd_lt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
fn simd_le_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn zip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn zip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn unzip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
fn unzip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> (f32x4<Self>, f32x4<Self>)
fn interleave_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, ) -> (f32x4<Self>, f32x4<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> (f32x4<Self>, f32x4<Self>)
fn deinterleave_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, ) -> (f32x4<Self>, f32x4<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn mul_add_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>
fn mul_add_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>, ) -> f32x4<Self>
Compute (a * b) + c (fused multiply-add) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors.
Sourcefn mul_add_precise_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>
fn mul_add_precise_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>, ) -> f32x4<Self>
Compute (a * b) + c for each element, with a single rounding at the end.
The result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than mul_add on platforms without fused multiply-add instructions, including WebAssembly.
§Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn mul_sub_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>
fn mul_sub_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>, ) -> f32x4<Self>
Compute (a * b) - c (fused multiply-subtract) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors.
Sourcefn mul_sub_precise_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>
fn mul_sub_precise_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>, ) -> f32x4<Self>
Compute (a * b) - c for each element, with a single rounding at the end.
The result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than mul_sub on platforms without fused multiply-add instructions, including WebAssembly.
# Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn floor_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn floor_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Return the largest integer less than or equal to each element, that is, round towards negative infinity.
Sourcefn ceil_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn ceil_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Return the smallest integer greater than or equal to each element, that is, round towards positive infinity.
Sourcefn round_ties_even_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn round_ties_even_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Round each element to the nearest integer, with ties rounding to the nearest even integer.
Sourcefn round_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn round_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Round each element to the nearest integer, with ties rounding away from zero.
§Performance considerations
Only AArch64 has native instructions for this operation. round has to be emulated on all other platforms which is around 2-4x slower than round_ties_even. Prefer using round_ties_even if possible.
Sourcefn fract_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn fract_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Return the fractional part of each element.
This is equivalent to a - a.trunc().
Sourcefn trunc_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn trunc_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Return the integer part of each element, rounding towards zero.
Sourcefn to_degrees_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn to_degrees_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Converts radians to degrees.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn to_radians_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
fn to_radians_f32x4(self, a: f32x4<Self>) -> f32x4<Self>
Converts degrees to radians.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn is_nan_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_nan_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements are NaN.
Sourcefn is_infinite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_infinite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements are positive or negative infinite.
Sourcefn is_finite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_finite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements are neither infinite nor NaN.
Sourcefn is_subnormal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_subnormal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements are subnormal.
This classifies the stored bit pattern, even when floating-point operations treat subnormals as zero.
Sourcefn is_normal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_normal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN.
Sourcefn is_sign_positive_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_sign_positive_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements have a positive sign, including +0.0, NaNs with positive sign bit and positive infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_positive for details.
Sourcefn is_sign_negative_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
fn is_sign_negative_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>
Return a mask indicating which elements have a negative sign, including -0.0, NaNs with negative sign bit and negative infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_negative for details.
Sourcefn select_f32x4(
self,
a: mask32x4<Self>,
b: f32x4<Self>,
c: f32x4<Self>,
) -> f32x4<Self>
fn select_f32x4( self, a: mask32x4<Self>, b: f32x4<Self>, c: f32x4<Self>, ) -> f32x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x8<Self>
fn combine_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn load_four_interleaved_f32x4(self, src: &[f32; 16]) -> [f32x4<Self>; 4]
fn load_four_interleaved_f32x4(self, src: &[f32; 16]) -> [f32x4<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_f32x4(
self,
vectors: [f32x4<Self>; 4],
dest: &mut [f32; 16],
)
fn store_four_interleaved_f32x4( self, vectors: [f32x4<Self>; 4], dest: &mut [f32; 16], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_f32x4(self, a: f32x4<Self>) -> (f64x2<Self>, f64x2<Self>)
fn widen_f32x4(self, a: f32x4<Self>) -> (f64x2<Self>, f64x2<Self>)
Widen every f32 lane exactly into two same-width f64 vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn cvt_u32_f32x4(self, a: f32x4<Self>) -> u32x4<Self>
fn cvt_u32_f32x4(self, a: f32x4<Self>) -> u32x4<Self>
Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
On x86 platforms below AVX-512, this operation will still be slower than converting to i32, because there is no native instruction for converting to u32.
If you know your values fit within range of an i32, you should convert to an i32 and cast to your desired datatype afterwards.
Sourcefn cvt_u32_precise_f32x4(self, a: f32x4<Self>) -> u32x4<Self>
fn cvt_u32_precise_f32x4(self, a: f32x4<Self>) -> u32x4<Self>
Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn cvt_i32_f32x4(self, a: f32x4<Self>) -> i32x4<Self>
fn cvt_i32_f32x4(self, a: f32x4<Self>) -> i32x4<Self>
Convert each floating-point element to a signed 32-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_i32_precise_f32x4(self, a: f32x4<Self>) -> i32x4<Self>
fn cvt_i32_precise_f32x4(self, a: f32x4<Self>) -> i32x4<Self>
Convert each floating-point element to a signed 32-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn abs_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
fn abs_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i8x16(self, val: i8) -> i8x16<Self>
fn splat_i8x16(self, val: i8) -> i8x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
fn reverse_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_i8x16<const SHIFT: usize>(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> i8x16<Self>
fn slide_i8x16<const SHIFT: usize>( self, a: i8x16<Self>, b: i8x16<Self>, ) -> i8x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
) -> i8x16<Self>
fn compress_i8x16( self, values: i8x16<Self>, mask: mask8x16<Self>, ) -> i8x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
merge: i8x16<Self>,
) -> i8x16<Self>
fn compress_merge_i8x16( self, values: i8x16<Self>, mask: mask8x16<Self>, merge: i8x16<Self>, ) -> i8x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i8x16(self, values: i8x16<Self>, mask: mask8x16<Self>) -> i8x16<Self>
fn expand_i8x16(self, values: i8x16<Self>, mask: mask8x16<Self>) -> i8x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i8x16(
self,
values: i8x16<Self>,
mask: mask8x16<Self>,
merge: i8x16<Self>,
) -> i8x16<Self>
fn expand_merge_i8x16( self, values: i8x16<Self>, mask: mask8x16<Self>, merge: i8x16<Self>, ) -> i8x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
fn count_ones_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
fn count_zeros_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn saturating_add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn saturating_sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn mul_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn and_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn or_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn xor_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>
fn shl_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn shlv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>
fn shr_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn shrv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i8x16(self, a: i8x16<Self>) -> i8
fn reduce_max_i8x16(self, a: i8x16<Self>) -> i8
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i8x16(self, a: i8x16<Self>) -> i8
fn reduce_min_i8x16(self, a: i8x16<Self>) -> i8
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i8x16(self, a: i8x16<Self>) -> i8
fn reduce_sum_i8x16(self, a: i8x16<Self>) -> i8
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i8x16(self, a: i8x16<Self>) -> i8
fn reduce_product_i8x16(self, a: i8x16<Self>) -> i8
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn max_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn min_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
c: i8x16<Self>,
) -> i8x16<Self>
fn clamp_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, c: i8x16<Self>, ) -> i8x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
fn simd_eq_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
fn simd_lt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
fn simd_le_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn zip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn zip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn unzip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
fn unzip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i8x16<Self>, i8x16<Self>)
fn interleave_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, ) -> (i8x16<Self>, i8x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i8x16<Self>, i8x16<Self>)
fn deinterleave_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, ) -> (i8x16<Self>, i8x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i8x16(
self,
a: mask8x16<Self>,
b: i8x16<Self>,
c: i8x16<Self>,
) -> i8x16<Self>
fn select_i8x16( self, a: mask8x16<Self>, b: i8x16<Self>, c: i8x16<Self>, ) -> i8x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x32<Self>
fn combine_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x32<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn neg_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
fn neg_i8x16(self, a: i8x16<Self>) -> i8x16<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn load_four_interleaved_i8x16(self, src: &[i8; 64]) -> [i8x16<Self>; 4]
fn load_four_interleaved_i8x16(self, src: &[i8; 64]) -> [i8x16<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_i8x16(
self,
vectors: [i8x16<Self>; 4],
dest: &mut [i8; 64],
)
fn store_four_interleaved_i8x16( self, vectors: [i8x16<Self>; 4], dest: &mut [i8; 64], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_i8x16(self, a: i8x16<Self>) -> (i16x8<Self>, i16x8<Self>)
fn widen_i8x16(self, a: i8x16<Self>) -> (i16x8<Self>, i16x8<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i16x8<Self>, i16x8<Self>)
fn widening_mul_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, ) -> (i16x8<Self>, i16x8<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> (i16x8<Self>, i16x8<Self>)
fn widening_add_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, ) -> (i16x8<Self>, i16x8<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i8x16(self, a: i8x16<Self>) -> i16x8<Self>
fn pairwise_widening_add_i8x16(self, a: i8x16<Self>) -> i16x8<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> i16x8<Self>
fn pairwise_dot_product_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, ) -> i16x8<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn splat_u8x16(self, val: u8) -> u8x16<Self>
fn splat_u8x16(self, val: u8) -> u8x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
fn reverse_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_u8x16<const SHIFT: usize>(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> u8x16<Self>
fn slide_u8x16<const SHIFT: usize>( self, a: u8x16<Self>, b: u8x16<Self>, ) -> u8x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn swizzle_dyn_within_blocks_u8x16(
self,
a: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>
fn swizzle_dyn_within_blocks_u8x16( self, a: u8x16<Self>, indices: u8x16<Self>, ) -> u8x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u8x16(self, a: u8x16<Self>, indices: u8x16<Self>) -> u8x16<Self>
fn swizzle_dyn_u8x16(self, a: u8x16<Self>, indices: u8x16<Self>) -> u8x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u8x16(
self,
a: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>
fn swizzle_dyn_precise_u8x16( self, a: u8x16<Self>, indices: u8x16<Self>, ) -> u8x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>
fn concat_swizzle_dyn_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, indices: u8x16<Self>, ) -> u8x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
indices: u8x16<Self>,
) -> u8x16<Self>
fn concat_swizzle_dyn_precise_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, indices: u8x16<Self>, ) -> u8x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn compress_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
) -> u8x16<Self>
fn compress_u8x16( self, values: u8x16<Self>, mask: mask8x16<Self>, ) -> u8x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
merge: u8x16<Self>,
) -> u8x16<Self>
fn compress_merge_u8x16( self, values: u8x16<Self>, mask: mask8x16<Self>, merge: u8x16<Self>, ) -> u8x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u8x16(self, values: u8x16<Self>, mask: mask8x16<Self>) -> u8x16<Self>
fn expand_u8x16(self, values: u8x16<Self>, mask: mask8x16<Self>) -> u8x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u8x16(
self,
values: u8x16<Self>,
mask: mask8x16<Self>,
merge: u8x16<Self>,
) -> u8x16<Self>
fn expand_merge_u8x16( self, values: u8x16<Self>, mask: mask8x16<Self>, merge: u8x16<Self>, ) -> u8x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
fn count_ones_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
fn count_zeros_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn saturating_add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn saturating_sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn mul_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn and_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn or_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn xor_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>
fn shl_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn shlv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>
fn shr_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn shrv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u8x16(self, a: u8x16<Self>) -> u8
fn reduce_max_u8x16(self, a: u8x16<Self>) -> u8
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u8x16(self, a: u8x16<Self>) -> u8
fn reduce_min_u8x16(self, a: u8x16<Self>) -> u8
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u8x16(self, a: u8x16<Self>) -> u8
fn reduce_sum_u8x16(self, a: u8x16<Self>) -> u8
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u8x16(self, a: u8x16<Self>) -> u8
fn reduce_product_u8x16(self, a: u8x16<Self>) -> u8
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn max_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn min_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
c: u8x16<Self>,
) -> u8x16<Self>
fn clamp_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, c: u8x16<Self>, ) -> u8x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
fn simd_eq_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
fn simd_lt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
fn simd_le_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn zip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn zip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn unzip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
fn unzip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u8x16<Self>, u8x16<Self>)
fn interleave_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, ) -> (u8x16<Self>, u8x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u8x16<Self>, u8x16<Self>)
fn deinterleave_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, ) -> (u8x16<Self>, u8x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u8x16(
self,
a: mask8x16<Self>,
b: u8x16<Self>,
c: u8x16<Self>,
) -> u8x16<Self>
fn select_u8x16( self, a: mask8x16<Self>, b: u8x16<Self>, c: u8x16<Self>, ) -> u8x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x32<Self>
fn combine_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x32<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn load_four_interleaved_u8x16(self, src: &[u8; 64]) -> [u8x16<Self>; 4]
fn load_four_interleaved_u8x16(self, src: &[u8; 64]) -> [u8x16<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_u8x16(
self,
vectors: [u8x16<Self>; 4],
dest: &mut [u8; 64],
)
fn store_four_interleaved_u8x16( self, vectors: [u8x16<Self>; 4], dest: &mut [u8; 64], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_u8x16(self, a: u8x16<Self>) -> (u16x8<Self>, u16x8<Self>)
fn widen_u8x16(self, a: u8x16<Self>) -> (u16x8<Self>, u16x8<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u16x8<Self>, u16x8<Self>)
fn widening_mul_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, ) -> (u16x8<Self>, u16x8<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> (u16x8<Self>, u16x8<Self>)
fn widening_add_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, ) -> (u16x8<Self>, u16x8<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u8x16(self, a: u8x16<Self>) -> u16x8<Self>
fn pairwise_widening_add_u8x16(self, a: u8x16<Self>) -> u16x8<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u8x16(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> u16x8<Self>
fn pairwise_dot_product_u8x16( self, a: u8x16<Self>, b: u8x16<Self>, ) -> u16x8<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn splat_mask8x16(self, val: bool) -> mask8x16<Self>
fn splat_mask8x16(self, val: bool) -> mask8x16<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask8x16(self, bits: u64) -> mask8x16<Self>
fn from_bitmask_mask8x16(self, bits: u64) -> mask8x16<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask8x16(self, a: mask8x16<Self>) -> u64
fn to_bitmask_mask8x16(self, a: mask8x16<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn from_vector_mask8x16(self, vector: i8x16<Self>) -> mask8x16<Self>
fn from_vector_mask8x16(self, vector: i8x16<Self>) -> mask8x16<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask8x16(self, a: mask8x16<Self>) -> i8x16<Self>
fn to_vector_mask8x16(self, a: mask8x16<Self>) -> i8x16<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask8x16(self, a: &mut mask8x16<Self>, index: usize, value: bool)
fn set_mask8x16(self, a: &mut mask8x16<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask8x16<const OFFSET: usize>(
self,
a: mask8x16<Self>,
) -> mask8x16<Self>
fn rotate_elements_left_mask8x16<const OFFSET: usize>( self, a: mask8x16<Self>, ) -> mask8x16<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask8x16<const OFFSET: usize>(
self,
a: mask8x16<Self>,
) -> mask8x16<Self>
fn rotate_elements_right_mask8x16<const OFFSET: usize>( self, a: mask8x16<Self>, ) -> mask8x16<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn and_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>
fn and_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>
Compute the logical AND of two masks.
Sourcefn or_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>
fn or_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>
fn xor_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>
fn not_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>
fn reverse_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
c: mask8x16<Self>,
) -> mask8x16<Self>
fn select_mask8x16( self, a: mask8x16<Self>, b: mask8x16<Self>, c: mask8x16<Self>, ) -> mask8x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x16<Self>
fn simd_eq_mask8x16( self, a: mask8x16<Self>, b: mask8x16<Self>, ) -> mask8x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn any_true_mask8x16(self, a: mask8x16<Self>) -> bool
fn any_true_mask8x16(self, a: mask8x16<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask8x16(self, a: mask8x16<Self>) -> bool
fn all_true_mask8x16(self, a: mask8x16<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask8x16(self, a: mask8x16<Self>) -> bool
fn any_false_mask8x16(self, a: mask8x16<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask8x16(self, a: mask8x16<Self>) -> bool
fn all_false_mask8x16(self, a: mask8x16<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn combine_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x32<Self>
fn combine_mask8x16( self, a: mask8x16<Self>, b: mask8x16<Self>, ) -> mask8x32<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn widen_mask8x16(self, a: mask8x16<Self>) -> (mask16x8<Self>, mask16x8<Self>)
fn widen_mask8x16(self, a: mask8x16<Self>) -> (mask16x8<Self>, mask16x8<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
fn abs_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i16x8(self, val: i16) -> i16x8<Self>
fn splat_i16x8(self, val: i16) -> i16x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
fn reverse_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_i16x8<const SHIFT: usize>(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i16x8<Self>
fn slide_i16x8<const SHIFT: usize>( self, a: i16x8<Self>, b: i16x8<Self>, ) -> i16x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
) -> i16x8<Self>
fn compress_i16x8( self, values: i16x8<Self>, mask: mask16x8<Self>, ) -> i16x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
merge: i16x8<Self>,
) -> i16x8<Self>
fn compress_merge_i16x8( self, values: i16x8<Self>, mask: mask16x8<Self>, merge: i16x8<Self>, ) -> i16x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i16x8(self, values: i16x8<Self>, mask: mask16x8<Self>) -> i16x8<Self>
fn expand_i16x8(self, values: i16x8<Self>, mask: mask16x8<Self>) -> i16x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i16x8(
self,
values: i16x8<Self>,
mask: mask16x8<Self>,
merge: i16x8<Self>,
) -> i16x8<Self>
fn expand_merge_i16x8( self, values: i16x8<Self>, mask: mask16x8<Self>, merge: i16x8<Self>, ) -> i16x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
fn count_ones_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
fn count_zeros_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn saturating_add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn saturating_sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn mul_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn and_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn or_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn xor_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>
fn shl_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn shlv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>
fn shr_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn shrv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i16x8(self, a: i16x8<Self>) -> i16
fn reduce_max_i16x8(self, a: i16x8<Self>) -> i16
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i16x8(self, a: i16x8<Self>) -> i16
fn reduce_min_i16x8(self, a: i16x8<Self>) -> i16
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i16x8(self, a: i16x8<Self>) -> i16
fn reduce_sum_i16x8(self, a: i16x8<Self>) -> i16
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i16x8(self, a: i16x8<Self>) -> i16
fn reduce_product_i16x8(self, a: i16x8<Self>) -> i16
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn max_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn min_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
c: i16x8<Self>,
) -> i16x8<Self>
fn clamp_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, c: i16x8<Self>, ) -> i16x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
fn simd_eq_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
fn simd_lt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
fn simd_le_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn zip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn zip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn unzip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
fn unzip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i16x8<Self>, i16x8<Self>)
fn interleave_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, ) -> (i16x8<Self>, i16x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i16x8<Self>, i16x8<Self>)
fn deinterleave_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, ) -> (i16x8<Self>, i16x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i16x8(
self,
a: mask16x8<Self>,
b: i16x8<Self>,
c: i16x8<Self>,
) -> i16x8<Self>
fn select_i16x8( self, a: mask16x8<Self>, b: i16x8<Self>, c: i16x8<Self>, ) -> i16x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x16<Self>
fn combine_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn neg_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
fn neg_i16x8(self, a: i16x8<Self>) -> i16x8<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn load_four_interleaved_i16x8(self, src: &[i16; 32]) -> [i16x8<Self>; 4]
fn load_four_interleaved_i16x8(self, src: &[i16; 32]) -> [i16x8<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_i16x8(
self,
vectors: [i16x8<Self>; 4],
dest: &mut [i16; 32],
)
fn store_four_interleaved_i16x8( self, vectors: [i16x8<Self>; 4], dest: &mut [i16; 32], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_i16x8(self, a: i16x8<Self>) -> (i32x4<Self>, i32x4<Self>)
fn widen_i16x8(self, a: i16x8<Self>) -> (i32x4<Self>, i32x4<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i32x4<Self>, i32x4<Self>)
fn widening_mul_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, ) -> (i32x4<Self>, i32x4<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> (i32x4<Self>, i32x4<Self>)
fn widening_add_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, ) -> (i32x4<Self>, i32x4<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i16x8(self, a: i16x8<Self>) -> i32x4<Self>
fn pairwise_widening_add_i16x8(self, a: i16x8<Self>) -> i32x4<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i32x4<Self>
fn pairwise_dot_product_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, ) -> i32x4<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>
fn narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>
fn saturating_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>
fn relaxed_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn splat_u16x8(self, val: u16) -> u16x8<Self>
fn splat_u16x8(self, val: u16) -> u16x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
fn reverse_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_u16x8<const SHIFT: usize>(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u16x8<Self>
fn slide_u16x8<const SHIFT: usize>( self, a: u16x8<Self>, b: u16x8<Self>, ) -> u16x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
) -> u16x8<Self>
fn compress_u16x8( self, values: u16x8<Self>, mask: mask16x8<Self>, ) -> u16x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
merge: u16x8<Self>,
) -> u16x8<Self>
fn compress_merge_u16x8( self, values: u16x8<Self>, mask: mask16x8<Self>, merge: u16x8<Self>, ) -> u16x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u16x8(self, values: u16x8<Self>, mask: mask16x8<Self>) -> u16x8<Self>
fn expand_u16x8(self, values: u16x8<Self>, mask: mask16x8<Self>) -> u16x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u16x8(
self,
values: u16x8<Self>,
mask: mask16x8<Self>,
merge: u16x8<Self>,
) -> u16x8<Self>
fn expand_merge_u16x8( self, values: u16x8<Self>, mask: mask16x8<Self>, merge: u16x8<Self>, ) -> u16x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
fn count_ones_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
fn count_zeros_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn saturating_add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn saturating_sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn mul_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn and_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn or_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn xor_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>
fn shl_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn shlv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>
fn shr_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn shrv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u16x8(self, a: u16x8<Self>) -> u16
fn reduce_max_u16x8(self, a: u16x8<Self>) -> u16
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u16x8(self, a: u16x8<Self>) -> u16
fn reduce_min_u16x8(self, a: u16x8<Self>) -> u16
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u16x8(self, a: u16x8<Self>) -> u16
fn reduce_sum_u16x8(self, a: u16x8<Self>) -> u16
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u16x8(self, a: u16x8<Self>) -> u16
fn reduce_product_u16x8(self, a: u16x8<Self>) -> u16
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn max_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn min_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
c: u16x8<Self>,
) -> u16x8<Self>
fn clamp_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, c: u16x8<Self>, ) -> u16x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
fn simd_eq_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
fn simd_lt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
fn simd_le_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn zip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn zip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn unzip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
fn unzip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u16x8<Self>, u16x8<Self>)
fn interleave_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, ) -> (u16x8<Self>, u16x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u16x8<Self>, u16x8<Self>)
fn deinterleave_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, ) -> (u16x8<Self>, u16x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u16x8(
self,
a: mask16x8<Self>,
b: u16x8<Self>,
c: u16x8<Self>,
) -> u16x8<Self>
fn select_u16x8( self, a: mask16x8<Self>, b: u16x8<Self>, c: u16x8<Self>, ) -> u16x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x16<Self>
fn combine_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn load_four_interleaved_u16x8(self, src: &[u16; 32]) -> [u16x8<Self>; 4]
fn load_four_interleaved_u16x8(self, src: &[u16; 32]) -> [u16x8<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_u16x8(
self,
vectors: [u16x8<Self>; 4],
dest: &mut [u16; 32],
)
fn store_four_interleaved_u16x8( self, vectors: [u16x8<Self>; 4], dest: &mut [u16; 32], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_u16x8(self, a: u16x8<Self>) -> (u32x4<Self>, u32x4<Self>)
fn widen_u16x8(self, a: u16x8<Self>) -> (u32x4<Self>, u32x4<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u32x4<Self>, u32x4<Self>)
fn widening_mul_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, ) -> (u32x4<Self>, u32x4<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> (u32x4<Self>, u32x4<Self>)
fn widening_add_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, ) -> (u32x4<Self>, u32x4<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u16x8(self, a: u16x8<Self>) -> u32x4<Self>
fn pairwise_widening_add_u16x8(self, a: u16x8<Self>) -> u32x4<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u32x4<Self>
fn pairwise_dot_product_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, ) -> u32x4<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>
fn narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>
fn saturating_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>
fn relaxed_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn splat_mask16x8(self, val: bool) -> mask16x8<Self>
fn splat_mask16x8(self, val: bool) -> mask16x8<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask16x8(self, bits: u64) -> mask16x8<Self>
fn from_bitmask_mask16x8(self, bits: u64) -> mask16x8<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask16x8(self, a: mask16x8<Self>) -> u64
fn to_bitmask_mask16x8(self, a: mask16x8<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn from_vector_mask16x8(self, vector: i16x8<Self>) -> mask16x8<Self>
fn from_vector_mask16x8(self, vector: i16x8<Self>) -> mask16x8<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask16x8(self, a: mask16x8<Self>) -> i16x8<Self>
fn to_vector_mask16x8(self, a: mask16x8<Self>) -> i16x8<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask16x8(self, a: &mut mask16x8<Self>, index: usize, value: bool)
fn set_mask16x8(self, a: &mut mask16x8<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask16x8<const OFFSET: usize>(
self,
a: mask16x8<Self>,
) -> mask16x8<Self>
fn rotate_elements_left_mask16x8<const OFFSET: usize>( self, a: mask16x8<Self>, ) -> mask16x8<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask16x8<const OFFSET: usize>(
self,
a: mask16x8<Self>,
) -> mask16x8<Self>
fn rotate_elements_right_mask16x8<const OFFSET: usize>( self, a: mask16x8<Self>, ) -> mask16x8<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn and_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>
fn and_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>
Compute the logical AND of two masks.
Sourcefn or_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>
fn or_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>
fn xor_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>
fn not_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>
fn reverse_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
c: mask16x8<Self>,
) -> mask16x8<Self>
fn select_mask16x8( self, a: mask16x8<Self>, b: mask16x8<Self>, c: mask16x8<Self>, ) -> mask16x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x8<Self>
fn simd_eq_mask16x8( self, a: mask16x8<Self>, b: mask16x8<Self>, ) -> mask16x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn any_true_mask16x8(self, a: mask16x8<Self>) -> bool
fn any_true_mask16x8(self, a: mask16x8<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask16x8(self, a: mask16x8<Self>) -> bool
fn all_true_mask16x8(self, a: mask16x8<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask16x8(self, a: mask16x8<Self>) -> bool
fn any_false_mask16x8(self, a: mask16x8<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask16x8(self, a: mask16x8<Self>) -> bool
fn all_false_mask16x8(self, a: mask16x8<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn combine_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x16<Self>
fn combine_mask16x8( self, a: mask16x8<Self>, b: mask16x8<Self>, ) -> mask16x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn widen_mask16x8(self, a: mask16x8<Self>) -> (mask32x4<Self>, mask32x4<Self>)
fn widen_mask16x8(self, a: mask16x8<Self>) -> (mask32x4<Self>, mask32x4<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn narrow_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask8x16<Self>
fn narrow_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask8x16<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
fn abs_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i32x4(self, val: i32) -> i32x4<Self>
fn splat_i32x4(self, val: i32) -> i32x4<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
fn reverse_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_i32x4<const SHIFT: usize>(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i32x4<Self>
fn slide_i32x4<const SHIFT: usize>( self, a: i32x4<Self>, b: i32x4<Self>, ) -> i32x4<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
) -> i32x4<Self>
fn compress_i32x4( self, values: i32x4<Self>, mask: mask32x4<Self>, ) -> i32x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
merge: i32x4<Self>,
) -> i32x4<Self>
fn compress_merge_i32x4( self, values: i32x4<Self>, mask: mask32x4<Self>, merge: i32x4<Self>, ) -> i32x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i32x4(self, values: i32x4<Self>, mask: mask32x4<Self>) -> i32x4<Self>
fn expand_i32x4(self, values: i32x4<Self>, mask: mask32x4<Self>) -> i32x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i32x4(
self,
values: i32x4<Self>,
mask: mask32x4<Self>,
merge: i32x4<Self>,
) -> i32x4<Self>
fn expand_merge_i32x4( self, values: i32x4<Self>, mask: mask32x4<Self>, merge: i32x4<Self>, ) -> i32x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
fn count_ones_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
fn count_zeros_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn saturating_add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn saturating_sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn mul_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn and_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn or_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn xor_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>
fn shl_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn shlv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>
fn shr_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn shrv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i32x4(self, a: i32x4<Self>) -> i32
fn reduce_max_i32x4(self, a: i32x4<Self>) -> i32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i32x4(self, a: i32x4<Self>) -> i32
fn reduce_min_i32x4(self, a: i32x4<Self>) -> i32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i32x4(self, a: i32x4<Self>) -> i32
fn reduce_sum_i32x4(self, a: i32x4<Self>) -> i32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i32x4(self, a: i32x4<Self>) -> i32
fn reduce_product_i32x4(self, a: i32x4<Self>) -> i32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn max_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn min_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
c: i32x4<Self>,
) -> i32x4<Self>
fn clamp_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, c: i32x4<Self>, ) -> i32x4<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
fn simd_eq_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
fn simd_lt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
fn simd_le_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn zip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn zip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn unzip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
fn unzip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i32x4<Self>, i32x4<Self>)
fn interleave_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, ) -> (i32x4<Self>, i32x4<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i32x4<Self>, i32x4<Self>)
fn deinterleave_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, ) -> (i32x4<Self>, i32x4<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i32x4(
self,
a: mask32x4<Self>,
b: i32x4<Self>,
c: i32x4<Self>,
) -> i32x4<Self>
fn select_i32x4( self, a: mask32x4<Self>, b: i32x4<Self>, c: i32x4<Self>, ) -> i32x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x8<Self>
fn combine_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn neg_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
fn neg_i32x4(self, a: i32x4<Self>) -> i32x4<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn load_four_interleaved_i32x4(self, src: &[i32; 16]) -> [i32x4<Self>; 4]
fn load_four_interleaved_i32x4(self, src: &[i32; 16]) -> [i32x4<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_i32x4(
self,
vectors: [i32x4<Self>; 4],
dest: &mut [i32; 16],
)
fn store_four_interleaved_i32x4( self, vectors: [i32x4<Self>; 4], dest: &mut [i32; 16], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_i32x4(self, a: i32x4<Self>) -> (i64x2<Self>, i64x2<Self>)
fn widen_i32x4(self, a: i32x4<Self>) -> (i64x2<Self>, i64x2<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i64x2<Self>, i64x2<Self>)
fn widening_mul_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, ) -> (i64x2<Self>, i64x2<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> (i64x2<Self>, i64x2<Self>)
fn widening_add_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, ) -> (i64x2<Self>, i64x2<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i32x4(self, a: i32x4<Self>) -> i64x2<Self>
fn pairwise_widening_add_i32x4(self, a: i32x4<Self>) -> i64x2<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i64x2<Self>
fn pairwise_dot_product_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, ) -> i64x2<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>
fn narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>
fn saturating_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>
fn relaxed_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f32_i32x4(self, a: i32x4<Self>) -> f32x4<Self>
fn cvt_f32_i32x4(self, a: i32x4<Self>) -> f32x4<Self>
Convert each signed 32-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_u32x4(self, val: u32) -> u32x4<Self>
fn splat_u32x4(self, val: u32) -> u32x4<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
fn reverse_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_u32x4<const SHIFT: usize>(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u32x4<Self>
fn slide_u32x4<const SHIFT: usize>( self, a: u32x4<Self>, b: u32x4<Self>, ) -> u32x4<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
) -> u32x4<Self>
fn compress_u32x4( self, values: u32x4<Self>, mask: mask32x4<Self>, ) -> u32x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
merge: u32x4<Self>,
) -> u32x4<Self>
fn compress_merge_u32x4( self, values: u32x4<Self>, mask: mask32x4<Self>, merge: u32x4<Self>, ) -> u32x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u32x4(self, values: u32x4<Self>, mask: mask32x4<Self>) -> u32x4<Self>
fn expand_u32x4(self, values: u32x4<Self>, mask: mask32x4<Self>) -> u32x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u32x4(
self,
values: u32x4<Self>,
mask: mask32x4<Self>,
merge: u32x4<Self>,
) -> u32x4<Self>
fn expand_merge_u32x4( self, values: u32x4<Self>, mask: mask32x4<Self>, merge: u32x4<Self>, ) -> u32x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
fn count_ones_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
fn count_zeros_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn saturating_add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn saturating_sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn mul_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn and_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn or_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn xor_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>
fn shl_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn shlv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>
fn shr_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn shrv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u32x4(self, a: u32x4<Self>) -> u32
fn reduce_max_u32x4(self, a: u32x4<Self>) -> u32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u32x4(self, a: u32x4<Self>) -> u32
fn reduce_min_u32x4(self, a: u32x4<Self>) -> u32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u32x4(self, a: u32x4<Self>) -> u32
fn reduce_sum_u32x4(self, a: u32x4<Self>) -> u32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u32x4(self, a: u32x4<Self>) -> u32
fn reduce_product_u32x4(self, a: u32x4<Self>) -> u32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn max_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn min_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
c: u32x4<Self>,
) -> u32x4<Self>
fn clamp_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, c: u32x4<Self>, ) -> u32x4<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
fn simd_eq_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
fn simd_lt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
fn simd_le_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn zip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn zip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn unzip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
fn unzip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u32x4<Self>, u32x4<Self>)
fn interleave_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, ) -> (u32x4<Self>, u32x4<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u32x4<Self>, u32x4<Self>)
fn deinterleave_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, ) -> (u32x4<Self>, u32x4<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u32x4(
self,
a: mask32x4<Self>,
b: u32x4<Self>,
c: u32x4<Self>,
) -> u32x4<Self>
fn select_u32x4( self, a: mask32x4<Self>, b: u32x4<Self>, c: u32x4<Self>, ) -> u32x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x8<Self>
fn combine_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn load_four_interleaved_u32x4(self, src: &[u32; 16]) -> [u32x4<Self>; 4]
fn load_four_interleaved_u32x4(self, src: &[u32; 16]) -> [u32x4<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_u32x4(
self,
vectors: [u32x4<Self>; 4],
dest: &mut [u32; 16],
)
fn store_four_interleaved_u32x4( self, vectors: [u32x4<Self>; 4], dest: &mut [u32; 16], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn widen_u32x4(self, a: u32x4<Self>) -> (u64x2<Self>, u64x2<Self>)
fn widen_u32x4(self, a: u32x4<Self>) -> (u64x2<Self>, u64x2<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u64x2<Self>, u64x2<Self>)
fn widening_mul_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, ) -> (u64x2<Self>, u64x2<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> (u64x2<Self>, u64x2<Self>)
fn widening_add_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, ) -> (u64x2<Self>, u64x2<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u32x4(self, a: u32x4<Self>) -> u64x2<Self>
fn pairwise_widening_add_u32x4(self, a: u32x4<Self>) -> u64x2<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u64x2<Self>
fn pairwise_dot_product_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, ) -> u64x2<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>
fn narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>
fn saturating_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>
fn relaxed_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f32_u32x4(self, a: u32x4<Self>) -> f32x4<Self>
fn cvt_f32_u32x4(self, a: u32x4<Self>) -> f32x4<Self>
Convert each unsigned 32-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_mask32x4(self, val: bool) -> mask32x4<Self>
fn splat_mask32x4(self, val: bool) -> mask32x4<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask32x4(self, bits: u64) -> mask32x4<Self>
fn from_bitmask_mask32x4(self, bits: u64) -> mask32x4<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask32x4(self, a: mask32x4<Self>) -> u64
fn to_bitmask_mask32x4(self, a: mask32x4<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn from_vector_mask32x4(self, vector: i32x4<Self>) -> mask32x4<Self>
fn from_vector_mask32x4(self, vector: i32x4<Self>) -> mask32x4<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask32x4(self, a: mask32x4<Self>) -> i32x4<Self>
fn to_vector_mask32x4(self, a: mask32x4<Self>) -> i32x4<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask32x4(self, a: &mut mask32x4<Self>, index: usize, value: bool)
fn set_mask32x4(self, a: &mut mask32x4<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask32x4<const OFFSET: usize>(
self,
a: mask32x4<Self>,
) -> mask32x4<Self>
fn rotate_elements_left_mask32x4<const OFFSET: usize>( self, a: mask32x4<Self>, ) -> mask32x4<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask32x4<const OFFSET: usize>(
self,
a: mask32x4<Self>,
) -> mask32x4<Self>
fn rotate_elements_right_mask32x4<const OFFSET: usize>( self, a: mask32x4<Self>, ) -> mask32x4<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn and_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>
fn and_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>
Compute the logical AND of two masks.
Sourcefn or_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>
fn or_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>
fn xor_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>
fn not_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>
fn reverse_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
c: mask32x4<Self>,
) -> mask32x4<Self>
fn select_mask32x4( self, a: mask32x4<Self>, b: mask32x4<Self>, c: mask32x4<Self>, ) -> mask32x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x4<Self>
fn simd_eq_mask32x4( self, a: mask32x4<Self>, b: mask32x4<Self>, ) -> mask32x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn any_true_mask32x4(self, a: mask32x4<Self>) -> bool
fn any_true_mask32x4(self, a: mask32x4<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask32x4(self, a: mask32x4<Self>) -> bool
fn all_true_mask32x4(self, a: mask32x4<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask32x4(self, a: mask32x4<Self>) -> bool
fn any_false_mask32x4(self, a: mask32x4<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask32x4(self, a: mask32x4<Self>) -> bool
fn all_false_mask32x4(self, a: mask32x4<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn combine_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x8<Self>
fn combine_mask32x4( self, a: mask32x4<Self>, b: mask32x4<Self>, ) -> mask32x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn widen_mask32x4(self, a: mask32x4<Self>) -> (mask64x2<Self>, mask64x2<Self>)
fn widen_mask32x4(self, a: mask32x4<Self>) -> (mask64x2<Self>, mask64x2<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn narrow_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask16x8<Self>
fn narrow_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask16x8<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn abs_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_f64x2(self, val: f64) -> f64x2<Self>
fn splat_f64x2(self, val: f64) -> f64x2<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn reverse_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_f64x2<const SHIFT: usize>(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> f64x2<Self>
fn slide_f64x2<const SHIFT: usize>( self, a: f64x2<Self>, b: f64x2<Self>, ) -> f64x2<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
) -> f64x2<Self>
fn compress_f64x2( self, values: f64x2<Self>, mask: mask64x2<Self>, ) -> f64x2<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
merge: f64x2<Self>,
) -> f64x2<Self>
fn compress_merge_f64x2( self, values: f64x2<Self>, mask: mask64x2<Self>, merge: f64x2<Self>, ) -> f64x2<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_f64x2(self, values: f64x2<Self>, mask: mask64x2<Self>) -> f64x2<Self>
fn expand_f64x2(self, values: f64x2<Self>, mask: mask64x2<Self>) -> f64x2<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_f64x2(
self,
values: f64x2<Self>,
mask: mask64x2<Self>,
merge: f64x2<Self>,
) -> f64x2<Self>
fn expand_merge_f64x2( self, values: f64x2<Self>, mask: mask64x2<Self>, merge: f64x2<Self>, ) -> f64x2<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn sqrt_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn sqrt_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Compute the square root of each element.
Negative elements other than -0.0 will become NaN.
Sourcefn approximate_recip_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn approximate_recip_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Compute an approximate reciprocal (1. / x) for each element.
This uses a fast hardware estimate where available, and falls back to exact division otherwise.
On x86 for f32, this has a relative error less than 1.5 × 2^-12. On AArch64 (f32 and f64), this has a relative error less than 2^-8. The precision of this operation may change as new platform support is added.
Sourcefn add_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn add_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Add two vectors element-wise.
Sourcefn sub_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn sub_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Subtract two vectors element-wise.
Sourcefn mul_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn mul_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Multiply two vectors element-wise.
Sourcefn div_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn div_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Divide two vectors element-wise.
Sourcefn copysign_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn copysign_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Return a vector with the magnitude of a and the sign of b for each element.
This operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit.
Sourcefn reduce_max_f64x2(self, a: f64x2<Self>) -> f64
fn reduce_max_f64x2(self, a: f64x2<Self>) -> f64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_f64x2(self, a: f64x2<Self>) -> f64
fn reduce_min_f64x2(self, a: f64x2<Self>) -> f64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_max_precise_f64x2(self, a: f64x2<Self>) -> f64
fn reduce_max_precise_f64x2(self, a: f64x2<Self>) -> f64
Return the maximum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_max.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_min_precise_f64x2(self, a: f64x2<Self>) -> f64
fn reduce_min_precise_f64x2(self, a: f64x2<Self>) -> f64
Return the minimum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_min.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_sum_f64x2(self, a: f64x2<Self>) -> f64
fn reduce_sum_f64x2(self, a: f64x2<Self>) -> f64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_f64x2(self, a: f64x2<Self>) -> f64
fn reduce_product_f64x2(self, a: f64x2<Self>) -> f64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn max_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn min_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn max_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn max_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Return the element-wise maximum of two vectors.
For integer vectors, this operation is the same as max.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn min_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn min_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Return the element-wise minimum of two vectors.
For integer vectors, this operation is the same as min.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn clamp_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>
fn clamp_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>, ) -> f64x2<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
fn simd_eq_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
fn simd_lt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
fn simd_le_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn zip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn zip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn unzip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
fn unzip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> (f64x2<Self>, f64x2<Self>)
fn interleave_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, ) -> (f64x2<Self>, f64x2<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> (f64x2<Self>, f64x2<Self>)
fn deinterleave_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, ) -> (f64x2<Self>, f64x2<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn mul_add_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>
fn mul_add_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>, ) -> f64x2<Self>
Compute (a * b) + c (fused multiply-add) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors.
Sourcefn mul_add_precise_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>
fn mul_add_precise_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>, ) -> f64x2<Self>
Compute (a * b) + c for each element, with a single rounding at the end.
The result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than mul_add on platforms without fused multiply-add instructions, including WebAssembly.
§Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn mul_sub_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>
fn mul_sub_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>, ) -> f64x2<Self>
Compute (a * b) - c (fused multiply-subtract) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors.
Sourcefn mul_sub_precise_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>
fn mul_sub_precise_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>, ) -> f64x2<Self>
Compute (a * b) - c for each element, with a single rounding at the end.
The result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than mul_sub on platforms without fused multiply-add instructions, including WebAssembly.
# Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn floor_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn floor_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Return the largest integer less than or equal to each element, that is, round towards negative infinity.
Sourcefn ceil_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn ceil_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Return the smallest integer greater than or equal to each element, that is, round towards positive infinity.
Sourcefn round_ties_even_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn round_ties_even_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Round each element to the nearest integer, with ties rounding to the nearest even integer.
Sourcefn round_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn round_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Round each element to the nearest integer, with ties rounding away from zero.
§Performance considerations
Only AArch64 has native instructions for this operation. round has to be emulated on all other platforms which is around 2-4x slower than round_ties_even. Prefer using round_ties_even if possible.
Sourcefn fract_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn fract_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Return the fractional part of each element.
This is equivalent to a - a.trunc().
Sourcefn trunc_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn trunc_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Return the integer part of each element, rounding towards zero.
Sourcefn to_degrees_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn to_degrees_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Converts radians to degrees.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn to_radians_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
fn to_radians_f64x2(self, a: f64x2<Self>) -> f64x2<Self>
Converts degrees to radians.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn is_nan_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_nan_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements are NaN.
Sourcefn is_infinite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_infinite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements are positive or negative infinite.
Sourcefn is_finite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_finite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements are neither infinite nor NaN.
Sourcefn is_subnormal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_subnormal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements are subnormal.
This classifies the stored bit pattern, even when floating-point operations treat subnormals as zero.
Sourcefn is_normal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_normal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN.
Sourcefn is_sign_positive_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_sign_positive_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements have a positive sign, including +0.0, NaNs with positive sign bit and positive infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_positive for details.
Sourcefn is_sign_negative_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
fn is_sign_negative_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>
Return a mask indicating which elements have a negative sign, including -0.0, NaNs with negative sign bit and negative infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_negative for details.
Sourcefn select_f64x2(
self,
a: mask64x2<Self>,
b: f64x2<Self>,
c: f64x2<Self>,
) -> f64x2<Self>
fn select_f64x2( self, a: mask64x2<Self>, b: f64x2<Self>, c: f64x2<Self>, ) -> f64x2<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x4<Self>
fn combine_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x4<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn load_four_interleaved_f64x2(self, src: &[f64; 8]) -> [f64x2<Self>; 4]
fn load_four_interleaved_f64x2(self, src: &[f64; 8]) -> [f64x2<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_f64x2(
self,
vectors: [f64x2<Self>; 4],
dest: &mut [f64; 8],
)
fn store_four_interleaved_f64x2( self, vectors: [f64x2<Self>; 4], dest: &mut [f64; 8], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>
fn narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
Values are rounded to the nearest representable f32, with ties resolved to even; overflow produces signed infinity.This is the same as the as operator, and follows the IEEE 754 narrowing behavior in round-to-even mode.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>
fn saturating_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
For floating-point vectors this is identical to narrow, including its rounding and overflow behavior.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>
fn relaxed_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
For floating-point vectors this is identical to narrow, including its rounding and overflow behavior.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_u64_f64x2(self, a: f64x2<Self>) -> u64x2<Self>
fn cvt_u64_f64x2(self, a: f64x2<Self>) -> u64x2<Self>
Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_u64_precise_f64x2(self, a: f64x2<Self>) -> u64x2<Self>
fn cvt_u64_precise_f64x2(self, a: f64x2<Self>) -> u64x2<Self>
Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn cvt_i64_f64x2(self, a: f64x2<Self>) -> i64x2<Self>
fn cvt_i64_f64x2(self, a: f64x2<Self>) -> i64x2<Self>
Convert each floating-point element to a signed 64-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_i64_precise_f64x2(self, a: f64x2<Self>) -> i64x2<Self>
fn cvt_i64_precise_f64x2(self, a: f64x2<Self>) -> i64x2<Self>
Convert each floating-point element to a signed 64-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn abs_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
fn abs_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i64x2(self, val: i64) -> i64x2<Self>
fn splat_i64x2(self, val: i64) -> i64x2<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
fn reverse_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_i64x2<const SHIFT: usize>(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> i64x2<Self>
fn slide_i64x2<const SHIFT: usize>( self, a: i64x2<Self>, b: i64x2<Self>, ) -> i64x2<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
) -> i64x2<Self>
fn compress_i64x2( self, values: i64x2<Self>, mask: mask64x2<Self>, ) -> i64x2<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
merge: i64x2<Self>,
) -> i64x2<Self>
fn compress_merge_i64x2( self, values: i64x2<Self>, mask: mask64x2<Self>, merge: i64x2<Self>, ) -> i64x2<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i64x2(self, values: i64x2<Self>, mask: mask64x2<Self>) -> i64x2<Self>
fn expand_i64x2(self, values: i64x2<Self>, mask: mask64x2<Self>) -> i64x2<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i64x2(
self,
values: i64x2<Self>,
mask: mask64x2<Self>,
merge: i64x2<Self>,
) -> i64x2<Self>
fn expand_merge_i64x2( self, values: i64x2<Self>, mask: mask64x2<Self>, merge: i64x2<Self>, ) -> i64x2<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
fn count_ones_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
fn count_zeros_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn saturating_add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn saturating_sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn mul_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn and_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn or_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn xor_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>
fn shl_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn shlv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>
fn shr_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn shrv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i64x2(self, a: i64x2<Self>) -> i64
fn reduce_max_i64x2(self, a: i64x2<Self>) -> i64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i64x2(self, a: i64x2<Self>) -> i64
fn reduce_min_i64x2(self, a: i64x2<Self>) -> i64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i64x2(self, a: i64x2<Self>) -> i64
fn reduce_sum_i64x2(self, a: i64x2<Self>) -> i64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i64x2(self, a: i64x2<Self>) -> i64
fn reduce_product_i64x2(self, a: i64x2<Self>) -> i64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn max_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn min_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
c: i64x2<Self>,
) -> i64x2<Self>
fn clamp_i64x2( self, a: i64x2<Self>, b: i64x2<Self>, c: i64x2<Self>, ) -> i64x2<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
fn simd_eq_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
fn simd_lt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
fn simd_le_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn zip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn zip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn unzip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
fn unzip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> (i64x2<Self>, i64x2<Self>)
fn interleave_i64x2( self, a: i64x2<Self>, b: i64x2<Self>, ) -> (i64x2<Self>, i64x2<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> (i64x2<Self>, i64x2<Self>)
fn deinterleave_i64x2( self, a: i64x2<Self>, b: i64x2<Self>, ) -> (i64x2<Self>, i64x2<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i64x2(
self,
a: mask64x2<Self>,
b: i64x2<Self>,
c: i64x2<Self>,
) -> i64x2<Self>
fn select_i64x2( self, a: mask64x2<Self>, b: i64x2<Self>, c: i64x2<Self>, ) -> i64x2<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x4<Self>
fn combine_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x4<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn neg_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
fn neg_i64x2(self, a: i64x2<Self>) -> i64x2<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn load_four_interleaved_i64x2(self, src: &[i64; 8]) -> [i64x2<Self>; 4]
fn load_four_interleaved_i64x2(self, src: &[i64; 8]) -> [i64x2<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_i64x2(
self,
vectors: [i64x2<Self>; 4],
dest: &mut [i64; 8],
)
fn store_four_interleaved_i64x2( self, vectors: [i64x2<Self>; 4], dest: &mut [i64; 8], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>
fn narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>
fn saturating_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>
fn relaxed_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f64_i64x2(self, a: i64x2<Self>) -> f64x2<Self>
fn cvt_f64_i64x2(self, a: i64x2<Self>) -> f64x2<Self>
Convert each signed 64-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_u64x2(self, val: u64) -> u64x2<Self>
fn splat_u64x2(self, val: u64) -> u64x2<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
fn reverse_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_u64x2<const SHIFT: usize>(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> u64x2<Self>
fn slide_u64x2<const SHIFT: usize>( self, a: u64x2<Self>, b: u64x2<Self>, ) -> u64x2<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
) -> u64x2<Self>
fn compress_u64x2( self, values: u64x2<Self>, mask: mask64x2<Self>, ) -> u64x2<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
merge: u64x2<Self>,
) -> u64x2<Self>
fn compress_merge_u64x2( self, values: u64x2<Self>, mask: mask64x2<Self>, merge: u64x2<Self>, ) -> u64x2<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u64x2(self, values: u64x2<Self>, mask: mask64x2<Self>) -> u64x2<Self>
fn expand_u64x2(self, values: u64x2<Self>, mask: mask64x2<Self>) -> u64x2<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u64x2(
self,
values: u64x2<Self>,
mask: mask64x2<Self>,
merge: u64x2<Self>,
) -> u64x2<Self>
fn expand_merge_u64x2( self, values: u64x2<Self>, mask: mask64x2<Self>, merge: u64x2<Self>, ) -> u64x2<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn count_ones_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
fn count_ones_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
fn count_zeros_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn saturating_add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn saturating_sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn mul_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn and_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn or_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn xor_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>
fn shl_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn shlv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>
fn shr_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn shrv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u64x2(self, a: u64x2<Self>) -> u64
fn reduce_max_u64x2(self, a: u64x2<Self>) -> u64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u64x2(self, a: u64x2<Self>) -> u64
fn reduce_min_u64x2(self, a: u64x2<Self>) -> u64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u64x2(self, a: u64x2<Self>) -> u64
fn reduce_sum_u64x2(self, a: u64x2<Self>) -> u64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u64x2(self, a: u64x2<Self>) -> u64
fn reduce_product_u64x2(self, a: u64x2<Self>) -> u64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn max_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn min_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
c: u64x2<Self>,
) -> u64x2<Self>
fn clamp_u64x2( self, a: u64x2<Self>, b: u64x2<Self>, c: u64x2<Self>, ) -> u64x2<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
fn simd_eq_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_lt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
fn simd_lt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
fn simd_le_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn zip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn zip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn zip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn unzip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
fn unzip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> (u64x2<Self>, u64x2<Self>)
fn interleave_u64x2( self, a: u64x2<Self>, b: u64x2<Self>, ) -> (u64x2<Self>, u64x2<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> (u64x2<Self>, u64x2<Self>)
fn deinterleave_u64x2( self, a: u64x2<Self>, b: u64x2<Self>, ) -> (u64x2<Self>, u64x2<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u64x2(
self,
a: mask64x2<Self>,
b: u64x2<Self>,
c: u64x2<Self>,
) -> u64x2<Self>
fn select_u64x2( self, a: mask64x2<Self>, b: u64x2<Self>, c: u64x2<Self>, ) -> u64x2<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn combine_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x4<Self>
fn combine_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x4<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn load_four_interleaved_u64x2(self, src: &[u64; 8]) -> [u64x2<Self>; 4]
fn load_four_interleaved_u64x2(self, src: &[u64; 8]) -> [u64x2<Self>; 4]
Load four 128-bit vectors from an array with 4-way interleaving.
This is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.
For example, with 32-bit lanes, memory laid out as[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3] loads as[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]].
Sourcefn store_four_interleaved_u64x2(
self,
vectors: [u64x2<Self>; 4],
dest: &mut [u64; 8],
)
fn store_four_interleaved_u64x2( self, vectors: [u64x2<Self>; 4], dest: &mut [u64; 8], )
Store four 128-bit vectors to an array with 4-way interleaving.
This is the inverse of load_four_interleaved.
This is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.
For example, with 32-bit lanes, vectors containing [[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]] get stored as [r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3].
Sourcefn narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>
fn narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>
fn saturating_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>
fn relaxed_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f64_u64x2(self, a: u64x2<Self>) -> f64x2<Self>
fn cvt_f64_u64x2(self, a: u64x2<Self>) -> f64x2<Self>
Convert each unsigned 64-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_mask64x2(self, val: bool) -> mask64x2<Self>
fn splat_mask64x2(self, val: bool) -> mask64x2<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask64x2(self, bits: u64) -> mask64x2<Self>
fn from_bitmask_mask64x2(self, bits: u64) -> mask64x2<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask64x2(self, a: mask64x2<Self>) -> u64
fn to_bitmask_mask64x2(self, a: mask64x2<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn from_vector_mask64x2(self, vector: i64x2<Self>) -> mask64x2<Self>
fn from_vector_mask64x2(self, vector: i64x2<Self>) -> mask64x2<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask64x2(self, a: mask64x2<Self>) -> i64x2<Self>
fn to_vector_mask64x2(self, a: mask64x2<Self>) -> i64x2<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask64x2(self, a: &mut mask64x2<Self>, index: usize, value: bool)
fn set_mask64x2(self, a: &mut mask64x2<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask64x2<const OFFSET: usize>(
self,
a: mask64x2<Self>,
) -> mask64x2<Self>
fn rotate_elements_left_mask64x2<const OFFSET: usize>( self, a: mask64x2<Self>, ) -> mask64x2<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask64x2<const OFFSET: usize>(
self,
a: mask64x2<Self>,
) -> mask64x2<Self>
fn rotate_elements_right_mask64x2<const OFFSET: usize>( self, a: mask64x2<Self>, ) -> mask64x2<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn and_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>
fn and_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>
Compute the logical AND of two masks.
Sourcefn or_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>
fn or_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>
fn xor_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>
fn not_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>
fn reverse_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
c: mask64x2<Self>,
) -> mask64x2<Self>
fn select_mask64x2( self, a: mask64x2<Self>, b: mask64x2<Self>, c: mask64x2<Self>, ) -> mask64x2<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x2<Self>
fn simd_eq_mask64x2( self, a: mask64x2<Self>, b: mask64x2<Self>, ) -> mask64x2<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn any_true_mask64x2(self, a: mask64x2<Self>) -> bool
fn any_true_mask64x2(self, a: mask64x2<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask64x2(self, a: mask64x2<Self>) -> bool
fn all_true_mask64x2(self, a: mask64x2<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask64x2(self, a: mask64x2<Self>) -> bool
fn any_false_mask64x2(self, a: mask64x2<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask64x2(self, a: mask64x2<Self>) -> bool
fn all_false_mask64x2(self, a: mask64x2<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn combine_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x4<Self>
fn combine_mask64x2( self, a: mask64x2<Self>, b: mask64x2<Self>, ) -> mask64x4<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn narrow_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask32x4<Self>
fn narrow_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask32x4<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn slide_f32x8<const SHIFT: usize>(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> f32x8<Self>
fn slide_f32x8<const SHIFT: usize>( self, a: f32x8<Self>, b: f32x8<Self>, ) -> f32x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
) -> f32x8<Self>
fn compress_f32x8( self, values: f32x8<Self>, mask: mask32x8<Self>, ) -> f32x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
merge: f32x8<Self>,
) -> f32x8<Self>
fn compress_merge_f32x8( self, values: f32x8<Self>, mask: mask32x8<Self>, merge: f32x8<Self>, ) -> f32x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_f32x8(self, values: f32x8<Self>, mask: mask32x8<Self>) -> f32x8<Self>
fn expand_f32x8(self, values: f32x8<Self>, mask: mask32x8<Self>) -> f32x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_f32x8(
self,
values: f32x8<Self>,
mask: mask32x8<Self>,
merge: f32x8<Self>,
) -> f32x8<Self>
fn expand_merge_f32x8( self, values: f32x8<Self>, mask: mask32x8<Self>, merge: f32x8<Self>, ) -> f32x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn is_nan_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_nan_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements are NaN.
Sourcefn is_infinite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_infinite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements are positive or negative infinite.
Sourcefn is_finite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_finite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements are neither infinite nor NaN.
Sourcefn is_subnormal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_subnormal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements are subnormal.
This classifies the stored bit pattern, even when floating-point operations treat subnormals as zero.
Sourcefn is_normal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_normal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN.
Sourcefn is_sign_positive_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_sign_positive_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements have a positive sign, including +0.0, NaNs with positive sign bit and positive infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_positive for details.
Sourcefn is_sign_negative_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
fn is_sign_negative_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>
Return a mask indicating which elements have a negative sign, including -0.0, NaNs with negative sign bit and negative infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_negative for details.
Sourcefn combine_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x16<Self>
fn combine_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_f32x8(self, a: f32x8<Self>) -> (f32x4<Self>, f32x4<Self>)
fn split_f32x8(self, a: f32x8<Self>) -> (f32x4<Self>, f32x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i8x32<const SHIFT: usize>(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> i8x32<Self>
fn slide_i8x32<const SHIFT: usize>( self, a: i8x32<Self>, b: i8x32<Self>, ) -> i8x32<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
) -> i8x32<Self>
fn compress_i8x32( self, values: i8x32<Self>, mask: mask8x32<Self>, ) -> i8x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
merge: i8x32<Self>,
) -> i8x32<Self>
fn compress_merge_i8x32( self, values: i8x32<Self>, mask: mask8x32<Self>, merge: i8x32<Self>, ) -> i8x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i8x32(self, values: i8x32<Self>, mask: mask8x32<Self>) -> i8x32<Self>
fn expand_i8x32(self, values: i8x32<Self>, mask: mask8x32<Self>) -> i8x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i8x32(
self,
values: i8x32<Self>,
mask: mask8x32<Self>,
merge: i8x32<Self>,
) -> i8x32<Self>
fn expand_merge_i8x32( self, values: i8x32<Self>, mask: mask8x32<Self>, merge: i8x32<Self>, ) -> i8x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x64<Self>
fn combine_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x64<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_i8x32(self, a: i8x32<Self>) -> (i8x16<Self>, i8x16<Self>)
fn split_i8x32(self, a: i8x32<Self>) -> (i8x16<Self>, i8x16<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u8x32<const SHIFT: usize>(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> u8x32<Self>
fn slide_u8x32<const SHIFT: usize>( self, a: u8x32<Self>, b: u8x32<Self>, ) -> u8x32<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn swizzle_dyn_u8x32(self, a: u8x32<Self>, indices: u8x32<Self>) -> u8x32<Self>
fn swizzle_dyn_u8x32(self, a: u8x32<Self>, indices: u8x32<Self>) -> u8x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u8x32(
self,
a: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>
fn swizzle_dyn_precise_u8x32( self, a: u8x32<Self>, indices: u8x32<Self>, ) -> u8x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>
fn concat_swizzle_dyn_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, indices: u8x32<Self>, ) -> u8x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>
fn concat_swizzle_dyn_precise_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, indices: u8x32<Self>, ) -> u8x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn compress_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
) -> u8x32<Self>
fn compress_u8x32( self, values: u8x32<Self>, mask: mask8x32<Self>, ) -> u8x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
merge: u8x32<Self>,
) -> u8x32<Self>
fn compress_merge_u8x32( self, values: u8x32<Self>, mask: mask8x32<Self>, merge: u8x32<Self>, ) -> u8x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u8x32(self, values: u8x32<Self>, mask: mask8x32<Self>) -> u8x32<Self>
fn expand_u8x32(self, values: u8x32<Self>, mask: mask8x32<Self>) -> u8x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u8x32(
self,
values: u8x32<Self>,
mask: mask8x32<Self>,
merge: u8x32<Self>,
) -> u8x32<Self>
fn expand_merge_u8x32( self, values: u8x32<Self>, mask: mask8x32<Self>, merge: u8x32<Self>, ) -> u8x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x64<Self>
fn combine_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x64<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_u8x32(self, a: u8x32<Self>) -> (u8x16<Self>, u8x16<Self>)
fn split_u8x32(self, a: u8x32<Self>) -> (u8x16<Self>, u8x16<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask8x32(self, vector: i8x32<Self>) -> mask8x32<Self>
fn from_vector_mask8x32(self, vector: i8x32<Self>) -> mask8x32<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask8x32(self, a: mask8x32<Self>) -> i8x32<Self>
fn to_vector_mask8x32(self, a: mask8x32<Self>) -> i8x32<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask8x32(self, a: &mut mask8x32<Self>, index: usize, value: bool)
fn set_mask8x32(self, a: &mut mask8x32<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask8x32<const OFFSET: usize>(
self,
a: mask8x32<Self>,
) -> mask8x32<Self>
fn rotate_elements_left_mask8x32<const OFFSET: usize>( self, a: mask8x32<Self>, ) -> mask8x32<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask8x32<const OFFSET: usize>(
self,
a: mask8x32<Self>,
) -> mask8x32<Self>
fn rotate_elements_right_mask8x32<const OFFSET: usize>( self, a: mask8x32<Self>, ) -> mask8x32<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn combine_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x64<Self>
fn combine_mask8x32( self, a: mask8x32<Self>, b: mask8x32<Self>, ) -> mask8x64<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_mask8x32(self, a: mask8x32<Self>) -> (mask8x16<Self>, mask8x16<Self>)
fn split_mask8x32(self, a: mask8x32<Self>) -> (mask8x16<Self>, mask8x16<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i16x16<const SHIFT: usize>(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i16x16<Self>
fn slide_i16x16<const SHIFT: usize>( self, a: i16x16<Self>, b: i16x16<Self>, ) -> i16x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
) -> i16x16<Self>
fn compress_i16x16( self, values: i16x16<Self>, mask: mask16x16<Self>, ) -> i16x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
merge: i16x16<Self>,
) -> i16x16<Self>
fn compress_merge_i16x16( self, values: i16x16<Self>, mask: mask16x16<Self>, merge: i16x16<Self>, ) -> i16x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
) -> i16x16<Self>
fn expand_i16x16( self, values: i16x16<Self>, mask: mask16x16<Self>, ) -> i16x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i16x16(
self,
values: i16x16<Self>,
mask: mask16x16<Self>,
merge: i16x16<Self>,
) -> i16x16<Self>
fn expand_merge_i16x16( self, values: i16x16<Self>, mask: mask16x16<Self>, merge: i16x16<Self>, ) -> i16x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x32<Self>
fn combine_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x32<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_i16x16(self, a: i16x16<Self>) -> (i16x8<Self>, i16x8<Self>)
fn split_i16x16(self, a: i16x16<Self>) -> (i16x8<Self>, i16x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u16x16<const SHIFT: usize>(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u16x16<Self>
fn slide_u16x16<const SHIFT: usize>( self, a: u16x16<Self>, b: u16x16<Self>, ) -> u16x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
) -> u16x16<Self>
fn compress_u16x16( self, values: u16x16<Self>, mask: mask16x16<Self>, ) -> u16x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
merge: u16x16<Self>,
) -> u16x16<Self>
fn compress_merge_u16x16( self, values: u16x16<Self>, mask: mask16x16<Self>, merge: u16x16<Self>, ) -> u16x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
) -> u16x16<Self>
fn expand_u16x16( self, values: u16x16<Self>, mask: mask16x16<Self>, ) -> u16x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u16x16(
self,
values: u16x16<Self>,
mask: mask16x16<Self>,
merge: u16x16<Self>,
) -> u16x16<Self>
fn expand_merge_u16x16( self, values: u16x16<Self>, mask: mask16x16<Self>, merge: u16x16<Self>, ) -> u16x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x32<Self>
fn combine_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x32<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_u16x16(self, a: u16x16<Self>) -> (u16x8<Self>, u16x8<Self>)
fn split_u16x16(self, a: u16x16<Self>) -> (u16x8<Self>, u16x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask16x16(self, vector: i16x16<Self>) -> mask16x16<Self>
fn from_vector_mask16x16(self, vector: i16x16<Self>) -> mask16x16<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask16x16(self, a: mask16x16<Self>) -> i16x16<Self>
fn to_vector_mask16x16(self, a: mask16x16<Self>) -> i16x16<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask16x16(self, a: &mut mask16x16<Self>, index: usize, value: bool)
fn set_mask16x16(self, a: &mut mask16x16<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask16x16<const OFFSET: usize>(
self,
a: mask16x16<Self>,
) -> mask16x16<Self>
fn rotate_elements_left_mask16x16<const OFFSET: usize>( self, a: mask16x16<Self>, ) -> mask16x16<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask16x16<const OFFSET: usize>(
self,
a: mask16x16<Self>,
) -> mask16x16<Self>
fn rotate_elements_right_mask16x16<const OFFSET: usize>( self, a: mask16x16<Self>, ) -> mask16x16<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn combine_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x32<Self>
fn combine_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, ) -> mask16x32<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_mask16x16(self, a: mask16x16<Self>) -> (mask16x8<Self>, mask16x8<Self>)
fn split_mask16x16(self, a: mask16x16<Self>) -> (mask16x8<Self>, mask16x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i32x8<const SHIFT: usize>(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i32x8<Self>
fn slide_i32x8<const SHIFT: usize>( self, a: i32x8<Self>, b: i32x8<Self>, ) -> i32x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
) -> i32x8<Self>
fn compress_i32x8( self, values: i32x8<Self>, mask: mask32x8<Self>, ) -> i32x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
merge: i32x8<Self>,
) -> i32x8<Self>
fn compress_merge_i32x8( self, values: i32x8<Self>, mask: mask32x8<Self>, merge: i32x8<Self>, ) -> i32x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i32x8(self, values: i32x8<Self>, mask: mask32x8<Self>) -> i32x8<Self>
fn expand_i32x8(self, values: i32x8<Self>, mask: mask32x8<Self>) -> i32x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i32x8(
self,
values: i32x8<Self>,
mask: mask32x8<Self>,
merge: i32x8<Self>,
) -> i32x8<Self>
fn expand_merge_i32x8( self, values: i32x8<Self>, mask: mask32x8<Self>, merge: i32x8<Self>, ) -> i32x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x16<Self>
fn combine_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_i32x8(self, a: i32x8<Self>) -> (i32x4<Self>, i32x4<Self>)
fn split_i32x8(self, a: i32x8<Self>) -> (i32x4<Self>, i32x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u32x8<const SHIFT: usize>(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u32x8<Self>
fn slide_u32x8<const SHIFT: usize>( self, a: u32x8<Self>, b: u32x8<Self>, ) -> u32x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
) -> u32x8<Self>
fn compress_u32x8( self, values: u32x8<Self>, mask: mask32x8<Self>, ) -> u32x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
merge: u32x8<Self>,
) -> u32x8<Self>
fn compress_merge_u32x8( self, values: u32x8<Self>, mask: mask32x8<Self>, merge: u32x8<Self>, ) -> u32x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u32x8(self, values: u32x8<Self>, mask: mask32x8<Self>) -> u32x8<Self>
fn expand_u32x8(self, values: u32x8<Self>, mask: mask32x8<Self>) -> u32x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u32x8(
self,
values: u32x8<Self>,
mask: mask32x8<Self>,
merge: u32x8<Self>,
) -> u32x8<Self>
fn expand_merge_u32x8( self, values: u32x8<Self>, mask: mask32x8<Self>, merge: u32x8<Self>, ) -> u32x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x16<Self>
fn combine_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_u32x8(self, a: u32x8<Self>) -> (u32x4<Self>, u32x4<Self>)
fn split_u32x8(self, a: u32x8<Self>) -> (u32x4<Self>, u32x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask32x8(self, vector: i32x8<Self>) -> mask32x8<Self>
fn from_vector_mask32x8(self, vector: i32x8<Self>) -> mask32x8<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask32x8(self, a: mask32x8<Self>) -> i32x8<Self>
fn to_vector_mask32x8(self, a: mask32x8<Self>) -> i32x8<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask32x8(self, a: &mut mask32x8<Self>, index: usize, value: bool)
fn set_mask32x8(self, a: &mut mask32x8<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask32x8<const OFFSET: usize>(
self,
a: mask32x8<Self>,
) -> mask32x8<Self>
fn rotate_elements_left_mask32x8<const OFFSET: usize>( self, a: mask32x8<Self>, ) -> mask32x8<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask32x8<const OFFSET: usize>(
self,
a: mask32x8<Self>,
) -> mask32x8<Self>
fn rotate_elements_right_mask32x8<const OFFSET: usize>( self, a: mask32x8<Self>, ) -> mask32x8<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn combine_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x16<Self>
fn combine_mask32x8( self, a: mask32x8<Self>, b: mask32x8<Self>, ) -> mask32x16<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_mask32x8(self, a: mask32x8<Self>) -> (mask32x4<Self>, mask32x4<Self>)
fn split_mask32x8(self, a: mask32x8<Self>) -> (mask32x4<Self>, mask32x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_f64x4<const SHIFT: usize>(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> f64x4<Self>
fn slide_f64x4<const SHIFT: usize>( self, a: f64x4<Self>, b: f64x4<Self>, ) -> f64x4<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
) -> f64x4<Self>
fn compress_f64x4( self, values: f64x4<Self>, mask: mask64x4<Self>, ) -> f64x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
merge: f64x4<Self>,
) -> f64x4<Self>
fn compress_merge_f64x4( self, values: f64x4<Self>, mask: mask64x4<Self>, merge: f64x4<Self>, ) -> f64x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_f64x4(self, values: f64x4<Self>, mask: mask64x4<Self>) -> f64x4<Self>
fn expand_f64x4(self, values: f64x4<Self>, mask: mask64x4<Self>) -> f64x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_f64x4(
self,
values: f64x4<Self>,
mask: mask64x4<Self>,
merge: f64x4<Self>,
) -> f64x4<Self>
fn expand_merge_f64x4( self, values: f64x4<Self>, mask: mask64x4<Self>, merge: f64x4<Self>, ) -> f64x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn is_nan_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_nan_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements are NaN.
Sourcefn is_infinite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_infinite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements are positive or negative infinite.
Sourcefn is_finite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_finite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements are neither infinite nor NaN.
Sourcefn is_subnormal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_subnormal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements are subnormal.
This classifies the stored bit pattern, even when floating-point operations treat subnormals as zero.
Sourcefn is_normal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_normal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN.
Sourcefn is_sign_positive_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_sign_positive_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements have a positive sign, including +0.0, NaNs with positive sign bit and positive infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_positive for details.
Sourcefn is_sign_negative_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
fn is_sign_negative_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>
Return a mask indicating which elements have a negative sign, including -0.0, NaNs with negative sign bit and negative infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_negative for details.
Sourcefn combine_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x8<Self>
fn combine_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_f64x4(self, a: f64x4<Self>) -> (f64x2<Self>, f64x2<Self>)
fn split_f64x4(self, a: f64x4<Self>) -> (f64x2<Self>, f64x2<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i64x4<const SHIFT: usize>(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> i64x4<Self>
fn slide_i64x4<const SHIFT: usize>( self, a: i64x4<Self>, b: i64x4<Self>, ) -> i64x4<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
) -> i64x4<Self>
fn compress_i64x4( self, values: i64x4<Self>, mask: mask64x4<Self>, ) -> i64x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
merge: i64x4<Self>,
) -> i64x4<Self>
fn compress_merge_i64x4( self, values: i64x4<Self>, mask: mask64x4<Self>, merge: i64x4<Self>, ) -> i64x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i64x4(self, values: i64x4<Self>, mask: mask64x4<Self>) -> i64x4<Self>
fn expand_i64x4(self, values: i64x4<Self>, mask: mask64x4<Self>) -> i64x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i64x4(
self,
values: i64x4<Self>,
mask: mask64x4<Self>,
merge: i64x4<Self>,
) -> i64x4<Self>
fn expand_merge_i64x4( self, values: i64x4<Self>, mask: mask64x4<Self>, merge: i64x4<Self>, ) -> i64x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x8<Self>
fn combine_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_i64x4(self, a: i64x4<Self>) -> (i64x2<Self>, i64x2<Self>)
fn split_i64x4(self, a: i64x4<Self>) -> (i64x2<Self>, i64x2<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u64x4<const SHIFT: usize>(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> u64x4<Self>
fn slide_u64x4<const SHIFT: usize>( self, a: u64x4<Self>, b: u64x4<Self>, ) -> u64x4<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
) -> u64x4<Self>
fn compress_u64x4( self, values: u64x4<Self>, mask: mask64x4<Self>, ) -> u64x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
merge: u64x4<Self>,
) -> u64x4<Self>
fn compress_merge_u64x4( self, values: u64x4<Self>, mask: mask64x4<Self>, merge: u64x4<Self>, ) -> u64x4<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u64x4(self, values: u64x4<Self>, mask: mask64x4<Self>) -> u64x4<Self>
fn expand_u64x4(self, values: u64x4<Self>, mask: mask64x4<Self>) -> u64x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u64x4(
self,
values: u64x4<Self>,
mask: mask64x4<Self>,
merge: u64x4<Self>,
) -> u64x4<Self>
fn expand_merge_u64x4( self, values: u64x4<Self>, mask: mask64x4<Self>, merge: u64x4<Self>, ) -> u64x4<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn combine_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x8<Self>
fn combine_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_u64x4(self, a: u64x4<Self>) -> (u64x2<Self>, u64x2<Self>)
fn split_u64x4(self, a: u64x4<Self>) -> (u64x2<Self>, u64x2<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask64x4(self, vector: i64x4<Self>) -> mask64x4<Self>
fn from_vector_mask64x4(self, vector: i64x4<Self>) -> mask64x4<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask64x4(self, a: mask64x4<Self>) -> i64x4<Self>
fn to_vector_mask64x4(self, a: mask64x4<Self>) -> i64x4<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask64x4(self, a: &mut mask64x4<Self>, index: usize, value: bool)
fn set_mask64x4(self, a: &mut mask64x4<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask64x4<const OFFSET: usize>(
self,
a: mask64x4<Self>,
) -> mask64x4<Self>
fn rotate_elements_left_mask64x4<const OFFSET: usize>( self, a: mask64x4<Self>, ) -> mask64x4<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask64x4<const OFFSET: usize>(
self,
a: mask64x4<Self>,
) -> mask64x4<Self>
fn rotate_elements_right_mask64x4<const OFFSET: usize>( self, a: mask64x4<Self>, ) -> mask64x4<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn combine_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x8<Self>
fn combine_mask64x4( self, a: mask64x4<Self>, b: mask64x4<Self>, ) -> mask64x8<Self>
Combine two vectors into a single vector with twice the width.
a provides the lower elements and b provides the upper elements.
Sourcefn split_mask64x4(self, a: mask64x4<Self>) -> (mask64x2<Self>, mask64x2<Self>)
fn split_mask64x4(self, a: mask64x4<Self>) -> (mask64x2<Self>, mask64x2<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_f32x16<const SHIFT: usize>(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> f32x16<Self>
fn slide_f32x16<const SHIFT: usize>( self, a: f32x16<Self>, b: f32x16<Self>, ) -> f32x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
) -> f32x16<Self>
fn compress_f32x16( self, values: f32x16<Self>, mask: mask32x16<Self>, ) -> f32x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
merge: f32x16<Self>,
) -> f32x16<Self>
fn compress_merge_f32x16( self, values: f32x16<Self>, mask: mask32x16<Self>, merge: f32x16<Self>, ) -> f32x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
) -> f32x16<Self>
fn expand_f32x16( self, values: f32x16<Self>, mask: mask32x16<Self>, ) -> f32x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_f32x16(
self,
values: f32x16<Self>,
mask: mask32x16<Self>,
merge: f32x16<Self>,
) -> f32x16<Self>
fn expand_merge_f32x16( self, values: f32x16<Self>, mask: mask32x16<Self>, merge: f32x16<Self>, ) -> f32x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn is_nan_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_nan_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements are NaN.
Sourcefn is_infinite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_infinite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements are positive or negative infinite.
Sourcefn is_finite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_finite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements are neither infinite nor NaN.
Sourcefn is_subnormal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_subnormal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements are subnormal.
This classifies the stored bit pattern, even when floating-point operations treat subnormals as zero.
Sourcefn is_normal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_normal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN.
Sourcefn is_sign_positive_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_sign_positive_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements have a positive sign, including +0.0, NaNs with positive sign bit and positive infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_positive for details.
Sourcefn is_sign_negative_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
fn is_sign_negative_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>
Return a mask indicating which elements have a negative sign, including -0.0, NaNs with negative sign bit and negative infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_negative for details.
Sourcefn split_f32x16(self, a: f32x16<Self>) -> (f32x8<Self>, f32x8<Self>)
fn split_f32x16(self, a: f32x16<Self>) -> (f32x8<Self>, f32x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i8x64<const SHIFT: usize>(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> i8x64<Self>
fn slide_i8x64<const SHIFT: usize>( self, a: i8x64<Self>, b: i8x64<Self>, ) -> i8x64<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
) -> i8x64<Self>
fn compress_i8x64( self, values: i8x64<Self>, mask: mask8x64<Self>, ) -> i8x64<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
merge: i8x64<Self>,
) -> i8x64<Self>
fn compress_merge_i8x64( self, values: i8x64<Self>, mask: mask8x64<Self>, merge: i8x64<Self>, ) -> i8x64<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i8x64(self, values: i8x64<Self>, mask: mask8x64<Self>) -> i8x64<Self>
fn expand_i8x64(self, values: i8x64<Self>, mask: mask8x64<Self>) -> i8x64<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i8x64(
self,
values: i8x64<Self>,
mask: mask8x64<Self>,
merge: i8x64<Self>,
) -> i8x64<Self>
fn expand_merge_i8x64( self, values: i8x64<Self>, mask: mask8x64<Self>, merge: i8x64<Self>, ) -> i8x64<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_i8x64(self, a: i8x64<Self>) -> (i8x32<Self>, i8x32<Self>)
fn split_i8x64(self, a: i8x64<Self>) -> (i8x32<Self>, i8x32<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u8x64<const SHIFT: usize>(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> u8x64<Self>
fn slide_u8x64<const SHIFT: usize>( self, a: u8x64<Self>, b: u8x64<Self>, ) -> u8x64<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn swizzle_dyn_u8x64(self, a: u8x64<Self>, indices: u8x64<Self>) -> u8x64<Self>
fn swizzle_dyn_u8x64(self, a: u8x64<Self>, indices: u8x64<Self>) -> u8x64<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u8x64(
self,
a: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>
fn swizzle_dyn_precise_u8x64( self, a: u8x64<Self>, indices: u8x64<Self>, ) -> u8x64<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>
fn concat_swizzle_dyn_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, indices: u8x64<Self>, ) -> u8x64<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>
fn concat_swizzle_dyn_precise_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, indices: u8x64<Self>, ) -> u8x64<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn compress_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
) -> u8x64<Self>
fn compress_u8x64( self, values: u8x64<Self>, mask: mask8x64<Self>, ) -> u8x64<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
merge: u8x64<Self>,
) -> u8x64<Self>
fn compress_merge_u8x64( self, values: u8x64<Self>, mask: mask8x64<Self>, merge: u8x64<Self>, ) -> u8x64<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u8x64(self, values: u8x64<Self>, mask: mask8x64<Self>) -> u8x64<Self>
fn expand_u8x64(self, values: u8x64<Self>, mask: mask8x64<Self>) -> u8x64<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u8x64(
self,
values: u8x64<Self>,
mask: mask8x64<Self>,
merge: u8x64<Self>,
) -> u8x64<Self>
fn expand_merge_u8x64( self, values: u8x64<Self>, mask: mask8x64<Self>, merge: u8x64<Self>, ) -> u8x64<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_u8x64(self, a: u8x64<Self>) -> (u8x32<Self>, u8x32<Self>)
fn split_u8x64(self, a: u8x64<Self>) -> (u8x32<Self>, u8x32<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask8x64(self, vector: i8x64<Self>) -> mask8x64<Self>
fn from_vector_mask8x64(self, vector: i8x64<Self>) -> mask8x64<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask8x64(self, a: mask8x64<Self>) -> i8x64<Self>
fn to_vector_mask8x64(self, a: mask8x64<Self>) -> i8x64<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask8x64(self, a: &mut mask8x64<Self>, index: usize, value: bool)
fn set_mask8x64(self, a: &mut mask8x64<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask8x64<const OFFSET: usize>(
self,
a: mask8x64<Self>,
) -> mask8x64<Self>
fn rotate_elements_left_mask8x64<const OFFSET: usize>( self, a: mask8x64<Self>, ) -> mask8x64<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask8x64<const OFFSET: usize>(
self,
a: mask8x64<Self>,
) -> mask8x64<Self>
fn rotate_elements_right_mask8x64<const OFFSET: usize>( self, a: mask8x64<Self>, ) -> mask8x64<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn split_mask8x64(self, a: mask8x64<Self>) -> (mask8x32<Self>, mask8x32<Self>)
fn split_mask8x64(self, a: mask8x64<Self>) -> (mask8x32<Self>, mask8x32<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i16x32<const SHIFT: usize>(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i16x32<Self>
fn slide_i16x32<const SHIFT: usize>( self, a: i16x32<Self>, b: i16x32<Self>, ) -> i16x32<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
) -> i16x32<Self>
fn compress_i16x32( self, values: i16x32<Self>, mask: mask16x32<Self>, ) -> i16x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
merge: i16x32<Self>,
) -> i16x32<Self>
fn compress_merge_i16x32( self, values: i16x32<Self>, mask: mask16x32<Self>, merge: i16x32<Self>, ) -> i16x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
) -> i16x32<Self>
fn expand_i16x32( self, values: i16x32<Self>, mask: mask16x32<Self>, ) -> i16x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i16x32(
self,
values: i16x32<Self>,
mask: mask16x32<Self>,
merge: i16x32<Self>,
) -> i16x32<Self>
fn expand_merge_i16x32( self, values: i16x32<Self>, mask: mask16x32<Self>, merge: i16x32<Self>, ) -> i16x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_i16x32(self, a: i16x32<Self>) -> (i16x16<Self>, i16x16<Self>)
fn split_i16x32(self, a: i16x32<Self>) -> (i16x16<Self>, i16x16<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u16x32<const SHIFT: usize>(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u16x32<Self>
fn slide_u16x32<const SHIFT: usize>( self, a: u16x32<Self>, b: u16x32<Self>, ) -> u16x32<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
) -> u16x32<Self>
fn compress_u16x32( self, values: u16x32<Self>, mask: mask16x32<Self>, ) -> u16x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
merge: u16x32<Self>,
) -> u16x32<Self>
fn compress_merge_u16x32( self, values: u16x32<Self>, mask: mask16x32<Self>, merge: u16x32<Self>, ) -> u16x32<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
) -> u16x32<Self>
fn expand_u16x32( self, values: u16x32<Self>, mask: mask16x32<Self>, ) -> u16x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u16x32(
self,
values: u16x32<Self>,
mask: mask16x32<Self>,
merge: u16x32<Self>,
) -> u16x32<Self>
fn expand_merge_u16x32( self, values: u16x32<Self>, mask: mask16x32<Self>, merge: u16x32<Self>, ) -> u16x32<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_u16x32(self, a: u16x32<Self>) -> (u16x16<Self>, u16x16<Self>)
fn split_u16x32(self, a: u16x32<Self>) -> (u16x16<Self>, u16x16<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask16x32(self, vector: i16x32<Self>) -> mask16x32<Self>
fn from_vector_mask16x32(self, vector: i16x32<Self>) -> mask16x32<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask16x32(self, a: mask16x32<Self>) -> i16x32<Self>
fn to_vector_mask16x32(self, a: mask16x32<Self>) -> i16x32<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask16x32(self, a: &mut mask16x32<Self>, index: usize, value: bool)
fn set_mask16x32(self, a: &mut mask16x32<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask16x32<const OFFSET: usize>(
self,
a: mask16x32<Self>,
) -> mask16x32<Self>
fn rotate_elements_left_mask16x32<const OFFSET: usize>( self, a: mask16x32<Self>, ) -> mask16x32<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask16x32<const OFFSET: usize>(
self,
a: mask16x32<Self>,
) -> mask16x32<Self>
fn rotate_elements_right_mask16x32<const OFFSET: usize>( self, a: mask16x32<Self>, ) -> mask16x32<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn split_mask16x32(
self,
a: mask16x32<Self>,
) -> (mask16x16<Self>, mask16x16<Self>)
fn split_mask16x32( self, a: mask16x32<Self>, ) -> (mask16x16<Self>, mask16x16<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i32x16<const SHIFT: usize>(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i32x16<Self>
fn slide_i32x16<const SHIFT: usize>( self, a: i32x16<Self>, b: i32x16<Self>, ) -> i32x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
) -> i32x16<Self>
fn compress_i32x16( self, values: i32x16<Self>, mask: mask32x16<Self>, ) -> i32x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
merge: i32x16<Self>,
) -> i32x16<Self>
fn compress_merge_i32x16( self, values: i32x16<Self>, mask: mask32x16<Self>, merge: i32x16<Self>, ) -> i32x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
) -> i32x16<Self>
fn expand_i32x16( self, values: i32x16<Self>, mask: mask32x16<Self>, ) -> i32x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i32x16(
self,
values: i32x16<Self>,
mask: mask32x16<Self>,
merge: i32x16<Self>,
) -> i32x16<Self>
fn expand_merge_i32x16( self, values: i32x16<Self>, mask: mask32x16<Self>, merge: i32x16<Self>, ) -> i32x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_i32x16(self, a: i32x16<Self>) -> (i32x8<Self>, i32x8<Self>)
fn split_i32x16(self, a: i32x16<Self>) -> (i32x8<Self>, i32x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u32x16<const SHIFT: usize>(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u32x16<Self>
fn slide_u32x16<const SHIFT: usize>( self, a: u32x16<Self>, b: u32x16<Self>, ) -> u32x16<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
) -> u32x16<Self>
fn compress_u32x16( self, values: u32x16<Self>, mask: mask32x16<Self>, ) -> u32x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
merge: u32x16<Self>,
) -> u32x16<Self>
fn compress_merge_u32x16( self, values: u32x16<Self>, mask: mask32x16<Self>, merge: u32x16<Self>, ) -> u32x16<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
) -> u32x16<Self>
fn expand_u32x16( self, values: u32x16<Self>, mask: mask32x16<Self>, ) -> u32x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u32x16(
self,
values: u32x16<Self>,
mask: mask32x16<Self>,
merge: u32x16<Self>,
) -> u32x16<Self>
fn expand_merge_u32x16( self, values: u32x16<Self>, mask: mask32x16<Self>, merge: u32x16<Self>, ) -> u32x16<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_u32x16(self, a: u32x16<Self>) -> (u32x8<Self>, u32x8<Self>)
fn split_u32x16(self, a: u32x16<Self>) -> (u32x8<Self>, u32x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask32x16(self, vector: i32x16<Self>) -> mask32x16<Self>
fn from_vector_mask32x16(self, vector: i32x16<Self>) -> mask32x16<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask32x16(self, a: mask32x16<Self>) -> i32x16<Self>
fn to_vector_mask32x16(self, a: mask32x16<Self>) -> i32x16<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask32x16(self, a: &mut mask32x16<Self>, index: usize, value: bool)
fn set_mask32x16(self, a: &mut mask32x16<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask32x16<const OFFSET: usize>(
self,
a: mask32x16<Self>,
) -> mask32x16<Self>
fn rotate_elements_left_mask32x16<const OFFSET: usize>( self, a: mask32x16<Self>, ) -> mask32x16<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask32x16<const OFFSET: usize>(
self,
a: mask32x16<Self>,
) -> mask32x16<Self>
fn rotate_elements_right_mask32x16<const OFFSET: usize>( self, a: mask32x16<Self>, ) -> mask32x16<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn split_mask32x16(self, a: mask32x16<Self>) -> (mask32x8<Self>, mask32x8<Self>)
fn split_mask32x16(self, a: mask32x16<Self>) -> (mask32x8<Self>, mask32x8<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_f64x8<const SHIFT: usize>(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> f64x8<Self>
fn slide_f64x8<const SHIFT: usize>( self, a: f64x8<Self>, b: f64x8<Self>, ) -> f64x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
) -> f64x8<Self>
fn compress_f64x8( self, values: f64x8<Self>, mask: mask64x8<Self>, ) -> f64x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
merge: f64x8<Self>,
) -> f64x8<Self>
fn compress_merge_f64x8( self, values: f64x8<Self>, mask: mask64x8<Self>, merge: f64x8<Self>, ) -> f64x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_f64x8(self, values: f64x8<Self>, mask: mask64x8<Self>) -> f64x8<Self>
fn expand_f64x8(self, values: f64x8<Self>, mask: mask64x8<Self>) -> f64x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_f64x8(
self,
values: f64x8<Self>,
mask: mask64x8<Self>,
merge: f64x8<Self>,
) -> f64x8<Self>
fn expand_merge_f64x8( self, values: f64x8<Self>, mask: mask64x8<Self>, merge: f64x8<Self>, ) -> f64x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn is_nan_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_nan_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements are NaN.
Sourcefn is_infinite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_infinite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements are positive or negative infinite.
Sourcefn is_finite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_finite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements are neither infinite nor NaN.
Sourcefn is_subnormal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_subnormal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements are subnormal.
This classifies the stored bit pattern, even when floating-point operations treat subnormals as zero.
Sourcefn is_normal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_normal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN.
Sourcefn is_sign_positive_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_sign_positive_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements have a positive sign, including +0.0, NaNs with positive sign bit and positive infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_positive for details.
Sourcefn is_sign_negative_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
fn is_sign_negative_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>
Return a mask indicating which elements have a negative sign, including -0.0, NaNs with negative sign bit and negative infinity.
NaN inputs may produce an unexpected or non-portable result, see f32::is_sign_negative for details.
Sourcefn split_f64x8(self, a: f64x8<Self>) -> (f64x4<Self>, f64x4<Self>)
fn split_f64x8(self, a: f64x8<Self>) -> (f64x4<Self>, f64x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_i64x8<const SHIFT: usize>(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> i64x8<Self>
fn slide_i64x8<const SHIFT: usize>( self, a: i64x8<Self>, b: i64x8<Self>, ) -> i64x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
) -> i64x8<Self>
fn compress_i64x8( self, values: i64x8<Self>, mask: mask64x8<Self>, ) -> i64x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
merge: i64x8<Self>,
) -> i64x8<Self>
fn compress_merge_i64x8( self, values: i64x8<Self>, mask: mask64x8<Self>, merge: i64x8<Self>, ) -> i64x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_i64x8(self, values: i64x8<Self>, mask: mask64x8<Self>) -> i64x8<Self>
fn expand_i64x8(self, values: i64x8<Self>, mask: mask64x8<Self>) -> i64x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_i64x8(
self,
values: i64x8<Self>,
mask: mask64x8<Self>,
merge: i64x8<Self>,
) -> i64x8<Self>
fn expand_merge_i64x8( self, values: i64x8<Self>, mask: mask64x8<Self>, merge: i64x8<Self>, ) -> i64x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_i64x8(self, a: i64x8<Self>) -> (i64x4<Self>, i64x4<Self>)
fn split_i64x8(self, a: i64x8<Self>) -> (i64x4<Self>, i64x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn slide_u64x8<const SHIFT: usize>(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> u64x8<Self>
fn slide_u64x8<const SHIFT: usize>( self, a: u64x8<Self>, b: u64x8<Self>, ) -> u64x8<Self>
Concatenate [self, rhs] and extract Self::LEN elements starting at index SHIFT.
SHIFT must be within [0, Self::LEN].
This can be used to implement a “shift items” operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by M items, the left-hand side should be all zeroes, and the shift amount will be Self::LEN - M.
This can also be used to rotate items within a vector by providing the same vector as both operands.
slide::<1>([a b c d], [e f g h]) == [b c d e]
Sourcefn compress_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
) -> u64x8<Self>
fn compress_u64x8( self, values: u64x8<Self>, mask: mask64x8<Self>, ) -> u64x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
This is equivalent to SimdBase::compress_merge with a zeroed merge vector.
Sourcefn compress_merge_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
merge: u64x8<Self>,
) -> u64x8<Self>
fn compress_merge_u64x8( self, values: u64x8<Self>, mask: mask64x8<Self>, merge: u64x8<Self>, ) -> u64x8<Self>
Compact the elements selected by mask into consecutive low lanes, preserving their order.
Lanes above the number of selected elements retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[k] = values[i];
k += 1;
}
}
return result;Sourcefn expand_u64x8(self, values: u64x8<Self>, mask: mask64x8<Self>) -> u64x8<Self>
fn expand_u64x8(self, values: u64x8<Self>, mask: mask64x8<Self>) -> u64x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes are zero (positive zero for floats).
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros..
This is equivalent to SimdBase::expand_merge with a zeroed merge vector.
Sourcefn expand_merge_u64x8(
self,
values: u64x8<Self>,
mask: mask64x8<Self>,
merge: u64x8<Self>,
) -> u64x8<Self>
fn expand_merge_u64x8( self, values: u64x8<Self>, mask: mask64x8<Self>, merge: u64x8<Self>, ) -> u64x8<Self>
Expand consecutive low elements from values into the lanes selected by mask, preserving their order.
Unselected lanes retain the corresponding values from merge.
Elements are moved without changing their bits, including floating-point NaN payloads and signed zeros.
§Pseudo code
let mut result = merge;
let mut k = 0;
for i in 0..LEN {
if mask[i] {
result[i] = values[k];
k += 1;
}
}
return result;Sourcefn split_u64x8(self, a: u64x8<Self>) -> (u64x4<Self>, u64x4<Self>)
fn split_u64x8(self, a: u64x8<Self>) -> (u64x4<Self>, u64x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Sourcefn from_vector_mask64x8(self, vector: i64x8<Self>) -> mask64x8<Self>
fn from_vector_mask64x8(self, vector: i64x8<Self>) -> mask64x8<Self>
Create a SIMD mask from an integer vector of the same width.
A lane value of -1 means “true”, a lane value of 0 means “false”, and all other lane values result in unspecified behavior.
Sourcefn to_vector_mask64x8(self, a: mask64x8<Self>) -> i64x8<Self>
fn to_vector_mask64x8(self, a: mask64x8<Self>) -> i64x8<Self>
Convert a SIMD mask to an integer vector of the same width.
“True” maps to -1 and “false” maps to 0.
Sourcefn set_mask64x8(self, a: &mut mask64x8<Self>, index: usize, value: bool)
fn set_mask64x8(self, a: &mut mask64x8<Self>, index: usize, value: bool)
Set one logical lane of a SIMD mask.
Sourcefn rotate_elements_left_mask64x8<const OFFSET: usize>(
self,
a: mask64x8<Self>,
) -> mask64x8<Self>
fn rotate_elements_left_mask64x8<const OFFSET: usize>( self, a: mask64x8<Self>, ) -> mask64x8<Self>
Rotate the mask elements to the left by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn rotate_elements_right_mask64x8<const OFFSET: usize>(
self,
a: mask64x8<Self>,
) -> mask64x8<Self>
fn rotate_elements_right_mask64x8<const OFFSET: usize>( self, a: mask64x8<Self>, ) -> mask64x8<Self>
Rotate the mask elements to the right by OFFSET.
If OFFSET is greater than or equal to Self::LEN, it wraps modulo Self::LEN.
Sourcefn split_mask64x8(self, a: mask64x8<Self>) -> (mask64x4<Self>, mask64x4<Self>)
fn split_mask64x8(self, a: mask64x8<Self>) -> (mask64x4<Self>, mask64x4<Self>)
Split a vector into two vectors of half the width.
Returns a tuple of (lower half, upper half).
Provided Methods§
Sourcefn slide_within_blocks_f32x4<const SHIFT: usize>(
self,
a: f32x4<Self>,
b: f32x4<Self>,
) -> f32x4<Self>
fn slide_within_blocks_f32x4<const SHIFT: usize>( self, a: f32x4<Self>, b: f32x4<Self>, ) -> f32x4<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_f32x4(
self,
a: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self>
fn swizzle_dyn_within_blocks_f32x4( self, a: f32x4<Self>, indices: u8x16<Self>, ) -> f32x4<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_f32x4(self, a: f32x4<Self>, indices: u8x16<Self>) -> f32x4<Self>
fn swizzle_dyn_f32x4(self, a: f32x4<Self>, indices: u8x16<Self>) -> f32x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_f32x4(
self,
a: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self>
fn swizzle_dyn_precise_f32x4( self, a: f32x4<Self>, indices: u8x16<Self>, ) -> f32x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self>
fn concat_swizzle_dyn_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, indices: u8x16<Self>, ) -> f32x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_f32x4(
self,
a: f32x4<Self>,
b: f32x4<Self>,
indices: u8x16<Self>,
) -> f32x4<Self>
fn concat_swizzle_dyn_precise_f32x4( self, a: f32x4<Self>, b: f32x4<Self>, indices: u8x16<Self>, ) -> f32x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
fn simd_ne_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
fn simd_ge_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
fn simd_gt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn slide_within_blocks_i8x16<const SHIFT: usize>(
self,
a: i8x16<Self>,
b: i8x16<Self>,
) -> i8x16<Self>
fn slide_within_blocks_i8x16<const SHIFT: usize>( self, a: i8x16<Self>, b: i8x16<Self>, ) -> i8x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i8x16(
self,
a: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self>
fn swizzle_dyn_within_blocks_i8x16( self, a: i8x16<Self>, indices: u8x16<Self>, ) -> i8x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i8x16(self, a: i8x16<Self>, indices: u8x16<Self>) -> i8x16<Self>
fn swizzle_dyn_i8x16(self, a: i8x16<Self>, indices: u8x16<Self>) -> i8x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i8x16(
self,
a: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self>
fn swizzle_dyn_precise_i8x16( self, a: i8x16<Self>, indices: u8x16<Self>, ) -> i8x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self>
fn concat_swizzle_dyn_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, indices: u8x16<Self>, ) -> i8x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i8x16(
self,
a: i8x16<Self>,
b: i8x16<Self>,
indices: u8x16<Self>,
) -> i8x16<Self>
fn concat_swizzle_dyn_precise_i8x16( self, a: i8x16<Self>, b: i8x16<Self>, indices: u8x16<Self>, ) -> i8x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
fn simd_ne_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
fn simd_ge_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
fn simd_gt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn abs_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
fn abs_u8x16(self, a: u8x16<Self>) -> u8x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn slide_within_blocks_u8x16<const SHIFT: usize>(
self,
a: u8x16<Self>,
b: u8x16<Self>,
) -> u8x16<Self>
fn slide_within_blocks_u8x16<const SHIFT: usize>( self, a: u8x16<Self>, b: u8x16<Self>, ) -> u8x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn simd_ne_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
fn simd_ne_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
fn simd_ge_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
fn simd_gt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn simd_ne_mask8x16(
self,
a: mask8x16<Self>,
b: mask8x16<Self>,
) -> mask8x16<Self>
fn simd_ne_mask8x16( self, a: mask8x16<Self>, b: mask8x16<Self>, ) -> mask8x16<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn slide_within_blocks_i16x8<const SHIFT: usize>(
self,
a: i16x8<Self>,
b: i16x8<Self>,
) -> i16x8<Self>
fn slide_within_blocks_i16x8<const SHIFT: usize>( self, a: i16x8<Self>, b: i16x8<Self>, ) -> i16x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i16x8(
self,
a: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self>
fn swizzle_dyn_within_blocks_i16x8( self, a: i16x8<Self>, indices: u8x16<Self>, ) -> i16x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i16x8(self, a: i16x8<Self>, indices: u8x16<Self>) -> i16x8<Self>
fn swizzle_dyn_i16x8(self, a: i16x8<Self>, indices: u8x16<Self>) -> i16x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i16x8(
self,
a: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self>
fn swizzle_dyn_precise_i16x8( self, a: i16x8<Self>, indices: u8x16<Self>, ) -> i16x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self>
fn concat_swizzle_dyn_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, indices: u8x16<Self>, ) -> i16x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i16x8(
self,
a: i16x8<Self>,
b: i16x8<Self>,
indices: u8x16<Self>,
) -> i16x8<Self>
fn concat_swizzle_dyn_precise_i16x8( self, a: i16x8<Self>, b: i16x8<Self>, indices: u8x16<Self>, ) -> i16x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
fn simd_ne_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
fn simd_ge_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
fn simd_gt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn abs_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
fn abs_u16x8(self, a: u16x8<Self>) -> u16x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn slide_within_blocks_u16x8<const SHIFT: usize>(
self,
a: u16x8<Self>,
b: u16x8<Self>,
) -> u16x8<Self>
fn slide_within_blocks_u16x8<const SHIFT: usize>( self, a: u16x8<Self>, b: u16x8<Self>, ) -> u16x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u16x8(
self,
a: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self>
fn swizzle_dyn_within_blocks_u16x8( self, a: u16x8<Self>, indices: u8x16<Self>, ) -> u16x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u16x8(self, a: u16x8<Self>, indices: u8x16<Self>) -> u16x8<Self>
fn swizzle_dyn_u16x8(self, a: u16x8<Self>, indices: u8x16<Self>) -> u16x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u16x8(
self,
a: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self>
fn swizzle_dyn_precise_u16x8( self, a: u16x8<Self>, indices: u8x16<Self>, ) -> u16x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self>
fn concat_swizzle_dyn_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, indices: u8x16<Self>, ) -> u16x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u16x8(
self,
a: u16x8<Self>,
b: u16x8<Self>,
indices: u8x16<Self>,
) -> u16x8<Self>
fn concat_swizzle_dyn_precise_u16x8( self, a: u16x8<Self>, b: u16x8<Self>, indices: u8x16<Self>, ) -> u16x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
fn simd_ne_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
fn simd_ge_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
fn simd_gt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn simd_ne_mask16x8(
self,
a: mask16x8<Self>,
b: mask16x8<Self>,
) -> mask16x8<Self>
fn simd_ne_mask16x8( self, a: mask16x8<Self>, b: mask16x8<Self>, ) -> mask16x8<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn slide_within_blocks_i32x4<const SHIFT: usize>(
self,
a: i32x4<Self>,
b: i32x4<Self>,
) -> i32x4<Self>
fn slide_within_blocks_i32x4<const SHIFT: usize>( self, a: i32x4<Self>, b: i32x4<Self>, ) -> i32x4<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i32x4(
self,
a: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self>
fn swizzle_dyn_within_blocks_i32x4( self, a: i32x4<Self>, indices: u8x16<Self>, ) -> i32x4<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i32x4(self, a: i32x4<Self>, indices: u8x16<Self>) -> i32x4<Self>
fn swizzle_dyn_i32x4(self, a: i32x4<Self>, indices: u8x16<Self>) -> i32x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i32x4(
self,
a: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self>
fn swizzle_dyn_precise_i32x4( self, a: i32x4<Self>, indices: u8x16<Self>, ) -> i32x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self>
fn concat_swizzle_dyn_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, indices: u8x16<Self>, ) -> i32x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i32x4(
self,
a: i32x4<Self>,
b: i32x4<Self>,
indices: u8x16<Self>,
) -> i32x4<Self>
fn concat_swizzle_dyn_precise_i32x4( self, a: i32x4<Self>, b: i32x4<Self>, indices: u8x16<Self>, ) -> i32x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
fn simd_ne_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
fn simd_ge_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
fn simd_gt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn abs_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
fn abs_u32x4(self, a: u32x4<Self>) -> u32x4<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn slide_within_blocks_u32x4<const SHIFT: usize>(
self,
a: u32x4<Self>,
b: u32x4<Self>,
) -> u32x4<Self>
fn slide_within_blocks_u32x4<const SHIFT: usize>( self, a: u32x4<Self>, b: u32x4<Self>, ) -> u32x4<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u32x4(
self,
a: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self>
fn swizzle_dyn_within_blocks_u32x4( self, a: u32x4<Self>, indices: u8x16<Self>, ) -> u32x4<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u32x4(self, a: u32x4<Self>, indices: u8x16<Self>) -> u32x4<Self>
fn swizzle_dyn_u32x4(self, a: u32x4<Self>, indices: u8x16<Self>) -> u32x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u32x4(
self,
a: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self>
fn swizzle_dyn_precise_u32x4( self, a: u32x4<Self>, indices: u8x16<Self>, ) -> u32x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self>
fn concat_swizzle_dyn_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, indices: u8x16<Self>, ) -> u32x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u32x4(
self,
a: u32x4<Self>,
b: u32x4<Self>,
indices: u8x16<Self>,
) -> u32x4<Self>
fn concat_swizzle_dyn_precise_u32x4( self, a: u32x4<Self>, b: u32x4<Self>, indices: u8x16<Self>, ) -> u32x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
fn simd_ne_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
fn simd_ge_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
fn simd_gt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn simd_ne_mask32x4(
self,
a: mask32x4<Self>,
b: mask32x4<Self>,
) -> mask32x4<Self>
fn simd_ne_mask32x4( self, a: mask32x4<Self>, b: mask32x4<Self>, ) -> mask32x4<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn slide_within_blocks_f64x2<const SHIFT: usize>(
self,
a: f64x2<Self>,
b: f64x2<Self>,
) -> f64x2<Self>
fn slide_within_blocks_f64x2<const SHIFT: usize>( self, a: f64x2<Self>, b: f64x2<Self>, ) -> f64x2<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_f64x2(
self,
a: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self>
fn swizzle_dyn_within_blocks_f64x2( self, a: f64x2<Self>, indices: u8x16<Self>, ) -> f64x2<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_f64x2(self, a: f64x2<Self>, indices: u8x16<Self>) -> f64x2<Self>
fn swizzle_dyn_f64x2(self, a: f64x2<Self>, indices: u8x16<Self>) -> f64x2<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_f64x2(
self,
a: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self>
fn swizzle_dyn_precise_f64x2( self, a: f64x2<Self>, indices: u8x16<Self>, ) -> f64x2<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self>
fn concat_swizzle_dyn_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, indices: u8x16<Self>, ) -> f64x2<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_f64x2(
self,
a: f64x2<Self>,
b: f64x2<Self>,
indices: u8x16<Self>,
) -> f64x2<Self>
fn concat_swizzle_dyn_precise_f64x2( self, a: f64x2<Self>, b: f64x2<Self>, indices: u8x16<Self>, ) -> f64x2<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
fn simd_ne_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
fn simd_ge_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
fn simd_gt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn slide_within_blocks_i64x2<const SHIFT: usize>(
self,
a: i64x2<Self>,
b: i64x2<Self>,
) -> i64x2<Self>
fn slide_within_blocks_i64x2<const SHIFT: usize>( self, a: i64x2<Self>, b: i64x2<Self>, ) -> i64x2<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i64x2(
self,
a: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self>
fn swizzle_dyn_within_blocks_i64x2( self, a: i64x2<Self>, indices: u8x16<Self>, ) -> i64x2<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i64x2(self, a: i64x2<Self>, indices: u8x16<Self>) -> i64x2<Self>
fn swizzle_dyn_i64x2(self, a: i64x2<Self>, indices: u8x16<Self>) -> i64x2<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i64x2(
self,
a: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self>
fn swizzle_dyn_precise_i64x2( self, a: i64x2<Self>, indices: u8x16<Self>, ) -> i64x2<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self>
fn concat_swizzle_dyn_i64x2( self, a: i64x2<Self>, b: i64x2<Self>, indices: u8x16<Self>, ) -> i64x2<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i64x2(
self,
a: i64x2<Self>,
b: i64x2<Self>,
indices: u8x16<Self>,
) -> i64x2<Self>
fn concat_swizzle_dyn_precise_i64x2( self, a: i64x2<Self>, b: i64x2<Self>, indices: u8x16<Self>, ) -> i64x2<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
fn simd_ne_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
fn simd_ge_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
fn simd_gt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn abs_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
fn abs_u64x2(self, a: u64x2<Self>) -> u64x2<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn slide_within_blocks_u64x2<const SHIFT: usize>(
self,
a: u64x2<Self>,
b: u64x2<Self>,
) -> u64x2<Self>
fn slide_within_blocks_u64x2<const SHIFT: usize>( self, a: u64x2<Self>, b: u64x2<Self>, ) -> u64x2<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u64x2(
self,
a: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self>
fn swizzle_dyn_within_blocks_u64x2( self, a: u64x2<Self>, indices: u8x16<Self>, ) -> u64x2<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u64x2(self, a: u64x2<Self>, indices: u8x16<Self>) -> u64x2<Self>
fn swizzle_dyn_u64x2(self, a: u64x2<Self>, indices: u8x16<Self>) -> u64x2<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u64x2(
self,
a: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self>
fn swizzle_dyn_precise_u64x2( self, a: u64x2<Self>, indices: u8x16<Self>, ) -> u64x2<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self>
fn concat_swizzle_dyn_u64x2( self, a: u64x2<Self>, b: u64x2<Self>, indices: u8x16<Self>, ) -> u64x2<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u64x2(
self,
a: u64x2<Self>,
b: u64x2<Self>,
indices: u8x16<Self>,
) -> u64x2<Self>
fn concat_swizzle_dyn_precise_u64x2( self, a: u64x2<Self>, b: u64x2<Self>, indices: u8x16<Self>, ) -> u64x2<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn simd_ne_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
fn simd_ne_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_ge_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
fn simd_ge_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
fn simd_gt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn simd_ne_mask64x2(
self,
a: mask64x2<Self>,
b: mask64x2<Self>,
) -> mask64x2<Self>
fn simd_ne_mask64x2( self, a: mask64x2<Self>, b: mask64x2<Self>, ) -> mask64x2<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn abs_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn abs_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_f32x8(self, val: f32) -> f32x8<Self>
fn splat_f32x8(self, val: f32) -> f32x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn reverse_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_f32x8<const SHIFT: usize>(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> f32x8<Self>
fn slide_within_blocks_f32x8<const SHIFT: usize>( self, a: f32x8<Self>, b: f32x8<Self>, ) -> f32x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_f32x8(
self,
a: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self>
fn swizzle_dyn_within_blocks_f32x8( self, a: f32x8<Self>, indices: u8x32<Self>, ) -> f32x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_f32x8(self, a: f32x8<Self>, indices: u8x32<Self>) -> f32x8<Self>
fn swizzle_dyn_f32x8(self, a: f32x8<Self>, indices: u8x32<Self>) -> f32x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_f32x8(
self,
a: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self>
fn swizzle_dyn_precise_f32x8( self, a: f32x8<Self>, indices: u8x32<Self>, ) -> f32x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self>
fn concat_swizzle_dyn_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, indices: u8x32<Self>, ) -> f32x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
indices: u8x32<Self>,
) -> f32x8<Self>
fn concat_swizzle_dyn_precise_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, indices: u8x32<Self>, ) -> f32x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn sqrt_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn sqrt_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Compute the square root of each element.
Negative elements other than -0.0 will become NaN.
Sourcefn approximate_recip_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn approximate_recip_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Compute an approximate reciprocal (1. / x) for each element.
This uses a fast hardware estimate where available, and falls back to exact division otherwise.
On x86 for f32, this has a relative error less than 1.5 × 2^-12. On AArch64 (f32 and f64), this has a relative error less than 2^-8. The precision of this operation may change as new platform support is added.
Sourcefn add_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn add_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Add two vectors element-wise.
Sourcefn sub_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn sub_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Subtract two vectors element-wise.
Sourcefn mul_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn mul_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Multiply two vectors element-wise.
Sourcefn div_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn div_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Divide two vectors element-wise.
Sourcefn copysign_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn copysign_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Return a vector with the magnitude of a and the sign of b for each element.
This operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit.
Sourcefn reduce_max_f32x8(self, a: f32x8<Self>) -> f32
fn reduce_max_f32x8(self, a: f32x8<Self>) -> f32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_f32x8(self, a: f32x8<Self>) -> f32
fn reduce_min_f32x8(self, a: f32x8<Self>) -> f32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_max_precise_f32x8(self, a: f32x8<Self>) -> f32
fn reduce_max_precise_f32x8(self, a: f32x8<Self>) -> f32
Return the maximum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_max.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_min_precise_f32x8(self, a: f32x8<Self>) -> f32
fn reduce_min_precise_f32x8(self, a: f32x8<Self>) -> f32
Return the minimum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_min.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_sum_f32x8(self, a: f32x8<Self>) -> f32
fn reduce_sum_f32x8(self, a: f32x8<Self>) -> f32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_f32x8(self, a: f32x8<Self>) -> f32
fn reduce_product_f32x8(self, a: f32x8<Self>) -> f32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn max_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn min_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn max_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn max_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Return the element-wise maximum of two vectors.
For integer vectors, this operation is the same as max.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn min_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn min_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Return the element-wise minimum of two vectors.
For integer vectors, this operation is the same as min.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn clamp_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self>
fn clamp_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>, ) -> f32x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
fn simd_eq_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
fn simd_ne_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
fn simd_lt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
fn simd_le_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
fn simd_ge_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
fn simd_gt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn zip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn zip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn unzip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
fn unzip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> (f32x8<Self>, f32x8<Self>)
fn interleave_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, ) -> (f32x8<Self>, f32x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
) -> (f32x8<Self>, f32x8<Self>)
fn deinterleave_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, ) -> (f32x8<Self>, f32x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn mul_add_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self>
fn mul_add_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>, ) -> f32x8<Self>
Compute (a * b) + c (fused multiply-add) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors.
Sourcefn mul_add_precise_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self>
fn mul_add_precise_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>, ) -> f32x8<Self>
Compute (a * b) + c for each element, with a single rounding at the end.
The result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than mul_add on platforms without fused multiply-add instructions, including WebAssembly.
§Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn mul_sub_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self>
fn mul_sub_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>, ) -> f32x8<Self>
Compute (a * b) - c (fused multiply-subtract) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors.
Sourcefn mul_sub_precise_f32x8(
self,
a: f32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self>
fn mul_sub_precise_f32x8( self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>, ) -> f32x8<Self>
Compute (a * b) - c for each element, with a single rounding at the end.
The result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than mul_sub on platforms without fused multiply-add instructions, including WebAssembly.
# Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn floor_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn floor_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Return the largest integer less than or equal to each element, that is, round towards negative infinity.
Sourcefn ceil_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn ceil_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Return the smallest integer greater than or equal to each element, that is, round towards positive infinity.
Sourcefn round_ties_even_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn round_ties_even_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Round each element to the nearest integer, with ties rounding to the nearest even integer.
Sourcefn round_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn round_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Round each element to the nearest integer, with ties rounding away from zero.
§Performance considerations
Only AArch64 has native instructions for this operation. round has to be emulated on all other platforms which is around 2-4x slower than round_ties_even. Prefer using round_ties_even if possible.
Sourcefn fract_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn fract_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Return the fractional part of each element.
This is equivalent to a - a.trunc().
Sourcefn trunc_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn trunc_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Return the integer part of each element, rounding towards zero.
Sourcefn to_degrees_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn to_degrees_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Converts radians to degrees.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn to_radians_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
fn to_radians_f32x8(self, a: f32x8<Self>) -> f32x8<Self>
Converts degrees to radians.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn select_f32x8(
self,
a: mask32x8<Self>,
b: f32x8<Self>,
c: f32x8<Self>,
) -> f32x8<Self>
fn select_f32x8( self, a: mask32x8<Self>, b: f32x8<Self>, c: f32x8<Self>, ) -> f32x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_f32x8(self, a: f32x8<Self>) -> (f64x4<Self>, f64x4<Self>)
fn widen_f32x8(self, a: f32x8<Self>) -> (f64x4<Self>, f64x4<Self>)
Widen every f32 lane exactly into two same-width f64 vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn cvt_u32_f32x8(self, a: f32x8<Self>) -> u32x8<Self>
fn cvt_u32_f32x8(self, a: f32x8<Self>) -> u32x8<Self>
Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
On x86 platforms below AVX-512, this operation will still be slower than converting to i32, because there is no native instruction for converting to u32.
If you know your values fit within range of an i32, you should convert to an i32 and cast to your desired datatype afterwards.
Sourcefn cvt_u32_precise_f32x8(self, a: f32x8<Self>) -> u32x8<Self>
fn cvt_u32_precise_f32x8(self, a: f32x8<Self>) -> u32x8<Self>
Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn cvt_i32_f32x8(self, a: f32x8<Self>) -> i32x8<Self>
fn cvt_i32_f32x8(self, a: f32x8<Self>) -> i32x8<Self>
Convert each floating-point element to a signed 32-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_i32_precise_f32x8(self, a: f32x8<Self>) -> i32x8<Self>
fn cvt_i32_precise_f32x8(self, a: f32x8<Self>) -> i32x8<Self>
Convert each floating-point element to a signed 32-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn abs_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
fn abs_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i8x32(self, val: i8) -> i8x32<Self>
fn splat_i8x32(self, val: i8) -> i8x32<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
fn reverse_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i8x32<const SHIFT: usize>(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> i8x32<Self>
fn slide_within_blocks_i8x32<const SHIFT: usize>( self, a: i8x32<Self>, b: i8x32<Self>, ) -> i8x32<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i8x32(
self,
a: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self>
fn swizzle_dyn_within_blocks_i8x32( self, a: i8x32<Self>, indices: u8x32<Self>, ) -> i8x32<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i8x32(self, a: i8x32<Self>, indices: u8x32<Self>) -> i8x32<Self>
fn swizzle_dyn_i8x32(self, a: i8x32<Self>, indices: u8x32<Self>) -> i8x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i8x32(
self,
a: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self>
fn swizzle_dyn_precise_i8x32( self, a: i8x32<Self>, indices: u8x32<Self>, ) -> i8x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self>
fn concat_swizzle_dyn_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, indices: u8x32<Self>, ) -> i8x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
indices: u8x32<Self>,
) -> i8x32<Self>
fn concat_swizzle_dyn_precise_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, indices: u8x32<Self>, ) -> i8x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
fn count_ones_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
fn count_zeros_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn saturating_add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn saturating_sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn mul_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn and_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn or_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn xor_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self>
fn shl_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn shlv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self>
fn shr_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn shrv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i8x32(self, a: i8x32<Self>) -> i8
fn reduce_max_i8x32(self, a: i8x32<Self>) -> i8
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i8x32(self, a: i8x32<Self>) -> i8
fn reduce_min_i8x32(self, a: i8x32<Self>) -> i8
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i8x32(self, a: i8x32<Self>) -> i8
fn reduce_sum_i8x32(self, a: i8x32<Self>) -> i8
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i8x32(self, a: i8x32<Self>) -> i8
fn reduce_product_i8x32(self, a: i8x32<Self>) -> i8
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn max_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn min_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
c: i8x32<Self>,
) -> i8x32<Self>
fn clamp_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, c: i8x32<Self>, ) -> i8x32<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
fn simd_eq_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
fn simd_ne_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
fn simd_lt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
fn simd_le_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
fn simd_ge_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
fn simd_gt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn zip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn zip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn unzip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
fn unzip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i8x32<Self>, i8x32<Self>)
fn interleave_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, ) -> (i8x32<Self>, i8x32<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i8x32<Self>, i8x32<Self>)
fn deinterleave_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, ) -> (i8x32<Self>, i8x32<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i8x32(
self,
a: mask8x32<Self>,
b: i8x32<Self>,
c: i8x32<Self>,
) -> i8x32<Self>
fn select_i8x32( self, a: mask8x32<Self>, b: i8x32<Self>, c: i8x32<Self>, ) -> i8x32<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
fn neg_i8x32(self, a: i8x32<Self>) -> i8x32<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn widen_i8x32(self, a: i8x32<Self>) -> (i16x16<Self>, i16x16<Self>)
fn widen_i8x32(self, a: i8x32<Self>) -> (i16x16<Self>, i16x16<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i16x16<Self>, i16x16<Self>)
fn widening_mul_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, ) -> (i16x16<Self>, i16x16<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> (i16x16<Self>, i16x16<Self>)
fn widening_add_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, ) -> (i16x16<Self>, i16x16<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i8x32(self, a: i8x32<Self>) -> i16x16<Self>
fn pairwise_widening_add_i8x32(self, a: i8x32<Self>) -> i16x16<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i8x32(
self,
a: i8x32<Self>,
b: i8x32<Self>,
) -> i16x16<Self>
fn pairwise_dot_product_i8x32( self, a: i8x32<Self>, b: i8x32<Self>, ) -> i16x16<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn abs_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
fn abs_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u8x32(self, val: u8) -> u8x32<Self>
fn splat_u8x32(self, val: u8) -> u8x32<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
fn reverse_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u8x32<const SHIFT: usize>(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> u8x32<Self>
fn slide_within_blocks_u8x32<const SHIFT: usize>( self, a: u8x32<Self>, b: u8x32<Self>, ) -> u8x32<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u8x32(
self,
a: u8x32<Self>,
indices: u8x32<Self>,
) -> u8x32<Self>
fn swizzle_dyn_within_blocks_u8x32( self, a: u8x32<Self>, indices: u8x32<Self>, ) -> u8x32<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn count_ones_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
fn count_ones_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
fn count_zeros_u8x32(self, a: u8x32<Self>) -> u8x32<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn saturating_add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn saturating_sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn mul_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn and_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn or_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn xor_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self>
fn shl_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn shlv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self>
fn shr_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn shrv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u8x32(self, a: u8x32<Self>) -> u8
fn reduce_max_u8x32(self, a: u8x32<Self>) -> u8
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u8x32(self, a: u8x32<Self>) -> u8
fn reduce_min_u8x32(self, a: u8x32<Self>) -> u8
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u8x32(self, a: u8x32<Self>) -> u8
fn reduce_sum_u8x32(self, a: u8x32<Self>) -> u8
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u8x32(self, a: u8x32<Self>) -> u8
fn reduce_product_u8x32(self, a: u8x32<Self>) -> u8
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn max_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn min_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
c: u8x32<Self>,
) -> u8x32<Self>
fn clamp_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, c: u8x32<Self>, ) -> u8x32<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
fn simd_eq_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
fn simd_ne_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
fn simd_lt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
fn simd_le_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
fn simd_ge_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
fn simd_gt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn zip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn zip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn unzip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
fn unzip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u8x32<Self>, u8x32<Self>)
fn interleave_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, ) -> (u8x32<Self>, u8x32<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u8x32<Self>, u8x32<Self>)
fn deinterleave_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, ) -> (u8x32<Self>, u8x32<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u8x32(
self,
a: mask8x32<Self>,
b: u8x32<Self>,
c: u8x32<Self>,
) -> u8x32<Self>
fn select_u8x32( self, a: mask8x32<Self>, b: u8x32<Self>, c: u8x32<Self>, ) -> u8x32<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_u8x32(self, a: u8x32<Self>) -> (u16x16<Self>, u16x16<Self>)
fn widen_u8x32(self, a: u8x32<Self>) -> (u16x16<Self>, u16x16<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u16x16<Self>, u16x16<Self>)
fn widening_mul_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, ) -> (u16x16<Self>, u16x16<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> (u16x16<Self>, u16x16<Self>)
fn widening_add_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, ) -> (u16x16<Self>, u16x16<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u8x32(self, a: u8x32<Self>) -> u16x16<Self>
fn pairwise_widening_add_u8x32(self, a: u8x32<Self>) -> u16x16<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u8x32(
self,
a: u8x32<Self>,
b: u8x32<Self>,
) -> u16x16<Self>
fn pairwise_dot_product_u8x32( self, a: u8x32<Self>, b: u8x32<Self>, ) -> u16x16<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn splat_mask8x32(self, val: bool) -> mask8x32<Self>
fn splat_mask8x32(self, val: bool) -> mask8x32<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask8x32(self, bits: u64) -> mask8x32<Self>
fn from_bitmask_mask8x32(self, bits: u64) -> mask8x32<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask8x32(self, a: mask8x32<Self>) -> u64
fn to_bitmask_mask8x32(self, a: mask8x32<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self>
fn and_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self>
Compute the logical AND of two masks.
Sourcefn or_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self>
fn or_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self>
fn xor_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self>
fn not_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self>
fn reverse_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
c: mask8x32<Self>,
) -> mask8x32<Self>
fn select_mask8x32( self, a: mask8x32<Self>, b: mask8x32<Self>, c: mask8x32<Self>, ) -> mask8x32<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x32<Self>
fn simd_eq_mask8x32( self, a: mask8x32<Self>, b: mask8x32<Self>, ) -> mask8x32<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask8x32(
self,
a: mask8x32<Self>,
b: mask8x32<Self>,
) -> mask8x32<Self>
fn simd_ne_mask8x32( self, a: mask8x32<Self>, b: mask8x32<Self>, ) -> mask8x32<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask8x32(self, a: mask8x32<Self>) -> bool
fn any_true_mask8x32(self, a: mask8x32<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask8x32(self, a: mask8x32<Self>) -> bool
fn all_true_mask8x32(self, a: mask8x32<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask8x32(self, a: mask8x32<Self>) -> bool
fn any_false_mask8x32(self, a: mask8x32<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask8x32(self, a: mask8x32<Self>) -> bool
fn all_false_mask8x32(self, a: mask8x32<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn widen_mask8x32(self, a: mask8x32<Self>) -> (mask16x16<Self>, mask16x16<Self>)
fn widen_mask8x32(self, a: mask8x32<Self>) -> (mask16x16<Self>, mask16x16<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
fn abs_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i16x16(self, val: i16) -> i16x16<Self>
fn splat_i16x16(self, val: i16) -> i16x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
fn reverse_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i16x16<const SHIFT: usize>(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i16x16<Self>
fn slide_within_blocks_i16x16<const SHIFT: usize>( self, a: i16x16<Self>, b: i16x16<Self>, ) -> i16x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i16x16(
self,
a: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self>
fn swizzle_dyn_within_blocks_i16x16( self, a: i16x16<Self>, indices: u8x32<Self>, ) -> i16x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i16x16(
self,
a: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self>
fn swizzle_dyn_i16x16( self, a: i16x16<Self>, indices: u8x32<Self>, ) -> i16x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i16x16(
self,
a: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self>
fn swizzle_dyn_precise_i16x16( self, a: i16x16<Self>, indices: u8x32<Self>, ) -> i16x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self>
fn concat_swizzle_dyn_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, indices: u8x32<Self>, ) -> i16x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
indices: u8x32<Self>,
) -> i16x16<Self>
fn concat_swizzle_dyn_precise_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, indices: u8x32<Self>, ) -> i16x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
fn count_ones_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
fn count_zeros_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn saturating_add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn saturating_sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn mul_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn and_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn or_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn xor_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Compute the bitwise XOR of two vectors.
Sourcefn not_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
fn not_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
Compute the bitwise NOT of the vector.
Sourcefn shl_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self>
fn shl_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn shlv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self>
fn shr_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn shrv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i16x16(self, a: i16x16<Self>) -> i16
fn reduce_max_i16x16(self, a: i16x16<Self>) -> i16
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i16x16(self, a: i16x16<Self>) -> i16
fn reduce_min_i16x16(self, a: i16x16<Self>) -> i16
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i16x16(self, a: i16x16<Self>) -> i16
fn reduce_sum_i16x16(self, a: i16x16<Self>) -> i16
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i16x16(self, a: i16x16<Self>) -> i16
fn reduce_product_i16x16(self, a: i16x16<Self>) -> i16
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn max_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn min_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
c: i16x16<Self>,
) -> i16x16<Self>
fn clamp_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, c: i16x16<Self>, ) -> i16x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
fn simd_eq_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
fn simd_ne_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
fn simd_lt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
fn simd_le_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
fn simd_ge_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
fn simd_gt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn zip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn zip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn unzip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
fn unzip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i16x16<Self>, i16x16<Self>)
fn interleave_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, ) -> (i16x16<Self>, i16x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i16x16<Self>, i16x16<Self>)
fn deinterleave_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, ) -> (i16x16<Self>, i16x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i16x16(
self,
a: mask16x16<Self>,
b: i16x16<Self>,
c: i16x16<Self>,
) -> i16x16<Self>
fn select_i16x16( self, a: mask16x16<Self>, b: i16x16<Self>, c: i16x16<Self>, ) -> i16x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
fn neg_i16x16(self, a: i16x16<Self>) -> i16x16<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn widen_i16x16(self, a: i16x16<Self>) -> (i32x8<Self>, i32x8<Self>)
fn widen_i16x16(self, a: i16x16<Self>) -> (i32x8<Self>, i32x8<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i32x8<Self>, i32x8<Self>)
fn widening_mul_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, ) -> (i32x8<Self>, i32x8<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> (i32x8<Self>, i32x8<Self>)
fn widening_add_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, ) -> (i32x8<Self>, i32x8<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i16x16(self, a: i16x16<Self>) -> i32x8<Self>
fn pairwise_widening_add_i16x16(self, a: i16x16<Self>) -> i32x8<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i32x8<Self>
fn pairwise_dot_product_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, ) -> i32x8<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self>
fn narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i16x16(
self,
a: i16x16<Self>,
b: i16x16<Self>,
) -> i8x32<Self>
fn saturating_narrow_i16x16( self, a: i16x16<Self>, b: i16x16<Self>, ) -> i8x32<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self>
fn relaxed_narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn abs_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
fn abs_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u16x16(self, val: u16) -> u16x16<Self>
fn splat_u16x16(self, val: u16) -> u16x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
fn reverse_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u16x16<const SHIFT: usize>(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u16x16<Self>
fn slide_within_blocks_u16x16<const SHIFT: usize>( self, a: u16x16<Self>, b: u16x16<Self>, ) -> u16x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u16x16(
self,
a: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self>
fn swizzle_dyn_within_blocks_u16x16( self, a: u16x16<Self>, indices: u8x32<Self>, ) -> u16x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u16x16(
self,
a: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self>
fn swizzle_dyn_u16x16( self, a: u16x16<Self>, indices: u8x32<Self>, ) -> u16x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u16x16(
self,
a: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self>
fn swizzle_dyn_precise_u16x16( self, a: u16x16<Self>, indices: u8x32<Self>, ) -> u16x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self>
fn concat_swizzle_dyn_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, indices: u8x32<Self>, ) -> u16x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
indices: u8x32<Self>,
) -> u16x16<Self>
fn concat_swizzle_dyn_precise_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, indices: u8x32<Self>, ) -> u16x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
fn count_ones_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
fn count_zeros_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn saturating_add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn saturating_sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn mul_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn and_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn or_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn xor_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Compute the bitwise XOR of two vectors.
Sourcefn not_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
fn not_u16x16(self, a: u16x16<Self>) -> u16x16<Self>
Compute the bitwise NOT of the vector.
Sourcefn shl_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self>
fn shl_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn shlv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self>
fn shr_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn shrv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u16x16(self, a: u16x16<Self>) -> u16
fn reduce_max_u16x16(self, a: u16x16<Self>) -> u16
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u16x16(self, a: u16x16<Self>) -> u16
fn reduce_min_u16x16(self, a: u16x16<Self>) -> u16
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u16x16(self, a: u16x16<Self>) -> u16
fn reduce_sum_u16x16(self, a: u16x16<Self>) -> u16
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u16x16(self, a: u16x16<Self>) -> u16
fn reduce_product_u16x16(self, a: u16x16<Self>) -> u16
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn max_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn min_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
c: u16x16<Self>,
) -> u16x16<Self>
fn clamp_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, c: u16x16<Self>, ) -> u16x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
fn simd_eq_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
fn simd_ne_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
fn simd_lt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
fn simd_le_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
fn simd_ge_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
fn simd_gt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn zip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn zip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn unzip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
fn unzip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u16x16<Self>, u16x16<Self>)
fn interleave_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, ) -> (u16x16<Self>, u16x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u16x16<Self>, u16x16<Self>)
fn deinterleave_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, ) -> (u16x16<Self>, u16x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u16x16(
self,
a: mask16x16<Self>,
b: u16x16<Self>,
c: u16x16<Self>,
) -> u16x16<Self>
fn select_u16x16( self, a: mask16x16<Self>, b: u16x16<Self>, c: u16x16<Self>, ) -> u16x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_u16x16(self, a: u16x16<Self>) -> (u32x8<Self>, u32x8<Self>)
fn widen_u16x16(self, a: u16x16<Self>) -> (u32x8<Self>, u32x8<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u32x8<Self>, u32x8<Self>)
fn widening_mul_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, ) -> (u32x8<Self>, u32x8<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> (u32x8<Self>, u32x8<Self>)
fn widening_add_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, ) -> (u32x8<Self>, u32x8<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u16x16(self, a: u16x16<Self>) -> u32x8<Self>
fn pairwise_widening_add_u16x16(self, a: u16x16<Self>) -> u32x8<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u32x8<Self>
fn pairwise_dot_product_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, ) -> u32x8<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self>
fn narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u16x16(
self,
a: u16x16<Self>,
b: u16x16<Self>,
) -> u8x32<Self>
fn saturating_narrow_u16x16( self, a: u16x16<Self>, b: u16x16<Self>, ) -> u8x32<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self>
fn relaxed_narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn splat_mask16x16(self, val: bool) -> mask16x16<Self>
fn splat_mask16x16(self, val: bool) -> mask16x16<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask16x16(self, bits: u64) -> mask16x16<Self>
fn from_bitmask_mask16x16(self, bits: u64) -> mask16x16<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask16x16(self, a: mask16x16<Self>) -> u64
fn to_bitmask_mask16x16(self, a: mask16x16<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self>
fn and_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, ) -> mask16x16<Self>
Compute the logical AND of two masks.
Sourcefn or_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self>
fn or_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self>
fn xor_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, ) -> mask16x16<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self>
fn not_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self>
fn reverse_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
c: mask16x16<Self>,
) -> mask16x16<Self>
fn select_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, c: mask16x16<Self>, ) -> mask16x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self>
fn simd_eq_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, ) -> mask16x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask16x16<Self>
fn simd_ne_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, ) -> mask16x16<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask16x16(self, a: mask16x16<Self>) -> bool
fn any_true_mask16x16(self, a: mask16x16<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask16x16(self, a: mask16x16<Self>) -> bool
fn all_true_mask16x16(self, a: mask16x16<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask16x16(self, a: mask16x16<Self>) -> bool
fn any_false_mask16x16(self, a: mask16x16<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask16x16(self, a: mask16x16<Self>) -> bool
fn all_false_mask16x16(self, a: mask16x16<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn widen_mask16x16(self, a: mask16x16<Self>) -> (mask32x8<Self>, mask32x8<Self>)
fn widen_mask16x16(self, a: mask16x16<Self>) -> (mask32x8<Self>, mask32x8<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn narrow_mask16x16(
self,
a: mask16x16<Self>,
b: mask16x16<Self>,
) -> mask8x32<Self>
fn narrow_mask16x16( self, a: mask16x16<Self>, b: mask16x16<Self>, ) -> mask8x32<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
fn abs_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i32x8(self, val: i32) -> i32x8<Self>
fn splat_i32x8(self, val: i32) -> i32x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
fn reverse_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i32x8<const SHIFT: usize>(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i32x8<Self>
fn slide_within_blocks_i32x8<const SHIFT: usize>( self, a: i32x8<Self>, b: i32x8<Self>, ) -> i32x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i32x8(
self,
a: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self>
fn swizzle_dyn_within_blocks_i32x8( self, a: i32x8<Self>, indices: u8x32<Self>, ) -> i32x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i32x8(self, a: i32x8<Self>, indices: u8x32<Self>) -> i32x8<Self>
fn swizzle_dyn_i32x8(self, a: i32x8<Self>, indices: u8x32<Self>) -> i32x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i32x8(
self,
a: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self>
fn swizzle_dyn_precise_i32x8( self, a: i32x8<Self>, indices: u8x32<Self>, ) -> i32x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self>
fn concat_swizzle_dyn_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, indices: u8x32<Self>, ) -> i32x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
indices: u8x32<Self>,
) -> i32x8<Self>
fn concat_swizzle_dyn_precise_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, indices: u8x32<Self>, ) -> i32x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
fn count_ones_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
fn count_zeros_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn saturating_add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn saturating_sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn mul_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn and_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn or_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn xor_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self>
fn shl_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn shlv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self>
fn shr_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn shrv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i32x8(self, a: i32x8<Self>) -> i32
fn reduce_max_i32x8(self, a: i32x8<Self>) -> i32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i32x8(self, a: i32x8<Self>) -> i32
fn reduce_min_i32x8(self, a: i32x8<Self>) -> i32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i32x8(self, a: i32x8<Self>) -> i32
fn reduce_sum_i32x8(self, a: i32x8<Self>) -> i32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i32x8(self, a: i32x8<Self>) -> i32
fn reduce_product_i32x8(self, a: i32x8<Self>) -> i32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn max_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn min_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
c: i32x8<Self>,
) -> i32x8<Self>
fn clamp_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, c: i32x8<Self>, ) -> i32x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
fn simd_eq_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
fn simd_ne_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
fn simd_lt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
fn simd_le_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
fn simd_ge_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
fn simd_gt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn zip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn zip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn unzip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
fn unzip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i32x8<Self>, i32x8<Self>)
fn interleave_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, ) -> (i32x8<Self>, i32x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i32x8<Self>, i32x8<Self>)
fn deinterleave_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, ) -> (i32x8<Self>, i32x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i32x8(
self,
a: mask32x8<Self>,
b: i32x8<Self>,
c: i32x8<Self>,
) -> i32x8<Self>
fn select_i32x8( self, a: mask32x8<Self>, b: i32x8<Self>, c: i32x8<Self>, ) -> i32x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
fn neg_i32x8(self, a: i32x8<Self>) -> i32x8<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn widen_i32x8(self, a: i32x8<Self>) -> (i64x4<Self>, i64x4<Self>)
fn widen_i32x8(self, a: i32x8<Self>) -> (i64x4<Self>, i64x4<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i64x4<Self>, i64x4<Self>)
fn widening_mul_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, ) -> (i64x4<Self>, i64x4<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> (i64x4<Self>, i64x4<Self>)
fn widening_add_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, ) -> (i64x4<Self>, i64x4<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i32x8(self, a: i32x8<Self>) -> i64x4<Self>
fn pairwise_widening_add_i32x8(self, a: i32x8<Self>) -> i64x4<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i32x8(
self,
a: i32x8<Self>,
b: i32x8<Self>,
) -> i64x4<Self>
fn pairwise_dot_product_i32x8( self, a: i32x8<Self>, b: i32x8<Self>, ) -> i64x4<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self>
fn narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self>
fn saturating_narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self>
fn relaxed_narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f32_i32x8(self, a: i32x8<Self>) -> f32x8<Self>
fn cvt_f32_i32x8(self, a: i32x8<Self>) -> f32x8<Self>
Convert each signed 32-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn abs_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
fn abs_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u32x8(self, val: u32) -> u32x8<Self>
fn splat_u32x8(self, val: u32) -> u32x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
fn reverse_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u32x8<const SHIFT: usize>(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u32x8<Self>
fn slide_within_blocks_u32x8<const SHIFT: usize>( self, a: u32x8<Self>, b: u32x8<Self>, ) -> u32x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u32x8(
self,
a: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self>
fn swizzle_dyn_within_blocks_u32x8( self, a: u32x8<Self>, indices: u8x32<Self>, ) -> u32x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u32x8(self, a: u32x8<Self>, indices: u8x32<Self>) -> u32x8<Self>
fn swizzle_dyn_u32x8(self, a: u32x8<Self>, indices: u8x32<Self>) -> u32x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u32x8(
self,
a: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self>
fn swizzle_dyn_precise_u32x8( self, a: u32x8<Self>, indices: u8x32<Self>, ) -> u32x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self>
fn concat_swizzle_dyn_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, indices: u8x32<Self>, ) -> u32x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
indices: u8x32<Self>,
) -> u32x8<Self>
fn concat_swizzle_dyn_precise_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, indices: u8x32<Self>, ) -> u32x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
fn count_ones_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
fn count_zeros_u32x8(self, a: u32x8<Self>) -> u32x8<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn saturating_add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn saturating_sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn mul_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn and_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn or_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn xor_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self>
fn shl_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn shlv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self>
fn shr_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn shrv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u32x8(self, a: u32x8<Self>) -> u32
fn reduce_max_u32x8(self, a: u32x8<Self>) -> u32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u32x8(self, a: u32x8<Self>) -> u32
fn reduce_min_u32x8(self, a: u32x8<Self>) -> u32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u32x8(self, a: u32x8<Self>) -> u32
fn reduce_sum_u32x8(self, a: u32x8<Self>) -> u32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u32x8(self, a: u32x8<Self>) -> u32
fn reduce_product_u32x8(self, a: u32x8<Self>) -> u32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn max_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn min_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
c: u32x8<Self>,
) -> u32x8<Self>
fn clamp_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, c: u32x8<Self>, ) -> u32x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
fn simd_eq_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
fn simd_ne_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
fn simd_lt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
fn simd_le_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
fn simd_ge_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
fn simd_gt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn zip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn zip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn unzip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
fn unzip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u32x8<Self>, u32x8<Self>)
fn interleave_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, ) -> (u32x8<Self>, u32x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u32x8<Self>, u32x8<Self>)
fn deinterleave_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, ) -> (u32x8<Self>, u32x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u32x8(
self,
a: mask32x8<Self>,
b: u32x8<Self>,
c: u32x8<Self>,
) -> u32x8<Self>
fn select_u32x8( self, a: mask32x8<Self>, b: u32x8<Self>, c: u32x8<Self>, ) -> u32x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_u32x8(self, a: u32x8<Self>) -> (u64x4<Self>, u64x4<Self>)
fn widen_u32x8(self, a: u32x8<Self>) -> (u64x4<Self>, u64x4<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u64x4<Self>, u64x4<Self>)
fn widening_mul_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, ) -> (u64x4<Self>, u64x4<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> (u64x4<Self>, u64x4<Self>)
fn widening_add_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, ) -> (u64x4<Self>, u64x4<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u32x8(self, a: u32x8<Self>) -> u64x4<Self>
fn pairwise_widening_add_u32x8(self, a: u32x8<Self>) -> u64x4<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u32x8(
self,
a: u32x8<Self>,
b: u32x8<Self>,
) -> u64x4<Self>
fn pairwise_dot_product_u32x8( self, a: u32x8<Self>, b: u32x8<Self>, ) -> u64x4<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self>
fn narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self>
fn saturating_narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self>
fn relaxed_narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f32_u32x8(self, a: u32x8<Self>) -> f32x8<Self>
fn cvt_f32_u32x8(self, a: u32x8<Self>) -> f32x8<Self>
Convert each unsigned 32-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_mask32x8(self, val: bool) -> mask32x8<Self>
fn splat_mask32x8(self, val: bool) -> mask32x8<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask32x8(self, bits: u64) -> mask32x8<Self>
fn from_bitmask_mask32x8(self, bits: u64) -> mask32x8<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask32x8(self, a: mask32x8<Self>) -> u64
fn to_bitmask_mask32x8(self, a: mask32x8<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self>
fn and_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self>
Compute the logical AND of two masks.
Sourcefn or_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self>
fn or_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self>
fn xor_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self>
fn not_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self>
fn reverse_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
c: mask32x8<Self>,
) -> mask32x8<Self>
fn select_mask32x8( self, a: mask32x8<Self>, b: mask32x8<Self>, c: mask32x8<Self>, ) -> mask32x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x8<Self>
fn simd_eq_mask32x8( self, a: mask32x8<Self>, b: mask32x8<Self>, ) -> mask32x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask32x8<Self>
fn simd_ne_mask32x8( self, a: mask32x8<Self>, b: mask32x8<Self>, ) -> mask32x8<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask32x8(self, a: mask32x8<Self>) -> bool
fn any_true_mask32x8(self, a: mask32x8<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask32x8(self, a: mask32x8<Self>) -> bool
fn all_true_mask32x8(self, a: mask32x8<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask32x8(self, a: mask32x8<Self>) -> bool
fn any_false_mask32x8(self, a: mask32x8<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask32x8(self, a: mask32x8<Self>) -> bool
fn all_false_mask32x8(self, a: mask32x8<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn widen_mask32x8(self, a: mask32x8<Self>) -> (mask64x4<Self>, mask64x4<Self>)
fn widen_mask32x8(self, a: mask32x8<Self>) -> (mask64x4<Self>, mask64x4<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn narrow_mask32x8(
self,
a: mask32x8<Self>,
b: mask32x8<Self>,
) -> mask16x16<Self>
fn narrow_mask32x8( self, a: mask32x8<Self>, b: mask32x8<Self>, ) -> mask16x16<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn abs_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_f64x4(self, val: f64) -> f64x4<Self>
fn splat_f64x4(self, val: f64) -> f64x4<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn reverse_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_f64x4<const SHIFT: usize>(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> f64x4<Self>
fn slide_within_blocks_f64x4<const SHIFT: usize>( self, a: f64x4<Self>, b: f64x4<Self>, ) -> f64x4<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_f64x4(
self,
a: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self>
fn swizzle_dyn_within_blocks_f64x4( self, a: f64x4<Self>, indices: u8x32<Self>, ) -> f64x4<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_f64x4(self, a: f64x4<Self>, indices: u8x32<Self>) -> f64x4<Self>
fn swizzle_dyn_f64x4(self, a: f64x4<Self>, indices: u8x32<Self>) -> f64x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_f64x4(
self,
a: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self>
fn swizzle_dyn_precise_f64x4( self, a: f64x4<Self>, indices: u8x32<Self>, ) -> f64x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self>
fn concat_swizzle_dyn_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, indices: u8x32<Self>, ) -> f64x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
indices: u8x32<Self>,
) -> f64x4<Self>
fn concat_swizzle_dyn_precise_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, indices: u8x32<Self>, ) -> f64x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn sqrt_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn sqrt_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Compute the square root of each element.
Negative elements other than -0.0 will become NaN.
Sourcefn approximate_recip_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn approximate_recip_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Compute an approximate reciprocal (1. / x) for each element.
This uses a fast hardware estimate where available, and falls back to exact division otherwise.
On x86 for f32, this has a relative error less than 1.5 × 2^-12. On AArch64 (f32 and f64), this has a relative error less than 2^-8. The precision of this operation may change as new platform support is added.
Sourcefn add_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn add_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Add two vectors element-wise.
Sourcefn sub_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn sub_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Subtract two vectors element-wise.
Sourcefn mul_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn mul_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Multiply two vectors element-wise.
Sourcefn div_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn div_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Divide two vectors element-wise.
Sourcefn copysign_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn copysign_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Return a vector with the magnitude of a and the sign of b for each element.
This operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit.
Sourcefn reduce_max_f64x4(self, a: f64x4<Self>) -> f64
fn reduce_max_f64x4(self, a: f64x4<Self>) -> f64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_f64x4(self, a: f64x4<Self>) -> f64
fn reduce_min_f64x4(self, a: f64x4<Self>) -> f64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_max_precise_f64x4(self, a: f64x4<Self>) -> f64
fn reduce_max_precise_f64x4(self, a: f64x4<Self>) -> f64
Return the maximum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_max.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_min_precise_f64x4(self, a: f64x4<Self>) -> f64
fn reduce_min_precise_f64x4(self, a: f64x4<Self>) -> f64
Return the minimum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_min.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_sum_f64x4(self, a: f64x4<Self>) -> f64
fn reduce_sum_f64x4(self, a: f64x4<Self>) -> f64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_f64x4(self, a: f64x4<Self>) -> f64
fn reduce_product_f64x4(self, a: f64x4<Self>) -> f64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn max_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn min_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn max_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn max_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Return the element-wise maximum of two vectors.
For integer vectors, this operation is the same as max.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn min_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn min_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Return the element-wise minimum of two vectors.
For integer vectors, this operation is the same as min.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn clamp_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self>
fn clamp_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>, ) -> f64x4<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
fn simd_eq_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
fn simd_ne_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
fn simd_lt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
fn simd_le_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
fn simd_ge_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
fn simd_gt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn zip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn zip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn unzip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
fn unzip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> (f64x4<Self>, f64x4<Self>)
fn interleave_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, ) -> (f64x4<Self>, f64x4<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
) -> (f64x4<Self>, f64x4<Self>)
fn deinterleave_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, ) -> (f64x4<Self>, f64x4<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn mul_add_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self>
fn mul_add_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>, ) -> f64x4<Self>
Compute (a * b) + c (fused multiply-add) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors.
Sourcefn mul_add_precise_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self>
fn mul_add_precise_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>, ) -> f64x4<Self>
Compute (a * b) + c for each element, with a single rounding at the end.
The result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than mul_add on platforms without fused multiply-add instructions, including WebAssembly.
§Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn mul_sub_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self>
fn mul_sub_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>, ) -> f64x4<Self>
Compute (a * b) - c (fused multiply-subtract) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors.
Sourcefn mul_sub_precise_f64x4(
self,
a: f64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self>
fn mul_sub_precise_f64x4( self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>, ) -> f64x4<Self>
Compute (a * b) - c for each element, with a single rounding at the end.
The result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than mul_sub on platforms without fused multiply-add instructions, including WebAssembly.
# Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn floor_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn floor_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Return the largest integer less than or equal to each element, that is, round towards negative infinity.
Sourcefn ceil_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn ceil_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Return the smallest integer greater than or equal to each element, that is, round towards positive infinity.
Sourcefn round_ties_even_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn round_ties_even_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Round each element to the nearest integer, with ties rounding to the nearest even integer.
Sourcefn round_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn round_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Round each element to the nearest integer, with ties rounding away from zero.
§Performance considerations
Only AArch64 has native instructions for this operation. round has to be emulated on all other platforms which is around 2-4x slower than round_ties_even. Prefer using round_ties_even if possible.
Sourcefn fract_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn fract_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Return the fractional part of each element.
This is equivalent to a - a.trunc().
Sourcefn trunc_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn trunc_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Return the integer part of each element, rounding towards zero.
Sourcefn to_degrees_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn to_degrees_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Converts radians to degrees.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn to_radians_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
fn to_radians_f64x4(self, a: f64x4<Self>) -> f64x4<Self>
Converts degrees to radians.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn select_f64x4(
self,
a: mask64x4<Self>,
b: f64x4<Self>,
c: f64x4<Self>,
) -> f64x4<Self>
fn select_f64x4( self, a: mask64x4<Self>, b: f64x4<Self>, c: f64x4<Self>, ) -> f64x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self>
fn narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
Values are rounded to the nearest representable f32, with ties resolved to even; overflow produces signed infinity.This is the same as the as operator, and follows the IEEE 754 narrowing behavior in round-to-even mode.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self>
fn saturating_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
For floating-point vectors this is identical to narrow, including its rounding and overflow behavior.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self>
fn relaxed_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
For floating-point vectors this is identical to narrow, including its rounding and overflow behavior.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_u64_f64x4(self, a: f64x4<Self>) -> u64x4<Self>
fn cvt_u64_f64x4(self, a: f64x4<Self>) -> u64x4<Self>
Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_u64_precise_f64x4(self, a: f64x4<Self>) -> u64x4<Self>
fn cvt_u64_precise_f64x4(self, a: f64x4<Self>) -> u64x4<Self>
Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn cvt_i64_f64x4(self, a: f64x4<Self>) -> i64x4<Self>
fn cvt_i64_f64x4(self, a: f64x4<Self>) -> i64x4<Self>
Convert each floating-point element to a signed 64-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_i64_precise_f64x4(self, a: f64x4<Self>) -> i64x4<Self>
fn cvt_i64_precise_f64x4(self, a: f64x4<Self>) -> i64x4<Self>
Convert each floating-point element to a signed 64-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn abs_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
fn abs_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i64x4(self, val: i64) -> i64x4<Self>
fn splat_i64x4(self, val: i64) -> i64x4<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
fn reverse_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i64x4<const SHIFT: usize>(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> i64x4<Self>
fn slide_within_blocks_i64x4<const SHIFT: usize>( self, a: i64x4<Self>, b: i64x4<Self>, ) -> i64x4<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i64x4(
self,
a: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self>
fn swizzle_dyn_within_blocks_i64x4( self, a: i64x4<Self>, indices: u8x32<Self>, ) -> i64x4<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i64x4(self, a: i64x4<Self>, indices: u8x32<Self>) -> i64x4<Self>
fn swizzle_dyn_i64x4(self, a: i64x4<Self>, indices: u8x32<Self>) -> i64x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i64x4(
self,
a: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self>
fn swizzle_dyn_precise_i64x4( self, a: i64x4<Self>, indices: u8x32<Self>, ) -> i64x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self>
fn concat_swizzle_dyn_i64x4( self, a: i64x4<Self>, b: i64x4<Self>, indices: u8x32<Self>, ) -> i64x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
indices: u8x32<Self>,
) -> i64x4<Self>
fn concat_swizzle_dyn_precise_i64x4( self, a: i64x4<Self>, b: i64x4<Self>, indices: u8x32<Self>, ) -> i64x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
fn count_ones_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
fn count_zeros_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn saturating_add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn saturating_sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn mul_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn and_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn or_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn xor_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self>
fn shl_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn shlv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self>
fn shr_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn shrv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i64x4(self, a: i64x4<Self>) -> i64
fn reduce_max_i64x4(self, a: i64x4<Self>) -> i64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i64x4(self, a: i64x4<Self>) -> i64
fn reduce_min_i64x4(self, a: i64x4<Self>) -> i64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i64x4(self, a: i64x4<Self>) -> i64
fn reduce_sum_i64x4(self, a: i64x4<Self>) -> i64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i64x4(self, a: i64x4<Self>) -> i64
fn reduce_product_i64x4(self, a: i64x4<Self>) -> i64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn max_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn min_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
c: i64x4<Self>,
) -> i64x4<Self>
fn clamp_i64x4( self, a: i64x4<Self>, b: i64x4<Self>, c: i64x4<Self>, ) -> i64x4<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
fn simd_eq_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
fn simd_ne_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
fn simd_lt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
fn simd_le_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
fn simd_ge_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
fn simd_gt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn zip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn zip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn unzip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
fn unzip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> (i64x4<Self>, i64x4<Self>)
fn interleave_i64x4( self, a: i64x4<Self>, b: i64x4<Self>, ) -> (i64x4<Self>, i64x4<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i64x4(
self,
a: i64x4<Self>,
b: i64x4<Self>,
) -> (i64x4<Self>, i64x4<Self>)
fn deinterleave_i64x4( self, a: i64x4<Self>, b: i64x4<Self>, ) -> (i64x4<Self>, i64x4<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i64x4(
self,
a: mask64x4<Self>,
b: i64x4<Self>,
c: i64x4<Self>,
) -> i64x4<Self>
fn select_i64x4( self, a: mask64x4<Self>, b: i64x4<Self>, c: i64x4<Self>, ) -> i64x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
fn neg_i64x4(self, a: i64x4<Self>) -> i64x4<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self>
fn narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self>
fn saturating_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self>
fn relaxed_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f64_i64x4(self, a: i64x4<Self>) -> f64x4<Self>
fn cvt_f64_i64x4(self, a: i64x4<Self>) -> f64x4<Self>
Convert each signed 64-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn abs_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
fn abs_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u64x4(self, val: u64) -> u64x4<Self>
fn splat_u64x4(self, val: u64) -> u64x4<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
fn reverse_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u64x4<const SHIFT: usize>(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> u64x4<Self>
fn slide_within_blocks_u64x4<const SHIFT: usize>( self, a: u64x4<Self>, b: u64x4<Self>, ) -> u64x4<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u64x4(
self,
a: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self>
fn swizzle_dyn_within_blocks_u64x4( self, a: u64x4<Self>, indices: u8x32<Self>, ) -> u64x4<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u64x4(self, a: u64x4<Self>, indices: u8x32<Self>) -> u64x4<Self>
fn swizzle_dyn_u64x4(self, a: u64x4<Self>, indices: u8x32<Self>) -> u64x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u64x4(
self,
a: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self>
fn swizzle_dyn_precise_u64x4( self, a: u64x4<Self>, indices: u8x32<Self>, ) -> u64x4<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self>
fn concat_swizzle_dyn_u64x4( self, a: u64x4<Self>, b: u64x4<Self>, indices: u8x32<Self>, ) -> u64x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
indices: u8x32<Self>,
) -> u64x4<Self>
fn concat_swizzle_dyn_precise_u64x4( self, a: u64x4<Self>, b: u64x4<Self>, indices: u8x32<Self>, ) -> u64x4<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
fn count_ones_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
fn count_zeros_u64x4(self, a: u64x4<Self>) -> u64x4<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn saturating_add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn saturating_sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn mul_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn and_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn or_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn xor_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self>
fn shl_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn shlv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self>
fn shr_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn shrv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u64x4(self, a: u64x4<Self>) -> u64
fn reduce_max_u64x4(self, a: u64x4<Self>) -> u64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u64x4(self, a: u64x4<Self>) -> u64
fn reduce_min_u64x4(self, a: u64x4<Self>) -> u64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u64x4(self, a: u64x4<Self>) -> u64
fn reduce_sum_u64x4(self, a: u64x4<Self>) -> u64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u64x4(self, a: u64x4<Self>) -> u64
fn reduce_product_u64x4(self, a: u64x4<Self>) -> u64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn max_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn min_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
c: u64x4<Self>,
) -> u64x4<Self>
fn clamp_u64x4( self, a: u64x4<Self>, b: u64x4<Self>, c: u64x4<Self>, ) -> u64x4<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
fn simd_eq_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
fn simd_ne_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
fn simd_lt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
fn simd_le_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
fn simd_ge_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
fn simd_gt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn zip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn zip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn unzip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
fn unzip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> (u64x4<Self>, u64x4<Self>)
fn interleave_u64x4( self, a: u64x4<Self>, b: u64x4<Self>, ) -> (u64x4<Self>, u64x4<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u64x4(
self,
a: u64x4<Self>,
b: u64x4<Self>,
) -> (u64x4<Self>, u64x4<Self>)
fn deinterleave_u64x4( self, a: u64x4<Self>, b: u64x4<Self>, ) -> (u64x4<Self>, u64x4<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u64x4(
self,
a: mask64x4<Self>,
b: u64x4<Self>,
c: u64x4<Self>,
) -> u64x4<Self>
fn select_u64x4( self, a: mask64x4<Self>, b: u64x4<Self>, c: u64x4<Self>, ) -> u64x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self>
fn narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self>
fn saturating_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self>
fn relaxed_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f64_u64x4(self, a: u64x4<Self>) -> f64x4<Self>
fn cvt_f64_u64x4(self, a: u64x4<Self>) -> f64x4<Self>
Convert each unsigned 64-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_mask64x4(self, val: bool) -> mask64x4<Self>
fn splat_mask64x4(self, val: bool) -> mask64x4<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask64x4(self, bits: u64) -> mask64x4<Self>
fn from_bitmask_mask64x4(self, bits: u64) -> mask64x4<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask64x4(self, a: mask64x4<Self>) -> u64
fn to_bitmask_mask64x4(self, a: mask64x4<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self>
fn and_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self>
Compute the logical AND of two masks.
Sourcefn or_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self>
fn or_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self>
fn xor_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self>
fn not_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self>
fn reverse_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
c: mask64x4<Self>,
) -> mask64x4<Self>
fn select_mask64x4( self, a: mask64x4<Self>, b: mask64x4<Self>, c: mask64x4<Self>, ) -> mask64x4<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x4<Self>
fn simd_eq_mask64x4( self, a: mask64x4<Self>, b: mask64x4<Self>, ) -> mask64x4<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask64x4(
self,
a: mask64x4<Self>,
b: mask64x4<Self>,
) -> mask64x4<Self>
fn simd_ne_mask64x4( self, a: mask64x4<Self>, b: mask64x4<Self>, ) -> mask64x4<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask64x4(self, a: mask64x4<Self>) -> bool
fn any_true_mask64x4(self, a: mask64x4<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask64x4(self, a: mask64x4<Self>) -> bool
fn all_true_mask64x4(self, a: mask64x4<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask64x4(self, a: mask64x4<Self>) -> bool
fn any_false_mask64x4(self, a: mask64x4<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask64x4(self, a: mask64x4<Self>) -> bool
fn all_false_mask64x4(self, a: mask64x4<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn narrow_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask32x8<Self>
fn narrow_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask32x8<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn abs_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_f32x16(self, val: f32) -> f32x16<Self>
fn splat_f32x16(self, val: f32) -> f32x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn reverse_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_f32x16<const SHIFT: usize>(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> f32x16<Self>
fn slide_within_blocks_f32x16<const SHIFT: usize>( self, a: f32x16<Self>, b: f32x16<Self>, ) -> f32x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_f32x16(
self,
a: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self>
fn swizzle_dyn_within_blocks_f32x16( self, a: f32x16<Self>, indices: u8x64<Self>, ) -> f32x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_f32x16(
self,
a: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self>
fn swizzle_dyn_f32x16( self, a: f32x16<Self>, indices: u8x64<Self>, ) -> f32x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_f32x16(
self,
a: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self>
fn swizzle_dyn_precise_f32x16( self, a: f32x16<Self>, indices: u8x64<Self>, ) -> f32x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self>
fn concat_swizzle_dyn_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, indices: u8x64<Self>, ) -> f32x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
indices: u8x64<Self>,
) -> f32x16<Self>
fn concat_swizzle_dyn_precise_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, indices: u8x64<Self>, ) -> f32x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn neg_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn neg_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Negate each element of the vector.
Sourcefn sqrt_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn sqrt_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Compute the square root of each element.
Negative elements other than -0.0 will become NaN.
Sourcefn approximate_recip_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn approximate_recip_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Compute an approximate reciprocal (1. / x) for each element.
This uses a fast hardware estimate where available, and falls back to exact division otherwise.
On x86 for f32, this has a relative error less than 1.5 × 2^-12. On AArch64 (f32 and f64), this has a relative error less than 2^-8. The precision of this operation may change as new platform support is added.
Sourcefn add_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn add_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Add two vectors element-wise.
Sourcefn sub_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn sub_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Subtract two vectors element-wise.
Sourcefn mul_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn mul_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Multiply two vectors element-wise.
Sourcefn div_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn div_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Divide two vectors element-wise.
Sourcefn copysign_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn copysign_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Return a vector with the magnitude of a and the sign of b for each element.
This operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit.
Sourcefn reduce_max_f32x16(self, a: f32x16<Self>) -> f32
fn reduce_max_f32x16(self, a: f32x16<Self>) -> f32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_f32x16(self, a: f32x16<Self>) -> f32
fn reduce_min_f32x16(self, a: f32x16<Self>) -> f32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_max_precise_f32x16(self, a: f32x16<Self>) -> f32
fn reduce_max_precise_f32x16(self, a: f32x16<Self>) -> f32
Return the maximum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_max.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_min_precise_f32x16(self, a: f32x16<Self>) -> f32
fn reduce_min_precise_f32x16(self, a: f32x16<Self>) -> f32
Return the minimum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_min.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_sum_f32x16(self, a: f32x16<Self>) -> f32
fn reduce_sum_f32x16(self, a: f32x16<Self>) -> f32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_f32x16(self, a: f32x16<Self>) -> f32
fn reduce_product_f32x16(self, a: f32x16<Self>) -> f32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn max_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn min_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn max_precise_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn max_precise_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Return the element-wise maximum of two vectors.
For integer vectors, this operation is the same as max.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn min_precise_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn min_precise_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Return the element-wise minimum of two vectors.
For integer vectors, this operation is the same as min.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn clamp_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self>
fn clamp_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>, ) -> f32x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
fn simd_eq_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
fn simd_ne_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
fn simd_lt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
fn simd_le_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
fn simd_ge_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
fn simd_gt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn zip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn zip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn unzip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
fn unzip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> (f32x16<Self>, f32x16<Self>)
fn interleave_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, ) -> (f32x16<Self>, f32x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
) -> (f32x16<Self>, f32x16<Self>)
fn deinterleave_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, ) -> (f32x16<Self>, f32x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn mul_add_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self>
fn mul_add_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>, ) -> f32x16<Self>
Compute (a * b) + c (fused multiply-add) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors.
Sourcefn mul_add_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self>
fn mul_add_precise_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>, ) -> f32x16<Self>
Compute (a * b) + c for each element, with a single rounding at the end.
The result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than mul_add on platforms without fused multiply-add instructions, including WebAssembly.
§Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn mul_sub_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self>
fn mul_sub_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>, ) -> f32x16<Self>
Compute (a * b) - c (fused multiply-subtract) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors.
Sourcefn mul_sub_precise_f32x16(
self,
a: f32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self>
fn mul_sub_precise_f32x16( self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>, ) -> f32x16<Self>
Compute (a * b) - c for each element, with a single rounding at the end.
The result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than mul_sub on platforms without fused multiply-add instructions, including WebAssembly.
# Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn floor_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn floor_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Return the largest integer less than or equal to each element, that is, round towards negative infinity.
Sourcefn ceil_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn ceil_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Return the smallest integer greater than or equal to each element, that is, round towards positive infinity.
Sourcefn round_ties_even_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn round_ties_even_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Round each element to the nearest integer, with ties rounding to the nearest even integer.
Sourcefn round_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn round_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Round each element to the nearest integer, with ties rounding away from zero.
§Performance considerations
Only AArch64 has native instructions for this operation. round has to be emulated on all other platforms which is around 2-4x slower than round_ties_even. Prefer using round_ties_even if possible.
Sourcefn fract_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn fract_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Return the fractional part of each element.
This is equivalent to a - a.trunc().
Sourcefn trunc_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn trunc_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Return the integer part of each element, rounding towards zero.
Sourcefn to_degrees_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn to_degrees_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Converts radians to degrees.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn to_radians_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
fn to_radians_f32x16(self, a: f32x16<Self>) -> f32x16<Self>
Converts degrees to radians.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn select_f32x16(
self,
a: mask32x16<Self>,
b: f32x16<Self>,
c: f32x16<Self>,
) -> f32x16<Self>
fn select_f32x16( self, a: mask32x16<Self>, b: f32x16<Self>, c: f32x16<Self>, ) -> f32x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_f32x16(self, a: f32x16<Self>) -> (f64x8<Self>, f64x8<Self>)
fn widen_f32x16(self, a: f32x16<Self>) -> (f64x8<Self>, f64x8<Self>)
Widen every f32 lane exactly into two same-width f64 vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn cvt_u32_f32x16(self, a: f32x16<Self>) -> u32x16<Self>
fn cvt_u32_f32x16(self, a: f32x16<Self>) -> u32x16<Self>
Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
On x86 platforms below AVX-512, this operation will still be slower than converting to i32, because there is no native instruction for converting to u32.
If you know your values fit within range of an i32, you should convert to an i32 and cast to your desired datatype afterwards.
Sourcefn cvt_u32_precise_f32x16(self, a: f32x16<Self>) -> u32x16<Self>
fn cvt_u32_precise_f32x16(self, a: f32x16<Self>) -> u32x16<Self>
Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn cvt_i32_f32x16(self, a: f32x16<Self>) -> i32x16<Self>
fn cvt_i32_f32x16(self, a: f32x16<Self>) -> i32x16<Self>
Convert each floating-point element to a signed 32-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_i32_precise_f32x16(self, a: f32x16<Self>) -> i32x16<Self>
fn cvt_i32_precise_f32x16(self, a: f32x16<Self>) -> i32x16<Self>
Convert each floating-point element to a signed 32-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn abs_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
fn abs_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i8x64(self, val: i8) -> i8x64<Self>
fn splat_i8x64(self, val: i8) -> i8x64<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
fn reverse_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i8x64<const SHIFT: usize>(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> i8x64<Self>
fn slide_within_blocks_i8x64<const SHIFT: usize>( self, a: i8x64<Self>, b: i8x64<Self>, ) -> i8x64<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i8x64(
self,
a: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self>
fn swizzle_dyn_within_blocks_i8x64( self, a: i8x64<Self>, indices: u8x64<Self>, ) -> i8x64<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i8x64(self, a: i8x64<Self>, indices: u8x64<Self>) -> i8x64<Self>
fn swizzle_dyn_i8x64(self, a: i8x64<Self>, indices: u8x64<Self>) -> i8x64<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i8x64(
self,
a: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self>
fn swizzle_dyn_precise_i8x64( self, a: i8x64<Self>, indices: u8x64<Self>, ) -> i8x64<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self>
fn concat_swizzle_dyn_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, indices: u8x64<Self>, ) -> i8x64<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
indices: u8x64<Self>,
) -> i8x64<Self>
fn concat_swizzle_dyn_precise_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, indices: u8x64<Self>, ) -> i8x64<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
fn count_ones_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
fn count_zeros_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn saturating_add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn saturating_sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn mul_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn and_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn or_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn xor_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self>
fn shl_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn shlv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self>
fn shr_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn shrv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i8x64(self, a: i8x64<Self>) -> i8
fn reduce_max_i8x64(self, a: i8x64<Self>) -> i8
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i8x64(self, a: i8x64<Self>) -> i8
fn reduce_min_i8x64(self, a: i8x64<Self>) -> i8
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i8x64(self, a: i8x64<Self>) -> i8
fn reduce_sum_i8x64(self, a: i8x64<Self>) -> i8
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i8x64(self, a: i8x64<Self>) -> i8
fn reduce_product_i8x64(self, a: i8x64<Self>) -> i8
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn max_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn min_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
c: i8x64<Self>,
) -> i8x64<Self>
fn clamp_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, c: i8x64<Self>, ) -> i8x64<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
fn simd_eq_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
fn simd_ne_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
fn simd_lt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
fn simd_le_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
fn simd_ge_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
fn simd_gt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn zip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn zip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn unzip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
fn unzip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i8x64<Self>, i8x64<Self>)
fn interleave_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, ) -> (i8x64<Self>, i8x64<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i8x64<Self>, i8x64<Self>)
fn deinterleave_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, ) -> (i8x64<Self>, i8x64<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i8x64(
self,
a: mask8x64<Self>,
b: i8x64<Self>,
c: i8x64<Self>,
) -> i8x64<Self>
fn select_i8x64( self, a: mask8x64<Self>, b: i8x64<Self>, c: i8x64<Self>, ) -> i8x64<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
fn neg_i8x64(self, a: i8x64<Self>) -> i8x64<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn widen_i8x64(self, a: i8x64<Self>) -> (i16x32<Self>, i16x32<Self>)
fn widen_i8x64(self, a: i8x64<Self>) -> (i16x32<Self>, i16x32<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i16x32<Self>, i16x32<Self>)
fn widening_mul_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, ) -> (i16x32<Self>, i16x32<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> (i16x32<Self>, i16x32<Self>)
fn widening_add_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, ) -> (i16x32<Self>, i16x32<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i8x64(self, a: i8x64<Self>) -> i16x32<Self>
fn pairwise_widening_add_i8x64(self, a: i8x64<Self>) -> i16x32<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i8x64(
self,
a: i8x64<Self>,
b: i8x64<Self>,
) -> i16x32<Self>
fn pairwise_dot_product_i8x64( self, a: i8x64<Self>, b: i8x64<Self>, ) -> i16x32<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn abs_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
fn abs_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u8x64(self, val: u8) -> u8x64<Self>
fn splat_u8x64(self, val: u8) -> u8x64<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
fn reverse_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u8x64<const SHIFT: usize>(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> u8x64<Self>
fn slide_within_blocks_u8x64<const SHIFT: usize>( self, a: u8x64<Self>, b: u8x64<Self>, ) -> u8x64<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u8x64(
self,
a: u8x64<Self>,
indices: u8x64<Self>,
) -> u8x64<Self>
fn swizzle_dyn_within_blocks_u8x64( self, a: u8x64<Self>, indices: u8x64<Self>, ) -> u8x64<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn count_ones_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
fn count_ones_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
fn count_zeros_u8x64(self, a: u8x64<Self>) -> u8x64<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn saturating_add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn saturating_sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn mul_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn and_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn or_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn xor_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self>
fn shl_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn shlv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self>
fn shr_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn shrv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u8x64(self, a: u8x64<Self>) -> u8
fn reduce_max_u8x64(self, a: u8x64<Self>) -> u8
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u8x64(self, a: u8x64<Self>) -> u8
fn reduce_min_u8x64(self, a: u8x64<Self>) -> u8
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u8x64(self, a: u8x64<Self>) -> u8
fn reduce_sum_u8x64(self, a: u8x64<Self>) -> u8
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u8x64(self, a: u8x64<Self>) -> u8
fn reduce_product_u8x64(self, a: u8x64<Self>) -> u8
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn max_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn min_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
c: u8x64<Self>,
) -> u8x64<Self>
fn clamp_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, c: u8x64<Self>, ) -> u8x64<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
fn simd_eq_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
fn simd_ne_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
fn simd_lt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
fn simd_le_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
fn simd_ge_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
fn simd_gt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn zip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn zip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn unzip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
fn unzip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u8x64<Self>, u8x64<Self>)
fn interleave_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, ) -> (u8x64<Self>, u8x64<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u8x64<Self>, u8x64<Self>)
fn deinterleave_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, ) -> (u8x64<Self>, u8x64<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u8x64(
self,
a: mask8x64<Self>,
b: u8x64<Self>,
c: u8x64<Self>,
) -> u8x64<Self>
fn select_u8x64( self, a: mask8x64<Self>, b: u8x64<Self>, c: u8x64<Self>, ) -> u8x64<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_u8x64(self, a: u8x64<Self>) -> (u16x32<Self>, u16x32<Self>)
fn widen_u8x64(self, a: u8x64<Self>) -> (u16x32<Self>, u16x32<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u16x32<Self>, u16x32<Self>)
fn widening_mul_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, ) -> (u16x32<Self>, u16x32<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> (u16x32<Self>, u16x32<Self>)
fn widening_add_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, ) -> (u16x32<Self>, u16x32<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u8x64(self, a: u8x64<Self>) -> u16x32<Self>
fn pairwise_widening_add_u8x64(self, a: u8x64<Self>) -> u16x32<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u8x64(
self,
a: u8x64<Self>,
b: u8x64<Self>,
) -> u16x32<Self>
fn pairwise_dot_product_u8x64( self, a: u8x64<Self>, b: u8x64<Self>, ) -> u16x32<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn splat_mask8x64(self, val: bool) -> mask8x64<Self>
fn splat_mask8x64(self, val: bool) -> mask8x64<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask8x64(self, bits: u64) -> mask8x64<Self>
fn from_bitmask_mask8x64(self, bits: u64) -> mask8x64<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask8x64(self, a: mask8x64<Self>) -> u64
fn to_bitmask_mask8x64(self, a: mask8x64<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self>
fn and_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self>
Compute the logical AND of two masks.
Sourcefn or_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self>
fn or_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self>
fn xor_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self>
fn not_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self>
fn reverse_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
c: mask8x64<Self>,
) -> mask8x64<Self>
fn select_mask8x64( self, a: mask8x64<Self>, b: mask8x64<Self>, c: mask8x64<Self>, ) -> mask8x64<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
) -> mask8x64<Self>
fn simd_eq_mask8x64( self, a: mask8x64<Self>, b: mask8x64<Self>, ) -> mask8x64<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask8x64(
self,
a: mask8x64<Self>,
b: mask8x64<Self>,
) -> mask8x64<Self>
fn simd_ne_mask8x64( self, a: mask8x64<Self>, b: mask8x64<Self>, ) -> mask8x64<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask8x64(self, a: mask8x64<Self>) -> bool
fn any_true_mask8x64(self, a: mask8x64<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask8x64(self, a: mask8x64<Self>) -> bool
fn all_true_mask8x64(self, a: mask8x64<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask8x64(self, a: mask8x64<Self>) -> bool
fn any_false_mask8x64(self, a: mask8x64<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask8x64(self, a: mask8x64<Self>) -> bool
fn all_false_mask8x64(self, a: mask8x64<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn widen_mask8x64(self, a: mask8x64<Self>) -> (mask16x32<Self>, mask16x32<Self>)
fn widen_mask8x64(self, a: mask8x64<Self>) -> (mask16x32<Self>, mask16x32<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
fn abs_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i16x32(self, val: i16) -> i16x32<Self>
fn splat_i16x32(self, val: i16) -> i16x32<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
fn reverse_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i16x32<const SHIFT: usize>(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i16x32<Self>
fn slide_within_blocks_i16x32<const SHIFT: usize>( self, a: i16x32<Self>, b: i16x32<Self>, ) -> i16x32<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i16x32(
self,
a: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self>
fn swizzle_dyn_within_blocks_i16x32( self, a: i16x32<Self>, indices: u8x64<Self>, ) -> i16x32<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i16x32(
self,
a: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self>
fn swizzle_dyn_i16x32( self, a: i16x32<Self>, indices: u8x64<Self>, ) -> i16x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i16x32(
self,
a: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self>
fn swizzle_dyn_precise_i16x32( self, a: i16x32<Self>, indices: u8x64<Self>, ) -> i16x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self>
fn concat_swizzle_dyn_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, indices: u8x64<Self>, ) -> i16x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
indices: u8x64<Self>,
) -> i16x32<Self>
fn concat_swizzle_dyn_precise_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, indices: u8x64<Self>, ) -> i16x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
fn count_ones_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
fn count_zeros_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn saturating_add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn saturating_sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn mul_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn and_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn or_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn xor_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Compute the bitwise XOR of two vectors.
Sourcefn not_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
fn not_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
Compute the bitwise NOT of the vector.
Sourcefn shl_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self>
fn shl_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn shlv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self>
fn shr_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn shrv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i16x32(self, a: i16x32<Self>) -> i16
fn reduce_max_i16x32(self, a: i16x32<Self>) -> i16
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i16x32(self, a: i16x32<Self>) -> i16
fn reduce_min_i16x32(self, a: i16x32<Self>) -> i16
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i16x32(self, a: i16x32<Self>) -> i16
fn reduce_sum_i16x32(self, a: i16x32<Self>) -> i16
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i16x32(self, a: i16x32<Self>) -> i16
fn reduce_product_i16x32(self, a: i16x32<Self>) -> i16
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn max_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn min_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
c: i16x32<Self>,
) -> i16x32<Self>
fn clamp_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, c: i16x32<Self>, ) -> i16x32<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
fn simd_eq_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
fn simd_ne_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
fn simd_lt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
fn simd_le_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
fn simd_ge_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
fn simd_gt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn zip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn zip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn unzip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
fn unzip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i16x32<Self>, i16x32<Self>)
fn interleave_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, ) -> (i16x32<Self>, i16x32<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i16x32<Self>, i16x32<Self>)
fn deinterleave_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, ) -> (i16x32<Self>, i16x32<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i16x32(
self,
a: mask16x32<Self>,
b: i16x32<Self>,
c: i16x32<Self>,
) -> i16x32<Self>
fn select_i16x32( self, a: mask16x32<Self>, b: i16x32<Self>, c: i16x32<Self>, ) -> i16x32<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
fn neg_i16x32(self, a: i16x32<Self>) -> i16x32<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn widen_i16x32(self, a: i16x32<Self>) -> (i32x16<Self>, i32x16<Self>)
fn widen_i16x32(self, a: i16x32<Self>) -> (i32x16<Self>, i32x16<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i32x16<Self>, i32x16<Self>)
fn widening_mul_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, ) -> (i32x16<Self>, i32x16<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> (i32x16<Self>, i32x16<Self>)
fn widening_add_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, ) -> (i32x16<Self>, i32x16<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i16x32(self, a: i16x32<Self>) -> i32x16<Self>
fn pairwise_widening_add_i16x32(self, a: i16x32<Self>) -> i32x16<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i32x16<Self>
fn pairwise_dot_product_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, ) -> i32x16<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self>
fn narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i16x32(
self,
a: i16x32<Self>,
b: i16x32<Self>,
) -> i8x64<Self>
fn saturating_narrow_i16x32( self, a: i16x32<Self>, b: i16x32<Self>, ) -> i8x64<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self>
fn relaxed_narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn abs_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
fn abs_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u16x32(self, val: u16) -> u16x32<Self>
fn splat_u16x32(self, val: u16) -> u16x32<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
fn reverse_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u16x32<const SHIFT: usize>(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u16x32<Self>
fn slide_within_blocks_u16x32<const SHIFT: usize>( self, a: u16x32<Self>, b: u16x32<Self>, ) -> u16x32<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u16x32(
self,
a: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self>
fn swizzle_dyn_within_blocks_u16x32( self, a: u16x32<Self>, indices: u8x64<Self>, ) -> u16x32<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u16x32(
self,
a: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self>
fn swizzle_dyn_u16x32( self, a: u16x32<Self>, indices: u8x64<Self>, ) -> u16x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u16x32(
self,
a: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self>
fn swizzle_dyn_precise_u16x32( self, a: u16x32<Self>, indices: u8x64<Self>, ) -> u16x32<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self>
fn concat_swizzle_dyn_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, indices: u8x64<Self>, ) -> u16x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
indices: u8x64<Self>,
) -> u16x32<Self>
fn concat_swizzle_dyn_precise_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, indices: u8x64<Self>, ) -> u16x32<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
fn count_ones_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
fn count_zeros_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn saturating_add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn saturating_sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn mul_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn and_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn or_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn xor_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Compute the bitwise XOR of two vectors.
Sourcefn not_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
fn not_u16x32(self, a: u16x32<Self>) -> u16x32<Self>
Compute the bitwise NOT of the vector.
Sourcefn shl_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self>
fn shl_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn shlv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self>
fn shr_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn shrv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u16x32(self, a: u16x32<Self>) -> u16
fn reduce_max_u16x32(self, a: u16x32<Self>) -> u16
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u16x32(self, a: u16x32<Self>) -> u16
fn reduce_min_u16x32(self, a: u16x32<Self>) -> u16
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u16x32(self, a: u16x32<Self>) -> u16
fn reduce_sum_u16x32(self, a: u16x32<Self>) -> u16
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u16x32(self, a: u16x32<Self>) -> u16
fn reduce_product_u16x32(self, a: u16x32<Self>) -> u16
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn max_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn min_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
c: u16x32<Self>,
) -> u16x32<Self>
fn clamp_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, c: u16x32<Self>, ) -> u16x32<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
fn simd_eq_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
fn simd_ne_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
fn simd_lt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
fn simd_le_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
fn simd_ge_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
fn simd_gt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn zip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn zip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn unzip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
fn unzip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u16x32<Self>, u16x32<Self>)
fn interleave_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, ) -> (u16x32<Self>, u16x32<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u16x32<Self>, u16x32<Self>)
fn deinterleave_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, ) -> (u16x32<Self>, u16x32<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u16x32(
self,
a: mask16x32<Self>,
b: u16x32<Self>,
c: u16x32<Self>,
) -> u16x32<Self>
fn select_u16x32( self, a: mask16x32<Self>, b: u16x32<Self>, c: u16x32<Self>, ) -> u16x32<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_u16x32(self, a: u16x32<Self>) -> (u32x16<Self>, u32x16<Self>)
fn widen_u16x32(self, a: u16x32<Self>) -> (u32x16<Self>, u32x16<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u32x16<Self>, u32x16<Self>)
fn widening_mul_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, ) -> (u32x16<Self>, u32x16<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> (u32x16<Self>, u32x16<Self>)
fn widening_add_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, ) -> (u32x16<Self>, u32x16<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u16x32(self, a: u16x32<Self>) -> u32x16<Self>
fn pairwise_widening_add_u16x32(self, a: u16x32<Self>) -> u32x16<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u32x16<Self>
fn pairwise_dot_product_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, ) -> u32x16<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self>
fn narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u16x32(
self,
a: u16x32<Self>,
b: u16x32<Self>,
) -> u8x64<Self>
fn saturating_narrow_u16x32( self, a: u16x32<Self>, b: u16x32<Self>, ) -> u8x64<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self>
fn relaxed_narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn splat_mask16x32(self, val: bool) -> mask16x32<Self>
fn splat_mask16x32(self, val: bool) -> mask16x32<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask16x32(self, bits: u64) -> mask16x32<Self>
fn from_bitmask_mask16x32(self, bits: u64) -> mask16x32<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask16x32(self, a: mask16x32<Self>) -> u64
fn to_bitmask_mask16x32(self, a: mask16x32<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self>
fn and_mask16x32( self, a: mask16x32<Self>, b: mask16x32<Self>, ) -> mask16x32<Self>
Compute the logical AND of two masks.
Sourcefn or_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self>
fn or_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self>
fn xor_mask16x32( self, a: mask16x32<Self>, b: mask16x32<Self>, ) -> mask16x32<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self>
fn not_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self>
fn reverse_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
c: mask16x32<Self>,
) -> mask16x32<Self>
fn select_mask16x32( self, a: mask16x32<Self>, b: mask16x32<Self>, c: mask16x32<Self>, ) -> mask16x32<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self>
fn simd_eq_mask16x32( self, a: mask16x32<Self>, b: mask16x32<Self>, ) -> mask16x32<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask16x32<Self>
fn simd_ne_mask16x32( self, a: mask16x32<Self>, b: mask16x32<Self>, ) -> mask16x32<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask16x32(self, a: mask16x32<Self>) -> bool
fn any_true_mask16x32(self, a: mask16x32<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask16x32(self, a: mask16x32<Self>) -> bool
fn all_true_mask16x32(self, a: mask16x32<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask16x32(self, a: mask16x32<Self>) -> bool
fn any_false_mask16x32(self, a: mask16x32<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask16x32(self, a: mask16x32<Self>) -> bool
fn all_false_mask16x32(self, a: mask16x32<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn widen_mask16x32(
self,
a: mask16x32<Self>,
) -> (mask32x16<Self>, mask32x16<Self>)
fn widen_mask16x32( self, a: mask16x32<Self>, ) -> (mask32x16<Self>, mask32x16<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn narrow_mask16x32(
self,
a: mask16x32<Self>,
b: mask16x32<Self>,
) -> mask8x64<Self>
fn narrow_mask16x32( self, a: mask16x32<Self>, b: mask16x32<Self>, ) -> mask8x64<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
fn abs_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i32x16(self, val: i32) -> i32x16<Self>
fn splat_i32x16(self, val: i32) -> i32x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
fn reverse_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i32x16<const SHIFT: usize>(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i32x16<Self>
fn slide_within_blocks_i32x16<const SHIFT: usize>( self, a: i32x16<Self>, b: i32x16<Self>, ) -> i32x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i32x16(
self,
a: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self>
fn swizzle_dyn_within_blocks_i32x16( self, a: i32x16<Self>, indices: u8x64<Self>, ) -> i32x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i32x16(
self,
a: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self>
fn swizzle_dyn_i32x16( self, a: i32x16<Self>, indices: u8x64<Self>, ) -> i32x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i32x16(
self,
a: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self>
fn swizzle_dyn_precise_i32x16( self, a: i32x16<Self>, indices: u8x64<Self>, ) -> i32x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self>
fn concat_swizzle_dyn_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, indices: u8x64<Self>, ) -> i32x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
indices: u8x64<Self>,
) -> i32x16<Self>
fn concat_swizzle_dyn_precise_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, indices: u8x64<Self>, ) -> i32x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
fn count_ones_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
fn count_zeros_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn saturating_add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn saturating_sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn mul_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn and_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn or_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn xor_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Compute the bitwise XOR of two vectors.
Sourcefn not_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
fn not_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
Compute the bitwise NOT of the vector.
Sourcefn shl_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self>
fn shl_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn shlv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self>
fn shr_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn shrv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i32x16(self, a: i32x16<Self>) -> i32
fn reduce_max_i32x16(self, a: i32x16<Self>) -> i32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i32x16(self, a: i32x16<Self>) -> i32
fn reduce_min_i32x16(self, a: i32x16<Self>) -> i32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i32x16(self, a: i32x16<Self>) -> i32
fn reduce_sum_i32x16(self, a: i32x16<Self>) -> i32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i32x16(self, a: i32x16<Self>) -> i32
fn reduce_product_i32x16(self, a: i32x16<Self>) -> i32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn max_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn min_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
c: i32x16<Self>,
) -> i32x16<Self>
fn clamp_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, c: i32x16<Self>, ) -> i32x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
fn simd_eq_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
fn simd_ne_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
fn simd_lt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
fn simd_le_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
fn simd_ge_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
fn simd_gt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn zip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn zip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn unzip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
fn unzip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i32x16<Self>, i32x16<Self>)
fn interleave_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, ) -> (i32x16<Self>, i32x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i32x16<Self>, i32x16<Self>)
fn deinterleave_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, ) -> (i32x16<Self>, i32x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i32x16(
self,
a: mask32x16<Self>,
b: i32x16<Self>,
c: i32x16<Self>,
) -> i32x16<Self>
fn select_i32x16( self, a: mask32x16<Self>, b: i32x16<Self>, c: i32x16<Self>, ) -> i32x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
fn neg_i32x16(self, a: i32x16<Self>) -> i32x16<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn widen_i32x16(self, a: i32x16<Self>) -> (i64x8<Self>, i64x8<Self>)
fn widen_i32x16(self, a: i32x16<Self>) -> (i64x8<Self>, i64x8<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i64x8<Self>, i64x8<Self>)
fn widening_mul_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, ) -> (i64x8<Self>, i64x8<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> (i64x8<Self>, i64x8<Self>)
fn widening_add_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, ) -> (i64x8<Self>, i64x8<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_i32x16(self, a: i32x16<Self>) -> i64x8<Self>
fn pairwise_widening_add_i32x16(self, a: i32x16<Self>) -> i64x8<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i64x8<Self>
fn pairwise_dot_product_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, ) -> i64x8<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self>
fn narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i32x16(
self,
a: i32x16<Self>,
b: i32x16<Self>,
) -> i16x32<Self>
fn saturating_narrow_i32x16( self, a: i32x16<Self>, b: i32x16<Self>, ) -> i16x32<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self>
fn relaxed_narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f32_i32x16(self, a: i32x16<Self>) -> f32x16<Self>
fn cvt_f32_i32x16(self, a: i32x16<Self>) -> f32x16<Self>
Convert each signed 32-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn abs_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
fn abs_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u32x16(self, val: u32) -> u32x16<Self>
fn splat_u32x16(self, val: u32) -> u32x16<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
fn reverse_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u32x16<const SHIFT: usize>(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u32x16<Self>
fn slide_within_blocks_u32x16<const SHIFT: usize>( self, a: u32x16<Self>, b: u32x16<Self>, ) -> u32x16<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u32x16(
self,
a: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self>
fn swizzle_dyn_within_blocks_u32x16( self, a: u32x16<Self>, indices: u8x64<Self>, ) -> u32x16<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u32x16(
self,
a: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self>
fn swizzle_dyn_u32x16( self, a: u32x16<Self>, indices: u8x64<Self>, ) -> u32x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u32x16(
self,
a: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self>
fn swizzle_dyn_precise_u32x16( self, a: u32x16<Self>, indices: u8x64<Self>, ) -> u32x16<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self>
fn concat_swizzle_dyn_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, indices: u8x64<Self>, ) -> u32x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
indices: u8x64<Self>,
) -> u32x16<Self>
fn concat_swizzle_dyn_precise_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, indices: u8x64<Self>, ) -> u32x16<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
fn count_ones_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
fn count_zeros_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn saturating_add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn saturating_sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn mul_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn and_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn or_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn xor_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Compute the bitwise XOR of two vectors.
Sourcefn not_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
fn not_u32x16(self, a: u32x16<Self>) -> u32x16<Self>
Compute the bitwise NOT of the vector.
Sourcefn shl_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self>
fn shl_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn shlv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self>
fn shr_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn shrv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u32x16(self, a: u32x16<Self>) -> u32
fn reduce_max_u32x16(self, a: u32x16<Self>) -> u32
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u32x16(self, a: u32x16<Self>) -> u32
fn reduce_min_u32x16(self, a: u32x16<Self>) -> u32
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u32x16(self, a: u32x16<Self>) -> u32
fn reduce_sum_u32x16(self, a: u32x16<Self>) -> u32
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u32x16(self, a: u32x16<Self>) -> u32
fn reduce_product_u32x16(self, a: u32x16<Self>) -> u32
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn max_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn min_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
c: u32x16<Self>,
) -> u32x16<Self>
fn clamp_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, c: u32x16<Self>, ) -> u32x16<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
fn simd_eq_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
fn simd_ne_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
fn simd_lt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
fn simd_le_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
fn simd_ge_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
fn simd_gt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn zip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn zip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn unzip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
fn unzip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u32x16<Self>, u32x16<Self>)
fn interleave_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, ) -> (u32x16<Self>, u32x16<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u32x16<Self>, u32x16<Self>)
fn deinterleave_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, ) -> (u32x16<Self>, u32x16<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u32x16(
self,
a: mask32x16<Self>,
b: u32x16<Self>,
c: u32x16<Self>,
) -> u32x16<Self>
fn select_u32x16( self, a: mask32x16<Self>, b: u32x16<Self>, c: u32x16<Self>, ) -> u32x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn widen_u32x16(self, a: u32x16<Self>) -> (u64x8<Self>, u64x8<Self>)
fn widen_u32x16(self, a: u32x16<Self>) -> (u64x8<Self>, u64x8<Self>)
Widen every lane into two same-width vectors.
The first result contains the widened lower lanes and the second contains the widened upper lanes.
Sourcefn widening_mul_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u64x8<Self>, u64x8<Self>)
fn widening_mul_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, ) -> (u64x8<Self>, u64x8<Self>)
Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn widening_add_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> (u64x8<Self>, u64x8<Self>)
fn widening_add_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, ) -> (u64x8<Self>, u64x8<Self>)
Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes.
Sourcefn pairwise_widening_add_u32x16(self, a: u32x16<Self>) -> u64x8<Self>
fn pairwise_widening_add_u32x16(self, a: u32x16<Self>) -> u64x8<Self>
Add adjacent integer lanes exactly into twice-wide lanes.
Output lane i is widen(a[2*i]) + widen(a[2*i+1]). The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.
For example, [1, 2, 3, 4, 5, 6, 7, 8] produces [3, 7, 11, 15]. See SimdIntWiden::pairwise_widening_add for supported types and examples.
Sourcefn pairwise_dot_product_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u64x8<Self>
fn pairwise_dot_product_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, ) -> u64x8<Self>
Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.
The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane i is widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1]); addition wraps in the destination type, including in debug builds.
For example, [1, 2, 3, 4, 5, 6, 7, 8] and [10, 20, 30, 40, 50, 60, 70, 80] produce [50, 250, 610, 1130]. See SimdIntWiden::pairwise_dot_product for examples.
Sourcefn narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self>
fn narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u32x16(
self,
a: u32x16<Self>,
b: u32x16<Self>,
) -> u16x32<Self>
fn saturating_narrow_u32x16( self, a: u32x16<Self>, b: u32x16<Self>, ) -> u16x32<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self>
fn relaxed_narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f32_u32x16(self, a: u32x16<Self>) -> f32x16<Self>
fn cvt_f32_u32x16(self, a: u32x16<Self>) -> f32x16<Self>
Convert each unsigned 32-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_mask32x16(self, val: bool) -> mask32x16<Self>
fn splat_mask32x16(self, val: bool) -> mask32x16<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask32x16(self, bits: u64) -> mask32x16<Self>
fn from_bitmask_mask32x16(self, bits: u64) -> mask32x16<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask32x16(self, a: mask32x16<Self>) -> u64
fn to_bitmask_mask32x16(self, a: mask32x16<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self>
fn and_mask32x16( self, a: mask32x16<Self>, b: mask32x16<Self>, ) -> mask32x16<Self>
Compute the logical AND of two masks.
Sourcefn or_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self>
fn or_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self>
fn xor_mask32x16( self, a: mask32x16<Self>, b: mask32x16<Self>, ) -> mask32x16<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self>
fn not_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self>
fn reverse_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
c: mask32x16<Self>,
) -> mask32x16<Self>
fn select_mask32x16( self, a: mask32x16<Self>, b: mask32x16<Self>, c: mask32x16<Self>, ) -> mask32x16<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self>
fn simd_eq_mask32x16( self, a: mask32x16<Self>, b: mask32x16<Self>, ) -> mask32x16<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask32x16<Self>
fn simd_ne_mask32x16( self, a: mask32x16<Self>, b: mask32x16<Self>, ) -> mask32x16<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask32x16(self, a: mask32x16<Self>) -> bool
fn any_true_mask32x16(self, a: mask32x16<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask32x16(self, a: mask32x16<Self>) -> bool
fn all_true_mask32x16(self, a: mask32x16<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask32x16(self, a: mask32x16<Self>) -> bool
fn any_false_mask32x16(self, a: mask32x16<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask32x16(self, a: mask32x16<Self>) -> bool
fn all_false_mask32x16(self, a: mask32x16<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn widen_mask32x16(self, a: mask32x16<Self>) -> (mask64x8<Self>, mask64x8<Self>)
fn widen_mask32x16(self, a: mask32x16<Self>) -> (mask64x8<Self>, mask64x8<Self>)
Widen each boolean lane into two masks of the same logical width, preserving its value.
The first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn narrow_mask32x16(
self,
a: mask32x16<Self>,
b: mask32x16<Self>,
) -> mask16x32<Self>
fn narrow_mask32x16( self, a: mask32x16<Self>, b: mask32x16<Self>, ) -> mask16x32<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Sourcefn abs_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn abs_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_f64x8(self, val: f64) -> f64x8<Self>
fn splat_f64x8(self, val: f64) -> f64x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn reverse_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_f64x8<const SHIFT: usize>(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> f64x8<Self>
fn slide_within_blocks_f64x8<const SHIFT: usize>( self, a: f64x8<Self>, b: f64x8<Self>, ) -> f64x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_f64x8(
self,
a: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self>
fn swizzle_dyn_within_blocks_f64x8( self, a: f64x8<Self>, indices: u8x64<Self>, ) -> f64x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_f64x8(self, a: f64x8<Self>, indices: u8x64<Self>) -> f64x8<Self>
fn swizzle_dyn_f64x8(self, a: f64x8<Self>, indices: u8x64<Self>) -> f64x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_f64x8(
self,
a: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self>
fn swizzle_dyn_precise_f64x8( self, a: f64x8<Self>, indices: u8x64<Self>, ) -> f64x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self>
fn concat_swizzle_dyn_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, indices: u8x64<Self>, ) -> f64x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
indices: u8x64<Self>,
) -> f64x8<Self>
fn concat_swizzle_dyn_precise_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, indices: u8x64<Self>, ) -> f64x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn sqrt_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn sqrt_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Compute the square root of each element.
Negative elements other than -0.0 will become NaN.
Sourcefn approximate_recip_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn approximate_recip_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Compute an approximate reciprocal (1. / x) for each element.
This uses a fast hardware estimate where available, and falls back to exact division otherwise.
On x86 for f32, this has a relative error less than 1.5 × 2^-12. On AArch64 (f32 and f64), this has a relative error less than 2^-8. The precision of this operation may change as new platform support is added.
Sourcefn add_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn add_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Add two vectors element-wise.
Sourcefn sub_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn sub_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Subtract two vectors element-wise.
Sourcefn mul_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn mul_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Multiply two vectors element-wise.
Sourcefn div_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn div_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Divide two vectors element-wise.
Sourcefn copysign_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn copysign_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Return a vector with the magnitude of a and the sign of b for each element.
This operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit.
Sourcefn reduce_max_f64x8(self, a: f64x8<Self>) -> f64
fn reduce_max_f64x8(self, a: f64x8<Self>) -> f64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_f64x8(self, a: f64x8<Self>) -> f64
fn reduce_min_f64x8(self, a: f64x8<Self>) -> f64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_max_precise_f64x8(self, a: f64x8<Self>) -> f64
fn reduce_max_precise_f64x8(self, a: f64x8<Self>) -> f64
Return the maximum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_max.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_min_precise_f64x8(self, a: f64x8<Self>) -> f64
fn reduce_min_precise_f64x8(self, a: f64x8<Self>) -> f64
Return the minimum element in the vector, ignoring quiet NaNs.
For integer vectors, this operation is the same as reduce_min.
For floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
If any lane is a signaling NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn reduce_sum_f64x8(self, a: f64x8<Self>) -> f64
fn reduce_sum_f64x8(self, a: f64x8<Self>) -> f64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_f64x8(self, a: f64x8<Self>) -> f64
fn reduce_product_f64x8(self, a: f64x8<Self>) -> f64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn max_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn min_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn max_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn max_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Return the element-wise maximum of two vectors.
For integer vectors, this operation is the same as max.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn min_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn min_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Return the element-wise minimum of two vectors.
For integer vectors, this operation is the same as min.
For floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
If a floating-point operand is a signaling NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand. Signaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don’t need to worry about them.
Sourcefn clamp_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self>
fn clamp_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>, ) -> f64x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
fn simd_eq_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
fn simd_ne_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
fn simd_lt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
fn simd_le_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
fn simd_ge_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
fn simd_gt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn zip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn zip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn unzip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
fn unzip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> (f64x8<Self>, f64x8<Self>)
fn interleave_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, ) -> (f64x8<Self>, f64x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
) -> (f64x8<Self>, f64x8<Self>)
fn deinterleave_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, ) -> (f64x8<Self>, f64x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn mul_add_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self>
fn mul_add_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>, ) -> f64x8<Self>
Compute (a * b) + c (fused multiply-add) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors.
Sourcefn mul_add_precise_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self>
fn mul_add_precise_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>, ) -> f64x8<Self>
Compute (a * b) + c for each element, with a single rounding at the end.
The result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than mul_add on platforms without fused multiply-add instructions, including WebAssembly.
§Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn mul_sub_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self>
fn mul_sub_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>, ) -> f64x8<Self>
Compute (a * b) - c (fused multiply-subtract) for each element.
Depending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors.
Sourcefn mul_sub_precise_f64x8(
self,
a: f64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self>
fn mul_sub_precise_f64x8( self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>, ) -> f64x8<Self>
Compute (a * b) - c for each element, with a single rounding at the end.
The result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than mul_sub on platforms without fused multiply-add instructions, including WebAssembly.
# Precision guarantees
This function is not susceptible to the bug in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.
On the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.
The exact NaN payloads as well as signaling NaNs are not preserved.
Sourcefn floor_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn floor_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Return the largest integer less than or equal to each element, that is, round towards negative infinity.
Sourcefn ceil_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn ceil_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Return the smallest integer greater than or equal to each element, that is, round towards positive infinity.
Sourcefn round_ties_even_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn round_ties_even_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Round each element to the nearest integer, with ties rounding to the nearest even integer.
Sourcefn round_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn round_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Round each element to the nearest integer, with ties rounding away from zero.
§Performance considerations
Only AArch64 has native instructions for this operation. round has to be emulated on all other platforms which is around 2-4x slower than round_ties_even. Prefer using round_ties_even if possible.
Sourcefn fract_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn fract_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Return the fractional part of each element.
This is equivalent to a - a.trunc().
Sourcefn trunc_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn trunc_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Return the integer part of each element, rounding towards zero.
Sourcefn to_degrees_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn to_degrees_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Converts radians to degrees.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn to_radians_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
fn to_radians_f64x8(self, a: f64x8<Self>) -> f64x8<Self>
Converts degrees to radians.
The precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next.
Sourcefn select_f64x8(
self,
a: mask64x8<Self>,
b: f64x8<Self>,
c: f64x8<Self>,
) -> f64x8<Self>
fn select_f64x8( self, a: mask64x8<Self>, b: f64x8<Self>, c: f64x8<Self>, ) -> f64x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self>
fn narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
Values are rounded to the nearest representable f32, with ties resolved to even; overflow produces signed infinity.This is the same as the as operator, and follows the IEEE 754 narrowing behavior in round-to-even mode.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self>
fn saturating_narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
For floating-point vectors this is identical to narrow, including its rounding and overflow behavior.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self>
fn relaxed_narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self>
Convert the lanes of two f64 vectors to f32 and concatenate them into one same-width vector.
For floating-point vectors this is identical to narrow, including its rounding and overflow behavior.
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_u64_f64x8(self, a: f64x8<Self>) -> u64x8<Self>
fn cvt_u64_f64x8(self, a: f64x8<Self>) -> u64x8<Self>
Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_u64_precise_f64x8(self, a: f64x8<Self>) -> u64x8<Self>
fn cvt_u64_precise_f64x8(self, a: f64x8<Self>) -> u64x8<Self>
Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn cvt_i64_f64x8(self, a: f64x8<Self>) -> i64x8<Self>
fn cvt_i64_f64x8(self, a: f64x8<Self>) -> i64x8<Self>
Convert each floating-point element to a signed 64-bit integer, truncating towards zero.
Out-of-range values or NaN will produce implementation-defined results.
Sourcefn cvt_i64_precise_f64x8(self, a: f64x8<Self>) -> i64x8<Self>
fn cvt_i64_precise_f64x8(self, a: f64x8<Self>) -> i64x8<Self>
Convert each floating-point element to a signed 64-bit integer, truncating towards zero.
Out-of-range values are saturated to the closest in-range value. NaN becomes 0.
Sourcefn abs_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
fn abs_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_i64x8(self, val: i64) -> i64x8<Self>
fn splat_i64x8(self, val: i64) -> i64x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
fn reverse_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_i64x8<const SHIFT: usize>(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> i64x8<Self>
fn slide_within_blocks_i64x8<const SHIFT: usize>( self, a: i64x8<Self>, b: i64x8<Self>, ) -> i64x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_i64x8(
self,
a: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self>
fn swizzle_dyn_within_blocks_i64x8( self, a: i64x8<Self>, indices: u8x64<Self>, ) -> i64x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_i64x8(self, a: i64x8<Self>, indices: u8x64<Self>) -> i64x8<Self>
fn swizzle_dyn_i64x8(self, a: i64x8<Self>, indices: u8x64<Self>) -> i64x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_i64x8(
self,
a: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self>
fn swizzle_dyn_precise_i64x8( self, a: i64x8<Self>, indices: u8x64<Self>, ) -> i64x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self>
fn concat_swizzle_dyn_i64x8( self, a: i64x8<Self>, b: i64x8<Self>, indices: u8x64<Self>, ) -> i64x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
indices: u8x64<Self>,
) -> i64x8<Self>
fn concat_swizzle_dyn_precise_i64x8( self, a: i64x8<Self>, b: i64x8<Self>, indices: u8x64<Self>, ) -> i64x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
fn count_ones_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
fn count_zeros_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn saturating_add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn saturating_sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn mul_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn and_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn or_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn xor_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self>
fn shl_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn shlv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self>
fn shr_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn shrv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_i64x8(self, a: i64x8<Self>) -> i64
fn reduce_max_i64x8(self, a: i64x8<Self>) -> i64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_i64x8(self, a: i64x8<Self>) -> i64
fn reduce_min_i64x8(self, a: i64x8<Self>) -> i64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_i64x8(self, a: i64x8<Self>) -> i64
fn reduce_sum_i64x8(self, a: i64x8<Self>) -> i64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_i64x8(self, a: i64x8<Self>) -> i64
fn reduce_product_i64x8(self, a: i64x8<Self>) -> i64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn max_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn min_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
c: i64x8<Self>,
) -> i64x8<Self>
fn clamp_i64x8( self, a: i64x8<Self>, b: i64x8<Self>, c: i64x8<Self>, ) -> i64x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
fn simd_eq_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
fn simd_ne_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
fn simd_lt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
fn simd_le_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
fn simd_ge_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
fn simd_gt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn zip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn zip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn unzip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
fn unzip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> (i64x8<Self>, i64x8<Self>)
fn interleave_i64x8( self, a: i64x8<Self>, b: i64x8<Self>, ) -> (i64x8<Self>, i64x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_i64x8(
self,
a: i64x8<Self>,
b: i64x8<Self>,
) -> (i64x8<Self>, i64x8<Self>)
fn deinterleave_i64x8( self, a: i64x8<Self>, b: i64x8<Self>, ) -> (i64x8<Self>, i64x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_i64x8(
self,
a: mask64x8<Self>,
b: i64x8<Self>,
c: i64x8<Self>,
) -> i64x8<Self>
fn select_i64x8( self, a: mask64x8<Self>, b: i64x8<Self>, c: i64x8<Self>, ) -> i64x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn neg_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
fn neg_i64x8(self, a: i64x8<Self>) -> i64x8<Self>
Negate each element of the vector, wrapping on overflow.
Sourcefn narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self>
fn narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self>
fn saturating_narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self>
fn relaxed_narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f64_i64x8(self, a: i64x8<Self>) -> f64x8<Self>
fn cvt_f64_i64x8(self, a: i64x8<Self>) -> f64x8<Self>
Convert each signed 64-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn abs_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
fn abs_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
Compute the absolute value of each element.
Unsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches i32::abs().
For floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero.
Sourcefn splat_u64x8(self, val: u64) -> u64x8<Self>
fn splat_u64x8(self, val: u64) -> u64x8<Self>
Create a SIMD vector with all elements set to the given value.
Sourcefn reverse_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
fn reverse_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
Reverse the order of the vector’s elements.
Sourcefn slide_within_blocks_u64x8<const SHIFT: usize>(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> u64x8<Self>
fn slide_within_blocks_u64x8<const SHIFT: usize>( self, a: u64x8<Self>, b: u64x8<Self>, ) -> u64x8<Self>
Like slide, but operates independently on each 128-bit block.
Sourcefn swizzle_dyn_within_blocks_u64x8(
self,
a: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self>
fn swizzle_dyn_within_blocks_u64x8( self, a: u64x8<Self>, indices: u8x64<Self>, ) -> u64x8<Self>
Dynamically swizzle this vector’s bytes independently within each 128-bit block.
The indices operand is a same-width byte vector. For each output byte, index values 0..=15 select the corresponding byte from the same 128-bit input block.
Out-of-range index behavior varies by platform.
Sourcefn swizzle_dyn_u64x8(self, a: u64x8<Self>, indices: u8x64<Self>) -> u64x8<Self>
fn swizzle_dyn_u64x8(self, a: u64x8<Self>, indices: u8x64<Self>) -> u64x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn swizzle_dyn_precise_u64x8(
self,
a: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self>
fn swizzle_dyn_precise_u64x8( self, a: u64x8<Self>, indices: u8x64<Self>, ) -> u64x8<Self>
Dynamically swizzle this vector’s bytes across the whole vector.
The indices operand is a same-width byte vector. For each output byte, index values within the vector’s byte length select the corresponding byte from the input vector. Out-of-range indices produce zero.
Sourcefn concat_swizzle_dyn_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self>
fn concat_swizzle_dyn_u64x8( self, a: u64x8<Self>, b: u64x8<Self>, indices: u8x64<Self>, ) -> u64x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices safely produce implementation-defined byte values.
Use SimdBase::concat_swizzle_dyn_precise if out-of-range indices must produce zero.
Sourcefn concat_swizzle_dyn_precise_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
indices: u8x64<Self>,
) -> u64x8<Self>
fn concat_swizzle_dyn_precise_u64x8( self, a: u64x8<Self>, b: u64x8<Self>, indices: u8x64<Self>, ) -> u64x8<Self>
Dynamically select bytes from the concatenation of this vector and rhs.
The indices operand is a same-width byte vector. For each output byte, index values within the concatenated vectors’ byte length select the corresponding byte: the first vector comes first, followed by rhs. Out-of-range indices produce zero.
Sourcefn count_ones_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
fn count_ones_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
Return the number of ones in the binary representation of each element.
Sourcefn count_zeros_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
fn count_zeros_u64x8(self, a: u64x8<Self>) -> u64x8<Self>
Return the number of zeros in the binary representation of each element.
Sourcefn add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Add two vectors element-wise, wrapping on overflow.
Sourcefn saturating_add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn saturating_add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Add two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86.
Sourcefn sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Subtract two vectors element-wise, wrapping on overflow.
Sourcefn saturating_sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn saturating_sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Subtract two vectors element-wise, saturating on overflow.
“Saturating” means that if the result is not representable, the closest representable value (either Element::MAX or Element::MIN) is returned.
On x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86.
Sourcefn mul_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn mul_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Multiply two vectors element-wise, wrapping on overflow.
Sourcefn and_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn and_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Compute the bitwise AND of two vectors.
Sourcefn or_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn or_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Compute the bitwise OR of two vectors.
Sourcefn xor_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn xor_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Compute the bitwise XOR of two vectors.
Sourcefn shl_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self>
fn shl_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shlv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn shlv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Shift each element left by the given number of bits.
Bits shifted out of the left side are discarded, and zeros are shifted in on the right.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn shr_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self>
fn shr_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self>
Shift each element right by the given number of bits.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
Sourcefn shrv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn shrv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Shift each element right by the corresponding element in another vector.
For unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.
When shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.
§Performance
This per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for u8 and i8 elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible.
Sourcefn reduce_max_u64x8(self, a: u64x8<Self>) -> u64
fn reduce_max_u64x8(self, a: u64x8<Self>) -> u64
Return the maximum element in the vector. Integer vectors always return the exact maximum.
For floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See reduce_max_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_min_u64x8(self, a: u64x8<Self>) -> u64
fn reduce_min_u64x8(self, a: u64x8<Self>) -> u64
Return the minimum element in the vector. Integer vectors always return the exact minimum.
For floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See reduce_min_precise for a version that ignores quiet NaNs.
If the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.
Sourcefn reduce_sum_u64x8(self, a: u64x8<Self>) -> u64
fn reduce_sum_u64x8(self, a: u64x8<Self>) -> u64
Return the sum of all elements in the vector. Integer addition wraps.
§Floating-point accuracy
For an input vector with N lanes, any lane’s contribution may be rounded at most log2(N) times.
For a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
Because floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See Taming Floating-Point Sums for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article’s terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different.
Sourcefn reduce_product_u64x8(self, a: u64x8<Self>) -> u64
fn reduce_product_u64x8(self, a: u64x8<Self>) -> u64
Return the product of all elements in the vector. Integer multiplication wraps.
§Floating-point behavior
For a vector with N elements, this operation performs N-1 roundings.
For a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as S::f32s independent of the selected SIMD level, because their lane counts can differ.
The result of this operation is not bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.
Intermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.
Because floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector.
Sourcefn max_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn max_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Return the element-wise maximum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See max_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn min_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn min_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Return the element-wise minimum of two vectors.
For floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined– it could be either the first or second operand. See min_precise for a version that returns the non-NaN operand if only one is NaN.
If one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one.
Sourcefn clamp_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
c: u64x8<Self>,
) -> u64x8<Self>
fn clamp_u64x8( self, a: u64x8<Self>, b: u64x8<Self>, c: u64x8<Self>, ) -> u64x8<Self>
Clamp each element to the interval [b, c].
If b > c, or b or c are NaN, the result is implementation-defined for that lane.
If a is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.
If one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.
§Panics
Panics with debug assertions if b > c for any element or any element of b or c is NaN.
Sourcefn simd_eq_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
fn simd_eq_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
fn simd_ne_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
For floating-point vectors, this follows Rust’s != semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn simd_lt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
fn simd_lt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for less than.
Returns a mask where each logical lane is true if a is less than b, and false if not.
Sourcefn simd_le_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
fn simd_le_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for less than or equal.
Returns a mask where each logical lane is true if a is less than or equal to b, and false if not.
Sourcefn simd_ge_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
fn simd_ge_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for greater than or equal.
Returns a mask where each logical lane is true if a is greater than or equal to b, and false if not.
Sourcefn simd_gt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
fn simd_gt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self>
Compare two vectors element-wise for greater than.
Returns a mask where each logical lane is true if a is greater than b, and false if not.
Sourcefn zip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn zip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Interleave the lower half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, b0, a1, b1].
Note: This operation is only useful if you need to discard elements a2, a3, b2, b3.
For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn zip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn zip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Interleave the upper half elements of two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a2, b2, a3, b3].
Note: This operation is only useful if you need to discard elements a0, a1, b0, b1.For fully interleaving two vectors prefer interleave,
which is faster than zip_low followed by zip_high on some platforms.
Sourcefn unzip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn unzip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Extract even-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a0, a2, b0, b2].
Note: This operation is only useful if you need to discard elements a1, a3, b1, b3.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn unzip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
fn unzip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>
Extract odd-indexed elements from two vectors.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns [a1, a3, b1, b3].
Note: This operation is only useful if you need to discard elements a0, a2, b0, b2.For fully deinterleaving two vectors prefer deinterleave,
which is faster than unzip_low followed by unzip_high on some platforms.
Sourcefn interleave_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> (u64x8<Self>, u64x8<Self>)
fn interleave_u64x8( self, a: u64x8<Self>, b: u64x8<Self>, ) -> (u64x8<Self>, u64x8<Self>)
Interleave two vectors.
The resulting vectors contain elements taken alternately from a and b, first filling the first result, and then the second.
The reverse of this operation is deinterleave.
For vectors [a0, a1, a2, a3] and [b0, b1, b2, b3], returns ([a0, b0, a1, b1], [a2, b2, a3, b3]).
Sourcefn deinterleave_u64x8(
self,
a: u64x8<Self>,
b: u64x8<Self>,
) -> (u64x8<Self>, u64x8<Self>)
fn deinterleave_u64x8( self, a: u64x8<Self>, b: u64x8<Self>, ) -> (u64x8<Self>, u64x8<Self>)
Deinterleave two vectors.
The first result contains all even-indexed elements from a followed by all even-indexed elements from b. The second result contains all odd-indexed elements from a followed by all odd-indexed elements from b.
The reverse of this operation is interleave.
For vectors [a0, b0, a1, b1] and [a2, b2, a3, b3], returns ([a0, a1, a2, a3], [b0, b1, b2, b3]).
Sourcefn select_u64x8(
self,
a: mask64x8<Self>,
b: u64x8<Self>,
c: u64x8<Self>,
) -> u64x8<Self>
fn select_u64x8( self, a: mask64x8<Self>, b: u64x8<Self>, c: u64x8<Self>, ) -> u64x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self>
fn narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self>
Truncate the lanes of two vectors and concatenate them into one same-width vector.
Each lane retains its low destination-width bits. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn saturating_narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self>
fn saturating_narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self>
Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.
Each lane is clamped to the destination type’s range. a provides the lower result lanes and b provides the upper result lanes.
Sourcefn relaxed_narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self>
fn relaxed_narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self>
Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.
Inputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).
a provides the lower result lanes and b provides the upper result lanes.
Sourcefn cvt_f64_u64x8(self, a: u64x8<Self>) -> f64x8<Self>
fn cvt_f64_u64x8(self, a: u64x8<Self>) -> f64x8<Self>
Convert each unsigned 64-bit integer element to a floating-point value.
Values that cannot be exactly represented are rounded to the nearest representable value.
Sourcefn splat_mask64x8(self, val: bool) -> mask64x8<Self>
fn splat_mask64x8(self, val: bool) -> mask64x8<Self>
Create a SIMD mask with all lanes set from the given boolean value.
Sourcefn from_bitmask_mask64x8(self, bits: u64) -> mask64x8<Self>
fn from_bitmask_mask64x8(self, bits: u64) -> mask64x8<Self>
Create a SIMD mask from a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored.
Sourcefn to_bitmask_mask64x8(self, a: mask64x8<Self>) -> u64
fn to_bitmask_mask64x8(self, a: mask64x8<Self>) -> u64
Convert a SIMD mask to a compact bitmask.
Bit i maps to lane i, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared.
Sourcefn and_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self>
fn and_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self>
Compute the logical AND of two masks.
Sourcefn or_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self>
fn or_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self>
Compute the logical OR of two masks.
Sourcefn xor_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self>
fn xor_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self>
Compute the logical XOR of two masks.
Sourcefn not_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self>
fn not_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self>
Compute the logical NOT of the mask.
Sourcefn reverse_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self>
fn reverse_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self>
Reverse the order of the mask’s logical lanes.
Sourcefn select_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
c: mask64x8<Self>,
) -> mask64x8<Self>
fn select_mask64x8( self, a: mask64x8<Self>, b: mask64x8<Self>, c: mask64x8<Self>, ) -> mask64x8<Self>
Select elements from b and c based on the mask operand a.
This operation’s behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the Select trait’s documentation for more information.
Sourcefn simd_eq_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask64x8<Self>
fn simd_eq_mask64x8( self, a: mask64x8<Self>, b: mask64x8<Self>, ) -> mask64x8<Self>
Compare two vectors element-wise for equality.
Returns a mask where each logical lane is true if the corresponding elements are equal, and false if not.
Sourcefn simd_ne_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask64x8<Self>
fn simd_ne_mask64x8( self, a: mask64x8<Self>, b: mask64x8<Self>, ) -> mask64x8<Self>
Compare two masks element-wise for inequality.
Returns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.
This is equivalent to negating the mask returned by simd_eq.
Sourcefn any_true_mask64x8(self, a: mask64x8<Self>) -> bool
fn any_true_mask64x8(self, a: mask64x8<Self>) -> bool
Returns true if any logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_true_mask64x8(self, a: mask64x8<Self>) -> bool
fn all_true_mask64x8(self, a: mask64x8<Self>) -> bool
Returns true if all logical lanes in this mask are true.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn any_false_mask64x8(self, a: mask64x8<Self>) -> bool
fn any_false_mask64x8(self, a: mask64x8<Self>) -> bool
Returns true if any logical lanes in this mask are false.
This is logically equivalent to !all_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn all_false_mask64x8(self, a: mask64x8<Self>) -> bool
fn all_false_mask64x8(self, a: mask64x8<Self>) -> bool
Returns true if all logical lanes in this mask are false.
This is logically equivalent to !any_true, but may be faster.
Masks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).
Behavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements’ width, the mask vector’s width, or library version.
The behavior is also not guaranteed to be logically consistent for such non-canonical masks. any_true may not return the same result as !all_false, and all_true may not return the same result as !any_false.
The select operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation.
Sourcefn narrow_mask64x8(
self,
a: mask64x8<Self>,
b: mask64x8<Self>,
) -> mask32x16<Self>
fn narrow_mask64x8( self, a: mask64x8<Self>, b: mask64x8<Self>, ) -> mask32x16<Self>
Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.
a supplies the lower result lanes and b supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior.
Dyn Compatibility§
This trait is not dyn compatible.
In older versions of Rust, dyn compatibility was called "object safety".
Implementors§
Source§impl Simd for Avx2
Available on x86 or x86-64 only.
impl Simd for Avx2
type f32s = f32x8<Avx2>
type f64s = f64x4<Avx2>
type u8s = u8x32<Avx2>
type i8s = i8x32<Avx2>
type u16s = u16x16<Avx2>
type i16s = i16x16<Avx2>
type u32s = u32x8<Avx2>
type i32s = i32x8<Avx2>
type u64s = u64x4<Avx2>
type i64s = i64x4<Avx2>
type mask8s = mask8x32<Avx2>
type mask16s = mask16x16<Avx2>
type mask32s = mask32x8<Avx2>
type mask64s = mask64x4<Avx2>
Source§impl Simd for Avx512
Available on x86 or x86-64 only.
impl Simd for Avx512
type f32s = f32x16<Avx512>
type f64s = f64x8<Avx512>
type u8s = u8x64<Avx512>
type i8s = i8x64<Avx512>
type u16s = u16x32<Avx512>
type i16s = i16x32<Avx512>
type u32s = u32x16<Avx512>
type i32s = i32x16<Avx512>
type u64s = u64x8<Avx512>
type i64s = i64x8<Avx512>
type mask8s = mask8x64<Avx512>
type mask16s = mask16x32<Avx512>
type mask32s = mask32x16<Avx512>
type mask64s = mask64x8<Avx512>
Source§impl Simd for Fallback
Available on crate feature force_support_fallback or neither AArch64 and target feature neon, nor target feature fxsr and target feature sse2 and (x86 or x86-64), nor WebAssembly and target feature simd128 only.
impl Simd for Fallback
force_support_fallback or neither AArch64 and target feature neon, nor target feature fxsr and target feature sse2 and (x86 or x86-64), nor WebAssembly and target feature simd128 only.