fearless_simd/generated/

simd_trait.rs

// Copyright 2025 the Fearless_SIMD Authors
// SPDX-License-Identifier: Apache-2.0 OR MIT

// This file is autogenerated by fearless_simd_gen

use crate::{
    Bytes, ExtractToken, Level, MaskNarrow, MaskWiden, Select, SimdCvtFloat, SimdCvtTruncate,
    SimdElement, SimdFloatElement, SimdFrom, SimdIntElement, SimdIntWiden, SimdInto, SimdNarrow,
    SimdWiden, seal::Seal,
};
use crate::{
    f32x4, f32x8, f32x16, f64x2, f64x4, f64x8, i8x16, i8x32, i8x64, i16x8, i16x16, i16x32, i32x4,
    i32x8, i32x16, i64x2, i64x4, i64x8, mask8x16, mask8x32, mask8x64, mask16x8, mask16x16,
    mask16x32, mask32x4, mask32x8, mask32x16, mask64x2, mask64x4, mask64x8, u8x16, u8x32, u8x64,
    u16x8, u16x16, u16x32, u32x4, u32x8, u32x16, u64x2, u64x4, u64x8,
};
use core::fmt::Debug;
#[doc = r" The main SIMD trait, implemented by all SIMD token types."]
#[doc = r""]
#[doc = r#" Each implementor of this trait (e.g. `Avx2`, `Sse4_2`, `Sse2`, `Neon`, `Fallback`) is a zero-sized "token" type"#]
#[doc = r" representing a specific SIMD instruction set. These tokens are obtained at runtime via [`Level`] and the"]
#[doc = r" [`dispatch!`](crate::dispatch) macro, which selects the best available backend for the current CPU."]
#[doc = r""]
#[doc = r" This trait defines all the low-level SIMD operations (e.g. [`add_f32x4`](Simd::add_f32x4),"]
#[doc = r" [`mul_u32x4`](Simd::mul_u32x4)) that are implemented by each token type using platform-specific intrinsics."]
#[doc = r" However, you typically won't call these methods directly. Instead, you'll probably be using the methods"]
#[doc = r" defined on the vector types themselves, such as [`f32x4`] or [`u32x4`]."]
#[doc = r""]
#[doc = r" # Associated Types"]
#[doc = r""]
#[doc = r#" The trait defines associated types for the highest "native" vector width of each scalar type (e.g. `f32s`,"#]
#[doc = r" `u32s`). These are always at least 128 bits, but may be larger. Currently, they are 128 bits on the"]
#[doc = r" fallback, NEON, WASM, SSE2, and SSE4.2 backends, 256 bits on AVX2, and 512 bits on AVX-512."]
#[doc = r""]
#[doc = r" # Example"]
#[doc = r""]
#[doc = r" ```"]
#[doc = r" # use fearless_simd::{prelude::*, f32x4, dispatch, Level};"]
#[doc = r""]
#[doc = r" #[inline(always)]"]
#[doc = r" fn add_vectors<S: Simd>(simd: S, a: f32x4<S>, b: f32x4<S>) -> f32x4<S> {"]
#[doc = r"     a + b  // Uses operator overloading, which calls simd.add_f32x4 internally"]
#[doc = r" }"]
#[doc = r""]
#[doc = r" let level = Level::new();"]
#[doc = r" dispatch!(level, simd => {"]
#[doc = r"     let a = [1.0, 2.0, 3.0, 4.0].simd_into(simd);"]
#[doc = r"     let b = [5.0, 6.0, 7.0, 8.0].simd_into(simd);"]
#[doc = r"     let result = add_vectors(simd, a, b);"]
#[doc = r"     # assert_eq!(*result, [6.0, 8.0, 10.0, 12.0]);"]
#[doc = r" });"]
#[doc = r" ```"]
pub trait Simd:
    ExtractToken<S = Self>
    + Sized
    + Clone
    + Copy
    + Send
    + Sync
    + Debug
    + Seal
    + arch_types::ArchTypes
    + 'static
{
    #[doc = r" A native-width SIMD vector of [`f32`]s."]
    type f32s: SimdFloat<
            Self,
            Element = f32,
            Block = f32x4<Self>,
            Mask = Self::mask32s,
            ByteVector = Self::u8s,
        > + SimdCvtFloat<Self::u32s>
        + SimdCvtFloat<Self::i32s>
        + SimdWiden<Self, Widened = Self::f64s>;
    #[doc = r" A native-width SIMD vector of [`f64`]s."]
    type f64s: SimdFloat<
            Self,
            Element = f64,
            Block = f64x2<Self>,
            Mask = Self::mask64s,
            ByteVector = Self::u8s,
        > + SimdCvtFloat<Self::u64s>
        + SimdCvtFloat<Self::i64s>
        + SimdNarrow<Self, Narrowed = Self::f32s>;
    #[doc = r" A native-width SIMD vector of [`u8`]s."]
    type u8s: SimdInt<
            Self,
            Element = u8,
            Block = u8x16<Self>,
            Mask = Self::mask8s,
            ByteVector = Self::u8s,
        > + SimdIntWiden<Self, Widened = Self::u16s>;
    #[doc = r" A native-width SIMD vector of [`i8`]s."]
    type i8s: SimdInt<
            Self,
            Element = i8,
            Block = i8x16<Self>,
            Mask = Self::mask8s,
            ByteVector = Self::u8s,
        > + SimdIntWiden<Self, Widened = Self::i16s>
        + core::ops::Neg<Output = Self::i8s>;
    #[doc = r" A native-width SIMD vector of [`u16`]s."]
    type u16s: SimdInt<
            Self,
            Element = u16,
            Block = u16x8<Self>,
            Mask = Self::mask16s,
            ByteVector = Self::u8s,
        > + SimdNarrow<Self, Narrowed = Self::u8s>
        + SimdIntWiden<Self, Widened = Self::u32s>;
    #[doc = r" A native-width SIMD vector of [`i16`]s."]
    type i16s: SimdInt<
            Self,
            Element = i16,
            Block = i16x8<Self>,
            Mask = Self::mask16s,
            ByteVector = Self::u8s,
        > + SimdNarrow<Self, Narrowed = Self::i8s>
        + SimdIntWiden<Self, Widened = Self::i32s>
        + core::ops::Neg<Output = Self::i16s>;
    #[doc = r" A native-width SIMD vector of [`u32`]s."]
    type u32s: SimdInt<
            Self,
            Element = u32,
            Block = u32x4<Self>,
            Mask = Self::mask32s,
            ByteVector = Self::u8s,
        > + SimdCvtTruncate<Self::f32s>
        + SimdNarrow<Self, Narrowed = Self::u16s>
        + SimdIntWiden<Self, Widened = Self::u64s>;
    #[doc = r" A native-width SIMD vector of [`i32`]s."]
    type i32s: SimdInt<
            Self,
            Element = i32,
            Block = i32x4<Self>,
            Mask = Self::mask32s,
            ByteVector = Self::u8s,
        > + SimdCvtTruncate<Self::f32s>
        + SimdNarrow<Self, Narrowed = Self::i16s>
        + SimdIntWiden<Self, Widened = Self::i64s>
        + core::ops::Neg<Output = Self::i32s>;
    #[doc = r" A native-width SIMD vector of [`u64`]s."]
    type u64s: SimdInt<
            Self,
            Element = u64,
            Block = u64x2<Self>,
            Mask = Self::mask64s,
            ByteVector = Self::u8s,
        > + SimdCvtTruncate<Self::f64s>
        + SimdNarrow<Self, Narrowed = Self::u32s>;
    #[doc = r" A native-width SIMD vector of [`i64`]s."]
    type i64s: SimdInt<
            Self,
            Element = i64,
            Block = i64x2<Self>,
            Mask = Self::mask64s,
            ByteVector = Self::u8s,
        > + SimdCvtTruncate<Self::f64s>
        + SimdNarrow<Self, Narrowed = Self::i32s>
        + core::ops::Neg<Output = Self::i64s>;
    #[doc = r" A native-width SIMD mask with 8-bit lanes."]
    type mask8s: SimdMask<Self, Element = i8, Ints = Self::i8s>
        + Select<Self::u8s>
        + Select<Self::i8s>
        + Select<Self::mask8s>
        + MaskWiden<Self, Widened = Self::mask16s>;
    #[doc = r" A native-width SIMD mask with 16-bit lanes."]
    type mask16s: SimdMask<Self, Element = i16, Ints = Self::i16s>
        + Select<Self::u16s>
        + Select<Self::i16s>
        + Select<Self::mask16s>
        + MaskNarrow<Self, Narrowed = Self::mask8s>
        + MaskWiden<Self, Widened = Self::mask32s>;
    #[doc = r" A native-width SIMD mask with 32-bit lanes."]
    type mask32s: SimdMask<Self, Element = i32, Ints = Self::i32s>
        + Select<Self::f32s>
        + Select<Self::u32s>
        + Select<Self::i32s>
        + Select<Self::mask32s>
        + MaskNarrow<Self, Narrowed = Self::mask16s>
        + MaskWiden<Self, Widened = Self::mask64s>;
    #[doc = r" A native-width SIMD mask with 64-bit lanes."]
    type mask64s: SimdMask<Self, Element = i64, Ints = Self::i64s>
        + Select<Self::f64s>
        + Select<Self::u64s>
        + Select<Self::i64s>
        + Select<Self::mask64s>
        + MaskNarrow<Self, Narrowed = Self::mask32s>;
    #[doc = r" This SIMD token's feature level."]
    fn level(self) -> Level;
    #[doc = r" Call a closure with the instructions for this SIMD level enabled."]
    #[doc = r""]
    #[doc = r" `vectorize()` establishes the correct `#[target_feature]` context. The provided"]
    #[doc = r" closure should be `#[inline(always)]` so that its body is incorporated into that"]
    #[doc = r" context and can use all instructions supported by this SIMD level."]
    #[doc = r""]
    #[doc = r" The small wrappers used by `vectorize()` are eligible for inlining when the caller"]
    #[doc = r" has a compatible target-feature context. A function containing the call does not"]
    #[doc = r" itself need an `#[inline(always)]` annotation; a target-feature boundary is retained"]
    #[doc = r" whenever one is required."]
    #[doc = r""]
    #[doc = r" The [`#[simd]`](https://docs.rs/fearless_simd_macros/latest/fearless_simd_macros/attr.simd.html)"]
    #[doc = r" attribute from the separate `fearless_simd_macros` crate establishes this context"]
    #[doc = r" automatically, passing ordinary function arguments separately to reduce capture"]
    #[doc = r" overhead. Calling `vectorize()` manually avoids the procedural-macro dependency."]
    #[doc = r""]
    #[doc = r" # Example"]
    #[doc = r""]
    #[doc = r" `double_u32s` does not need to be marked `#[inline(always)]`; only the closure passed"]
    #[doc = r" to `vectorize()` does."]
    #[doc = r""]
    #[doc = r" ```"]
    #[doc = r" use fearless_simd::{dispatch, prelude::*, Level};"]
    #[doc = r""]
    #[doc = r" fn double_u32s<S: Simd>(simd: S, values: &mut [u32]) {"]
    #[doc = r"     simd.vectorize("]
    #[doc = r"         #[inline(always)]"]
    #[doc = r"         || {"]
    #[doc = r"             let mut chunks = values.chunks_exact_mut(S::u32s::LEN);"]
    #[doc = r"             for chunk in &mut chunks {"]
    #[doc = r"                 let value = S::u32s::from_slice(simd, chunk);"]
    #[doc = r"                 (value * 2).store_slice(chunk);"]
    #[doc = r"             }"]
    #[doc = r"             for value in chunks.into_remainder() {"]
    #[doc = r"                 *value *= 2;"]
    #[doc = r"             }"]
    #[doc = r"         },"]
    #[doc = r"     );"]
    #[doc = r" }"]
    #[doc = r""]
    #[doc = r" let mut values = [1, 2, 3, 4, 5];"]
    #[doc = r" let level = Level::new();"]
    #[doc = r" dispatch!(level, simd => double_u32s(simd, &mut values));"]
    #[doc = r" assert_eq!(values, [2, 4, 6, 8, 10]);"]
    #[doc = r" ```"]
    fn vectorize<F: FnOnce() -> R, R>(self, f: F) -> R;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_f32x4(self, val: f32) -> f32x4<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_f32x4<const SHIFT: usize>(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_f32x4<const SHIFT: usize>(
        self,
        a: f32x4<Self>,
        b: f32x4<Self>,
    ) -> f32x4<Self> {
        self.slide_f32x4::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_f32x4(self, a: f32x4<Self>, indices: u8x16<Self>) -> f32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_f32x4(self, a: f32x4<Self>, indices: u8x16<Self>) -> f32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_f32x4(self, a: f32x4<Self>, indices: u8x16<Self>) -> f32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_f32x4(
        self,
        a: f32x4<Self>,
        b: f32x4<Self>,
        indices: u8x16<Self>,
    ) -> f32x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_f32x4(
        self,
        a: f32x4<Self>,
        b: f32x4<Self>,
        indices: u8x16<Self>,
    ) -> f32x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_f32x4(self, values: f32x4<Self>, mask: mask32x4<Self>) -> f32x4<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_f32x4(
        self,
        values: f32x4<Self>,
        mask: mask32x4<Self>,
        merge: f32x4<Self>,
    ) -> f32x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_f32x4(self, values: f32x4<Self>, mask: mask32x4<Self>) -> f32x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_f32x4(
        self,
        values: f32x4<Self>,
        mask: mask32x4<Self>,
        merge: f32x4<Self>,
    ) -> f32x4<Self>;
    #[doc = "Negate each element of the vector."]
    fn neg_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    fn sqrt_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    fn approximate_recip_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Add two vectors element-wise."]
    fn add_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Subtract two vectors element-wise."]
    fn sub_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Multiply two vectors element-wise."]
    fn mul_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Divide two vectors element-wise."]
    fn div_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return a vector with the magnitude of `a` and the sign of `b` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    fn copysign_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_f32x4(self, a: f32x4<Self>) -> f32;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_f32x4(self, a: f32x4<Self>) -> f32;
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn reduce_max_precise_f32x4(self, a: f32x4<Self>) -> f32;
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn reduce_min_precise_f32x4(self, a: f32x4<Self>) -> f32;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_f32x4(self, a: f32x4<Self>) -> f32;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_f32x4(self, a: f32x4<Self>) -> f32;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn max_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn min_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_f32x4(self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self> {
        self.not_mask32x4(self.simd_eq_f32x4(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self> {
        self.simd_le_f32x4(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> mask32x4<Self> {
        self.simd_lt_f32x4(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> (f32x4<Self>, f32x4<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> (f32x4<Self>, f32x4<Self>);
    #[doc = "Compute `(a * b) + c` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    fn mul_add_f32x4(self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Compute `(a * b) + c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    fn mul_add_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Compute `(a * b) - c` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    fn mul_sub_f32x4(self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Compute `(a * b) - c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    fn mul_sub_precise_f32x4(self, a: f32x4<Self>, b: f32x4<Self>, c: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    fn floor_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    fn ceil_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    fn round_ties_even_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    fn round_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `a - a.trunc()`."]
    fn fract_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return the integer part of each element, rounding towards zero."]
    fn trunc_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    fn to_degrees_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    fn to_radians_f32x4(self, a: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative_f32x4(self, a: f32x4<Self>) -> mask32x4<Self>;
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_f32x4(self, a: mask32x4<Self>, b: f32x4<Self>, c: f32x4<Self>) -> f32x4<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_f32x4(self, a: f32x4<Self>, b: f32x4<Self>) -> f32x8<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_f32x4(self, src: &[f32; 16usize]) -> [f32x4<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_f32x4(
        self,
        vectors: [f32x4<Self>; 4usize],
        dest: &mut [f32; 16usize],
    ) -> ();
    #[doc = "Widen every `f32` lane exactly into two same-width `f64` vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_f32x4(self, a: f32x4<Self>) -> (f64x2<Self>, f64x2<Self>);
    #[doc = "Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results.\n\nOn x86 platforms below AVX-512, this operation will still be slower than converting to `i32`, because there is no native instruction for converting to `u32`.\nIf you know your values fit within range of an `i32`, you should convert to an `i32` and cast to your desired datatype afterwards."]
    fn cvt_u32_f32x4(self, a: f32x4<Self>) -> u32x4<Self>;
    #[doc = "Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    fn cvt_u32_precise_f32x4(self, a: f32x4<Self>) -> u32x4<Self>;
    #[doc = "Convert each floating-point element to a signed 32-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    fn cvt_i32_f32x4(self, a: f32x4<Self>) -> i32x4<Self>;
    #[doc = "Convert each floating-point element to a signed 32-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    fn cvt_i32_precise_f32x4(self, a: f32x4<Self>) -> i32x4<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_i8x16(self, val: i8) -> i8x16<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i8x16<const SHIFT: usize>(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i8x16<const SHIFT: usize>(
        self,
        a: i8x16<Self>,
        b: i8x16<Self>,
    ) -> i8x16<Self> {
        self.slide_i8x16::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i8x16(self, a: i8x16<Self>, indices: u8x16<Self>) -> i8x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i8x16(self, a: i8x16<Self>, indices: u8x16<Self>) -> i8x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i8x16(self, a: i8x16<Self>, indices: u8x16<Self>) -> i8x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i8x16(
        self,
        a: i8x16<Self>,
        b: i8x16<Self>,
        indices: u8x16<Self>,
    ) -> i8x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i8x16(
        self,
        a: i8x16<Self>,
        b: i8x16<Self>,
        indices: u8x16<Self>,
    ) -> i8x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i8x16(self, values: i8x16<Self>, mask: mask8x16<Self>) -> i8x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i8x16(
        self,
        values: i8x16<Self>,
        mask: mask8x16<Self>,
        merge: i8x16<Self>,
    ) -> i8x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i8x16(self, values: i8x16<Self>, mask: mask8x16<Self>) -> i8x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i8x16(
        self,
        values: i8x16<Self>,
        mask: mask8x16<Self>,
        merge: i8x16<Self>,
    ) -> i8x16<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_i8x16(self, a: i8x16<Self>, shift: u32) -> i8x16<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_i8x16(self, a: i8x16<Self>) -> i8;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_i8x16(self, a: i8x16<Self>) -> i8;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_i8x16(self, a: i8x16<Self>) -> i8;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_i8x16(self, a: i8x16<Self>) -> i8;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_i8x16(self, a: i8x16<Self>, b: i8x16<Self>, c: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self> {
        self.not_mask8x16(self.simd_eq_i8x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self> {
        self.simd_le_i8x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> mask8x16<Self> {
        self.simd_lt_i8x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> (i8x16<Self>, i8x16<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> (i8x16<Self>, i8x16<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_i8x16(self, a: mask8x16<Self>, b: i8x16<Self>, c: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i8x32<Self>;
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    fn neg_i8x16(self, a: i8x16<Self>) -> i8x16<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_i8x16(self, src: &[i8; 64usize]) -> [i8x16<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_i8x16(
        self,
        vectors: [i8x16<Self>; 4usize],
        dest: &mut [i8; 64usize],
    ) -> ();
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_i8x16(self, a: i8x16<Self>) -> (i16x8<Self>, i16x8<Self>);
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_mul_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> (i16x8<Self>, i16x8<Self>);
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_add_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> (i16x8<Self>, i16x8<Self>);
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    fn pairwise_widening_add_i8x16(self, a: i8x16<Self>) -> i16x8<Self>;
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    fn pairwise_dot_product_i8x16(self, a: i8x16<Self>, b: i8x16<Self>) -> i16x8<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u8x16(self, a: u8x16<Self>) -> u8x16<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_u8x16(self, val: u8) -> u8x16<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u8x16<const SHIFT: usize>(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u8x16<const SHIFT: usize>(
        self,
        a: u8x16<Self>,
        b: u8x16<Self>,
    ) -> u8x16<Self> {
        self.slide_u8x16::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    fn swizzle_dyn_within_blocks_u8x16(self, a: u8x16<Self>, indices: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn swizzle_dyn_u8x16(self, a: u8x16<Self>, indices: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    fn swizzle_dyn_precise_u8x16(self, a: u8x16<Self>, indices: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn concat_swizzle_dyn_u8x16(
        self,
        a: u8x16<Self>,
        b: u8x16<Self>,
        indices: u8x16<Self>,
    ) -> u8x16<Self>;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    fn concat_swizzle_dyn_precise_u8x16(
        self,
        a: u8x16<Self>,
        b: u8x16<Self>,
        indices: u8x16<Self>,
    ) -> u8x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u8x16(self, values: u8x16<Self>, mask: mask8x16<Self>) -> u8x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u8x16(
        self,
        values: u8x16<Self>,
        mask: mask8x16<Self>,
        merge: u8x16<Self>,
    ) -> u8x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u8x16(self, values: u8x16<Self>, mask: mask8x16<Self>) -> u8x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u8x16(
        self,
        values: u8x16<Self>,
        mask: mask8x16<Self>,
        merge: u8x16<Self>,
    ) -> u8x16<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_u8x16(self, a: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_u8x16(self, a: u8x16<Self>, shift: u32) -> u8x16<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_u8x16(self, a: u8x16<Self>) -> u8;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_u8x16(self, a: u8x16<Self>) -> u8;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_u8x16(self, a: u8x16<Self>) -> u8;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_u8x16(self, a: u8x16<Self>) -> u8;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_u8x16(self, a: u8x16<Self>, b: u8x16<Self>, c: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self> {
        self.not_mask8x16(self.simd_eq_u8x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self> {
        self.simd_le_u8x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> mask8x16<Self> {
        self.simd_lt_u8x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> (u8x16<Self>, u8x16<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> (u8x16<Self>, u8x16<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_u8x16(self, a: mask8x16<Self>, b: u8x16<Self>, c: u8x16<Self>) -> u8x16<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u8x32<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_u8x16(self, src: &[u8; 64usize]) -> [u8x16<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_u8x16(
        self,
        vectors: [u8x16<Self>; 4usize],
        dest: &mut [u8; 64usize],
    ) -> ();
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_u8x16(self, a: u8x16<Self>) -> (u16x8<Self>, u16x8<Self>);
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_mul_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> (u16x8<Self>, u16x8<Self>);
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_add_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> (u16x8<Self>, u16x8<Self>);
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    fn pairwise_widening_add_u8x16(self, a: u8x16<Self>) -> u16x8<Self>;
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    fn pairwise_dot_product_u8x16(self, a: u8x16<Self>, b: u8x16<Self>) -> u16x8<Self>;
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    fn splat_mask8x16(self, val: bool) -> mask8x16<Self>;
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    fn from_bitmask_mask8x16(self, bits: u64) -> mask8x16<Self>;
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    fn to_bitmask_mask8x16(self, a: mask8x16<Self>) -> u64;
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask8x16(self, vector: i8x16<Self>) -> mask8x16<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask8x16(self, a: mask8x16<Self>) -> i8x16<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask8x16(self, a: &mut mask8x16<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask8x16<const OFFSET: usize>(
        self,
        a: mask8x16<Self>,
    ) -> mask8x16<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask8x16<const OFFSET: usize>(
        self,
        a: mask8x16<Self>,
    ) -> mask8x16<Self>;
    #[doc = "Compute the logical AND of two masks."]
    fn and_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compute the logical OR of two masks."]
    fn or_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compute the logical XOR of two masks."]
    fn xor_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compute the logical NOT of the mask."]
    fn not_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>;
    #[doc = "Reverse the order of the mask's logical lanes."]
    fn reverse_mask8x16(self, a: mask8x16<Self>) -> mask8x16<Self>;
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_mask8x16(
        self,
        a: mask8x16<Self>,
        b: mask8x16<Self>,
        c: mask8x16<Self>,
    ) -> mask8x16<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self>;
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x16<Self> {
        self.not_mask8x16(self.simd_eq_mask8x16(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_true_mask8x16(self, a: mask8x16<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_true_mask8x16(self, a: mask8x16<Self>) -> bool;
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_false_mask8x16(self, a: mask8x16<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_false_mask8x16(self, a: mask8x16<Self>) -> bool;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask8x16(self, a: mask8x16<Self>, b: mask8x16<Self>) -> mask8x32<Self>;
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    fn widen_mask8x16(self, a: mask8x16<Self>) -> (mask16x8<Self>, mask16x8<Self>);
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_i16x8(self, val: i16) -> i16x8<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i16x8<const SHIFT: usize>(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i16x8<const SHIFT: usize>(
        self,
        a: i16x8<Self>,
        b: i16x8<Self>,
    ) -> i16x8<Self> {
        self.slide_i16x8::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i16x8(self, a: i16x8<Self>, indices: u8x16<Self>) -> i16x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i16x8(self, a: i16x8<Self>, indices: u8x16<Self>) -> i16x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i16x8(self, a: i16x8<Self>, indices: u8x16<Self>) -> i16x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i16x8(
        self,
        a: i16x8<Self>,
        b: i16x8<Self>,
        indices: u8x16<Self>,
    ) -> i16x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i16x8(
        self,
        a: i16x8<Self>,
        b: i16x8<Self>,
        indices: u8x16<Self>,
    ) -> i16x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i16x8(self, values: i16x8<Self>, mask: mask16x8<Self>) -> i16x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i16x8(
        self,
        values: i16x8<Self>,
        mask: mask16x8<Self>,
        merge: i16x8<Self>,
    ) -> i16x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i16x8(self, values: i16x8<Self>, mask: mask16x8<Self>) -> i16x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i16x8(
        self,
        values: i16x8<Self>,
        mask: mask16x8<Self>,
        merge: i16x8<Self>,
    ) -> i16x8<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_i16x8(self, a: i16x8<Self>, shift: u32) -> i16x8<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_i16x8(self, a: i16x8<Self>) -> i16;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_i16x8(self, a: i16x8<Self>) -> i16;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_i16x8(self, a: i16x8<Self>) -> i16;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_i16x8(self, a: i16x8<Self>) -> i16;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_i16x8(self, a: i16x8<Self>, b: i16x8<Self>, c: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self> {
        self.not_mask16x8(self.simd_eq_i16x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self> {
        self.simd_le_i16x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> mask16x8<Self> {
        self.simd_lt_i16x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> (i16x8<Self>, i16x8<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> (i16x8<Self>, i16x8<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_i16x8(self, a: mask16x8<Self>, b: i16x8<Self>, c: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i16x16<Self>;
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    fn neg_i16x8(self, a: i16x8<Self>) -> i16x8<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_i16x8(self, src: &[i16; 32usize]) -> [i16x8<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_i16x8(
        self,
        vectors: [i16x8<Self>; 4usize],
        dest: &mut [i16; 32usize],
    ) -> ();
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_i16x8(self, a: i16x8<Self>) -> (i32x4<Self>, i32x4<Self>);
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_mul_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> (i32x4<Self>, i32x4<Self>);
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_add_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> (i32x4<Self>, i32x4<Self>);
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    fn pairwise_widening_add_i16x8(self, a: i16x8<Self>) -> i32x4<Self>;
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    fn pairwise_dot_product_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i32x4<Self>;
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>;
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>;
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_i16x8(self, a: i16x8<Self>, b: i16x8<Self>) -> i8x16<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u16x8(self, a: u16x8<Self>) -> u16x8<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_u16x8(self, val: u16) -> u16x8<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u16x8<const SHIFT: usize>(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u16x8<const SHIFT: usize>(
        self,
        a: u16x8<Self>,
        b: u16x8<Self>,
    ) -> u16x8<Self> {
        self.slide_u16x8::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u16x8(self, a: u16x8<Self>, indices: u8x16<Self>) -> u16x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u16x8(self, a: u16x8<Self>, indices: u8x16<Self>) -> u16x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u16x8(self, a: u16x8<Self>, indices: u8x16<Self>) -> u16x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u16x8(
        self,
        a: u16x8<Self>,
        b: u16x8<Self>,
        indices: u8x16<Self>,
    ) -> u16x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u16x8(
        self,
        a: u16x8<Self>,
        b: u16x8<Self>,
        indices: u8x16<Self>,
    ) -> u16x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u16x8(self, values: u16x8<Self>, mask: mask16x8<Self>) -> u16x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u16x8(
        self,
        values: u16x8<Self>,
        mask: mask16x8<Self>,
        merge: u16x8<Self>,
    ) -> u16x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u16x8(self, values: u16x8<Self>, mask: mask16x8<Self>) -> u16x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u16x8(
        self,
        values: u16x8<Self>,
        mask: mask16x8<Self>,
        merge: u16x8<Self>,
    ) -> u16x8<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_u16x8(self, a: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_u16x8(self, a: u16x8<Self>, shift: u32) -> u16x8<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_u16x8(self, a: u16x8<Self>) -> u16;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_u16x8(self, a: u16x8<Self>) -> u16;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_u16x8(self, a: u16x8<Self>) -> u16;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_u16x8(self, a: u16x8<Self>) -> u16;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_u16x8(self, a: u16x8<Self>, b: u16x8<Self>, c: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self> {
        self.not_mask16x8(self.simd_eq_u16x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self> {
        self.simd_le_u16x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> mask16x8<Self> {
        self.simd_lt_u16x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> (u16x8<Self>, u16x8<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> (u16x8<Self>, u16x8<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_u16x8(self, a: mask16x8<Self>, b: u16x8<Self>, c: u16x8<Self>) -> u16x8<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u16x16<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_u16x8(self, src: &[u16; 32usize]) -> [u16x8<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_u16x8(
        self,
        vectors: [u16x8<Self>; 4usize],
        dest: &mut [u16; 32usize],
    ) -> ();
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_u16x8(self, a: u16x8<Self>) -> (u32x4<Self>, u32x4<Self>);
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_mul_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> (u32x4<Self>, u32x4<Self>);
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_add_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> (u32x4<Self>, u32x4<Self>);
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    fn pairwise_widening_add_u16x8(self, a: u16x8<Self>) -> u32x4<Self>;
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    fn pairwise_dot_product_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u32x4<Self>;
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>;
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>;
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_u16x8(self, a: u16x8<Self>, b: u16x8<Self>) -> u8x16<Self>;
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    fn splat_mask16x8(self, val: bool) -> mask16x8<Self>;
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    fn from_bitmask_mask16x8(self, bits: u64) -> mask16x8<Self>;
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    fn to_bitmask_mask16x8(self, a: mask16x8<Self>) -> u64;
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask16x8(self, vector: i16x8<Self>) -> mask16x8<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask16x8(self, a: mask16x8<Self>) -> i16x8<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask16x8(self, a: &mut mask16x8<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask16x8<const OFFSET: usize>(
        self,
        a: mask16x8<Self>,
    ) -> mask16x8<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask16x8<const OFFSET: usize>(
        self,
        a: mask16x8<Self>,
    ) -> mask16x8<Self>;
    #[doc = "Compute the logical AND of two masks."]
    fn and_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compute the logical OR of two masks."]
    fn or_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compute the logical XOR of two masks."]
    fn xor_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compute the logical NOT of the mask."]
    fn not_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>;
    #[doc = "Reverse the order of the mask's logical lanes."]
    fn reverse_mask16x8(self, a: mask16x8<Self>) -> mask16x8<Self>;
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_mask16x8(
        self,
        a: mask16x8<Self>,
        b: mask16x8<Self>,
        c: mask16x8<Self>,
    ) -> mask16x8<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self>;
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x8<Self> {
        self.not_mask16x8(self.simd_eq_mask16x8(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_true_mask16x8(self, a: mask16x8<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_true_mask16x8(self, a: mask16x8<Self>) -> bool;
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_false_mask16x8(self, a: mask16x8<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_false_mask16x8(self, a: mask16x8<Self>) -> bool;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask16x16<Self>;
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    fn widen_mask16x8(self, a: mask16x8<Self>) -> (mask32x4<Self>, mask32x4<Self>);
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    fn narrow_mask16x8(self, a: mask16x8<Self>, b: mask16x8<Self>) -> mask8x16<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_i32x4(self, val: i32) -> i32x4<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i32x4<const SHIFT: usize>(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i32x4<const SHIFT: usize>(
        self,
        a: i32x4<Self>,
        b: i32x4<Self>,
    ) -> i32x4<Self> {
        self.slide_i32x4::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i32x4(self, a: i32x4<Self>, indices: u8x16<Self>) -> i32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i32x4(self, a: i32x4<Self>, indices: u8x16<Self>) -> i32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i32x4(self, a: i32x4<Self>, indices: u8x16<Self>) -> i32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i32x4(
        self,
        a: i32x4<Self>,
        b: i32x4<Self>,
        indices: u8x16<Self>,
    ) -> i32x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i32x4(
        self,
        a: i32x4<Self>,
        b: i32x4<Self>,
        indices: u8x16<Self>,
    ) -> i32x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i32x4(self, values: i32x4<Self>, mask: mask32x4<Self>) -> i32x4<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i32x4(
        self,
        values: i32x4<Self>,
        mask: mask32x4<Self>,
        merge: i32x4<Self>,
    ) -> i32x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i32x4(self, values: i32x4<Self>, mask: mask32x4<Self>) -> i32x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i32x4(
        self,
        values: i32x4<Self>,
        mask: mask32x4<Self>,
        merge: i32x4<Self>,
    ) -> i32x4<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_i32x4(self, a: i32x4<Self>, shift: u32) -> i32x4<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_i32x4(self, a: i32x4<Self>) -> i32;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_i32x4(self, a: i32x4<Self>) -> i32;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_i32x4(self, a: i32x4<Self>) -> i32;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_i32x4(self, a: i32x4<Self>) -> i32;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_i32x4(self, a: i32x4<Self>, b: i32x4<Self>, c: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self> {
        self.not_mask32x4(self.simd_eq_i32x4(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self> {
        self.simd_le_i32x4(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> mask32x4<Self> {
        self.simd_lt_i32x4(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> (i32x4<Self>, i32x4<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> (i32x4<Self>, i32x4<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_i32x4(self, a: mask32x4<Self>, b: i32x4<Self>, c: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i32x8<Self>;
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    fn neg_i32x4(self, a: i32x4<Self>) -> i32x4<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_i32x4(self, src: &[i32; 16usize]) -> [i32x4<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_i32x4(
        self,
        vectors: [i32x4<Self>; 4usize],
        dest: &mut [i32; 16usize],
    ) -> ();
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_i32x4(self, a: i32x4<Self>) -> (i64x2<Self>, i64x2<Self>);
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_mul_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> (i64x2<Self>, i64x2<Self>);
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_add_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> (i64x2<Self>, i64x2<Self>);
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    fn pairwise_widening_add_i32x4(self, a: i32x4<Self>) -> i64x2<Self>;
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    fn pairwise_dot_product_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i64x2<Self>;
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>;
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>;
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_i32x4(self, a: i32x4<Self>, b: i32x4<Self>) -> i16x8<Self>;
    #[doc = "Convert each signed 32-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    fn cvt_f32_i32x4(self, a: i32x4<Self>) -> f32x4<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u32x4(self, a: u32x4<Self>) -> u32x4<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_u32x4(self, val: u32) -> u32x4<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u32x4<const SHIFT: usize>(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u32x4<const SHIFT: usize>(
        self,
        a: u32x4<Self>,
        b: u32x4<Self>,
    ) -> u32x4<Self> {
        self.slide_u32x4::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u32x4(self, a: u32x4<Self>, indices: u8x16<Self>) -> u32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u32x4(self, a: u32x4<Self>, indices: u8x16<Self>) -> u32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u32x4(self, a: u32x4<Self>, indices: u8x16<Self>) -> u32x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u32x4(
        self,
        a: u32x4<Self>,
        b: u32x4<Self>,
        indices: u8x16<Self>,
    ) -> u32x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u32x4(
        self,
        a: u32x4<Self>,
        b: u32x4<Self>,
        indices: u8x16<Self>,
    ) -> u32x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u32x4(self, values: u32x4<Self>, mask: mask32x4<Self>) -> u32x4<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u32x4(
        self,
        values: u32x4<Self>,
        mask: mask32x4<Self>,
        merge: u32x4<Self>,
    ) -> u32x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u32x4(self, values: u32x4<Self>, mask: mask32x4<Self>) -> u32x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u32x4(
        self,
        values: u32x4<Self>,
        mask: mask32x4<Self>,
        merge: u32x4<Self>,
    ) -> u32x4<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_u32x4(self, a: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_u32x4(self, a: u32x4<Self>, shift: u32) -> u32x4<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_u32x4(self, a: u32x4<Self>) -> u32;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_u32x4(self, a: u32x4<Self>) -> u32;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_u32x4(self, a: u32x4<Self>) -> u32;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_u32x4(self, a: u32x4<Self>) -> u32;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_u32x4(self, a: u32x4<Self>, b: u32x4<Self>, c: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self> {
        self.not_mask32x4(self.simd_eq_u32x4(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self> {
        self.simd_le_u32x4(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> mask32x4<Self> {
        self.simd_lt_u32x4(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> (u32x4<Self>, u32x4<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> (u32x4<Self>, u32x4<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_u32x4(self, a: mask32x4<Self>, b: u32x4<Self>, c: u32x4<Self>) -> u32x4<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u32x8<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_u32x4(self, src: &[u32; 16usize]) -> [u32x4<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_u32x4(
        self,
        vectors: [u32x4<Self>; 4usize],
        dest: &mut [u32; 16usize],
    ) -> ();
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    fn widen_u32x4(self, a: u32x4<Self>) -> (u64x2<Self>, u64x2<Self>);
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_mul_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> (u64x2<Self>, u64x2<Self>);
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    fn widening_add_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> (u64x2<Self>, u64x2<Self>);
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    fn pairwise_widening_add_u32x4(self, a: u32x4<Self>) -> u64x2<Self>;
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    fn pairwise_dot_product_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u64x2<Self>;
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>;
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>;
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_u32x4(self, a: u32x4<Self>, b: u32x4<Self>) -> u16x8<Self>;
    #[doc = "Convert each unsigned 32-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    fn cvt_f32_u32x4(self, a: u32x4<Self>) -> f32x4<Self>;
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    fn splat_mask32x4(self, val: bool) -> mask32x4<Self>;
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    fn from_bitmask_mask32x4(self, bits: u64) -> mask32x4<Self>;
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    fn to_bitmask_mask32x4(self, a: mask32x4<Self>) -> u64;
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask32x4(self, vector: i32x4<Self>) -> mask32x4<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask32x4(self, a: mask32x4<Self>) -> i32x4<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask32x4(self, a: &mut mask32x4<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask32x4<const OFFSET: usize>(
        self,
        a: mask32x4<Self>,
    ) -> mask32x4<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask32x4<const OFFSET: usize>(
        self,
        a: mask32x4<Self>,
    ) -> mask32x4<Self>;
    #[doc = "Compute the logical AND of two masks."]
    fn and_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compute the logical OR of two masks."]
    fn or_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compute the logical XOR of two masks."]
    fn xor_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compute the logical NOT of the mask."]
    fn not_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>;
    #[doc = "Reverse the order of the mask's logical lanes."]
    fn reverse_mask32x4(self, a: mask32x4<Self>) -> mask32x4<Self>;
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_mask32x4(
        self,
        a: mask32x4<Self>,
        b: mask32x4<Self>,
        c: mask32x4<Self>,
    ) -> mask32x4<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self>;
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x4<Self> {
        self.not_mask32x4(self.simd_eq_mask32x4(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_true_mask32x4(self, a: mask32x4<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_true_mask32x4(self, a: mask32x4<Self>) -> bool;
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_false_mask32x4(self, a: mask32x4<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_false_mask32x4(self, a: mask32x4<Self>) -> bool;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask32x8<Self>;
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    fn widen_mask32x4(self, a: mask32x4<Self>) -> (mask64x2<Self>, mask64x2<Self>);
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    fn narrow_mask32x4(self, a: mask32x4<Self>, b: mask32x4<Self>) -> mask16x8<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_f64x2(self, val: f64) -> f64x2<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_f64x2<const SHIFT: usize>(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_f64x2<const SHIFT: usize>(
        self,
        a: f64x2<Self>,
        b: f64x2<Self>,
    ) -> f64x2<Self> {
        self.slide_f64x2::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_f64x2(self, a: f64x2<Self>, indices: u8x16<Self>) -> f64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_f64x2(self, a: f64x2<Self>, indices: u8x16<Self>) -> f64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_f64x2(self, a: f64x2<Self>, indices: u8x16<Self>) -> f64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_f64x2(
        self,
        a: f64x2<Self>,
        b: f64x2<Self>,
        indices: u8x16<Self>,
    ) -> f64x2<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_f64x2(
        self,
        a: f64x2<Self>,
        b: f64x2<Self>,
        indices: u8x16<Self>,
    ) -> f64x2<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_f64x2(self, values: f64x2<Self>, mask: mask64x2<Self>) -> f64x2<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_f64x2(
        self,
        values: f64x2<Self>,
        mask: mask64x2<Self>,
        merge: f64x2<Self>,
    ) -> f64x2<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_f64x2(self, values: f64x2<Self>, mask: mask64x2<Self>) -> f64x2<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_f64x2(
        self,
        values: f64x2<Self>,
        mask: mask64x2<Self>,
        merge: f64x2<Self>,
    ) -> f64x2<Self>;
    #[doc = "Negate each element of the vector."]
    fn neg_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    fn sqrt_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    fn approximate_recip_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Add two vectors element-wise."]
    fn add_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Subtract two vectors element-wise."]
    fn sub_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Multiply two vectors element-wise."]
    fn mul_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Divide two vectors element-wise."]
    fn div_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return a vector with the magnitude of `a` and the sign of `b` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    fn copysign_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_f64x2(self, a: f64x2<Self>) -> f64;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_f64x2(self, a: f64x2<Self>) -> f64;
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn reduce_max_precise_f64x2(self, a: f64x2<Self>) -> f64;
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn reduce_min_precise_f64x2(self, a: f64x2<Self>) -> f64;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_f64x2(self, a: f64x2<Self>) -> f64;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_f64x2(self, a: f64x2<Self>) -> f64;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn max_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn min_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_f64x2(self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self> {
        self.not_mask64x2(self.simd_eq_f64x2(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self> {
        self.simd_le_f64x2(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> mask64x2<Self> {
        self.simd_lt_f64x2(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> (f64x2<Self>, f64x2<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> (f64x2<Self>, f64x2<Self>);
    #[doc = "Compute `(a * b) + c` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    fn mul_add_f64x2(self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Compute `(a * b) + c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    fn mul_add_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Compute `(a * b) - c` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    fn mul_sub_f64x2(self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Compute `(a * b) - c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    fn mul_sub_precise_f64x2(self, a: f64x2<Self>, b: f64x2<Self>, c: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    fn floor_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    fn ceil_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    fn round_ties_even_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    fn round_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `a - a.trunc()`."]
    fn fract_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return the integer part of each element, rounding towards zero."]
    fn trunc_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    fn to_degrees_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    fn to_radians_f64x2(self, a: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative_f64x2(self, a: f64x2<Self>) -> mask64x2<Self>;
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_f64x2(self, a: mask64x2<Self>, b: f64x2<Self>, c: f64x2<Self>) -> f64x2<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f64x4<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_f64x2(self, src: &[f64; 8usize]) -> [f64x2<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_f64x2(
        self,
        vectors: [f64x2<Self>; 4usize],
        dest: &mut [f64; 8usize],
    ) -> ();
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nValues are rounded to the nearest representable `f32`, with ties resolved to even; overflow produces signed infinity.This is the same as the `as` operator, and follows the IEEE 754 narrowing behavior in round-to-even mode.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>;
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nFor floating-point vectors this is identical to `narrow`, including its rounding and overflow behavior.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>;
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nFor floating-point vectors this is identical to `narrow`, including its rounding and overflow behavior.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_f64x2(self, a: f64x2<Self>, b: f64x2<Self>) -> f32x4<Self>;
    #[doc = "Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    fn cvt_u64_f64x2(self, a: f64x2<Self>) -> u64x2<Self>;
    #[doc = "Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    fn cvt_u64_precise_f64x2(self, a: f64x2<Self>) -> u64x2<Self>;
    #[doc = "Convert each floating-point element to a signed 64-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    fn cvt_i64_f64x2(self, a: f64x2<Self>) -> i64x2<Self>;
    #[doc = "Convert each floating-point element to a signed 64-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    fn cvt_i64_precise_f64x2(self, a: f64x2<Self>) -> i64x2<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_i64x2(self, val: i64) -> i64x2<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i64x2<const SHIFT: usize>(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i64x2<const SHIFT: usize>(
        self,
        a: i64x2<Self>,
        b: i64x2<Self>,
    ) -> i64x2<Self> {
        self.slide_i64x2::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i64x2(self, a: i64x2<Self>, indices: u8x16<Self>) -> i64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i64x2(self, a: i64x2<Self>, indices: u8x16<Self>) -> i64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i64x2(self, a: i64x2<Self>, indices: u8x16<Self>) -> i64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i64x2(
        self,
        a: i64x2<Self>,
        b: i64x2<Self>,
        indices: u8x16<Self>,
    ) -> i64x2<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i64x2(
        self,
        a: i64x2<Self>,
        b: i64x2<Self>,
        indices: u8x16<Self>,
    ) -> i64x2<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i64x2(self, values: i64x2<Self>, mask: mask64x2<Self>) -> i64x2<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i64x2(
        self,
        values: i64x2<Self>,
        mask: mask64x2<Self>,
        merge: i64x2<Self>,
    ) -> i64x2<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i64x2(self, values: i64x2<Self>, mask: mask64x2<Self>) -> i64x2<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i64x2(
        self,
        values: i64x2<Self>,
        mask: mask64x2<Self>,
        merge: i64x2<Self>,
    ) -> i64x2<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_i64x2(self, a: i64x2<Self>, shift: u32) -> i64x2<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_i64x2(self, a: i64x2<Self>) -> i64;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_i64x2(self, a: i64x2<Self>) -> i64;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_i64x2(self, a: i64x2<Self>) -> i64;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_i64x2(self, a: i64x2<Self>) -> i64;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_i64x2(self, a: i64x2<Self>, b: i64x2<Self>, c: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self> {
        self.not_mask64x2(self.simd_eq_i64x2(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self> {
        self.simd_le_i64x2(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> mask64x2<Self> {
        self.simd_lt_i64x2(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> (i64x2<Self>, i64x2<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> (i64x2<Self>, i64x2<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_i64x2(self, a: mask64x2<Self>, b: i64x2<Self>, c: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i64x4<Self>;
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    fn neg_i64x2(self, a: i64x2<Self>) -> i64x2<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_i64x2(self, src: &[i64; 8usize]) -> [i64x2<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_i64x2(
        self,
        vectors: [i64x2<Self>; 4usize],
        dest: &mut [i64; 8usize],
    ) -> ();
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>;
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>;
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_i64x2(self, a: i64x2<Self>, b: i64x2<Self>) -> i32x4<Self>;
    #[doc = "Convert each signed 64-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    fn cvt_f64_i64x2(self, a: i64x2<Self>) -> f64x2<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u64x2(self, a: u64x2<Self>) -> u64x2<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat_u64x2(self, val: u64) -> u64x2<Self>;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u64x2<const SHIFT: usize>(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u64x2<const SHIFT: usize>(
        self,
        a: u64x2<Self>,
        b: u64x2<Self>,
    ) -> u64x2<Self> {
        self.slide_u64x2::<SHIFT>(a, b)
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u64x2(self, a: u64x2<Self>, indices: u8x16<Self>) -> u64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u64x2(self, a: u64x2<Self>, indices: u8x16<Self>) -> u64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u64x2(self, a: u64x2<Self>, indices: u8x16<Self>) -> u64x2<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x16(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u64x2(
        self,
        a: u64x2<Self>,
        b: u64x2<Self>,
        indices: u8x16<Self>,
    ) -> u64x2<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u64x2(
        self,
        a: u64x2<Self>,
        b: u64x2<Self>,
        indices: u8x16<Self>,
    ) -> u64x2<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x16(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u64x2(self, values: u64x2<Self>, mask: mask64x2<Self>) -> u64x2<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u64x2(
        self,
        values: u64x2<Self>,
        mask: mask64x2<Self>,
        merge: u64x2<Self>,
    ) -> u64x2<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u64x2(self, values: u64x2<Self>, mask: mask64x2<Self>) -> u64x2<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u64x2(
        self,
        values: u64x2<Self>,
        mask: mask64x2<Self>,
        merge: u64x2<Self>,
    ) -> u64x2<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    fn add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    fn sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    fn mul_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Compute the bitwise AND of two vectors."]
    fn and_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Compute the bitwise OR of two vectors."]
    fn or_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Compute the bitwise XOR of two vectors."]
    fn xor_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Compute the bitwise NOT of the vector."]
    fn not_u64x2(self, a: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shl_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>;
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shlv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    fn shr_u64x2(self, a: u64x2<Self>, shift: u32) -> u64x2<Self>;
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    fn shrv_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max_u64x2(self, a: u64x2<Self>) -> u64;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min_u64x2(self, a: u64x2<Self>) -> u64;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum_u64x2(self, a: u64x2<Self>) -> u64;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product_u64x2(self, a: u64x2<Self>) -> u64;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    fn clamp_u64x2(self, a: u64x2<Self>, b: u64x2<Self>, c: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self> {
        self.not_mask64x2(self.simd_eq_u64x2(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    fn simd_lt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    fn simd_le_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self> {
        self.simd_le_u64x2(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> mask64x2<Self> {
        self.simd_lt_u64x2(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> (u64x2<Self>, u64x2<Self>);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> (u64x2<Self>, u64x2<Self>);
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_u64x2(self, a: mask64x2<Self>, b: u64x2<Self>, c: u64x2<Self>) -> u64x2<Self>;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u64x4<Self>;
    #[doc = "Load four 128-bit vectors from an array with 4-way interleaving.\n\nThis is useful e.g. in image processing to turn interleaved RGBA pixels into vectors of each color component.\n\nFor example, with 32-bit lanes, memory laid out as`[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]` loads as`[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]`."]
    #[doc(alias = "load_interleaved")]
    fn load_four_interleaved_u64x2(self, src: &[u64; 8usize]) -> [u64x2<Self>; 4usize];
    #[doc = "Store four 128-bit vectors to an array with 4-way interleaving.\n\nThis is the inverse of `load_four_interleaved`.\n\nThis is useful e.g. in image processing to turn vectors of each color component into interleaved RGBA pixels.\n\nFor example, with 32-bit lanes, vectors containing `[[r0, r1, r2, r3], [g0, g1, g2, g3], [b0, b1, b2, b3], [a0, a1, a2, a3]]` get stored as `[r0, g0, b0, a0, r1, g1, b1, a1, r2, g2, b2, a2, r3, g3, b3, a3]`."]
    #[doc(alias = "store_interleaved")]
    fn store_four_interleaved_u64x2(
        self,
        vectors: [u64x2<Self>; 4usize],
        dest: &mut [u64; 8usize],
    ) -> ();
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>;
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn saturating_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>;
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    fn relaxed_narrow_u64x2(self, a: u64x2<Self>, b: u64x2<Self>) -> u32x4<Self>;
    #[doc = "Convert each unsigned 64-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    fn cvt_f64_u64x2(self, a: u64x2<Self>) -> f64x2<Self>;
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    fn splat_mask64x2(self, val: bool) -> mask64x2<Self>;
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    fn from_bitmask_mask64x2(self, bits: u64) -> mask64x2<Self>;
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    fn to_bitmask_mask64x2(self, a: mask64x2<Self>) -> u64;
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask64x2(self, vector: i64x2<Self>) -> mask64x2<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask64x2(self, a: mask64x2<Self>) -> i64x2<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask64x2(self, a: &mut mask64x2<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask64x2<const OFFSET: usize>(
        self,
        a: mask64x2<Self>,
    ) -> mask64x2<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask64x2<const OFFSET: usize>(
        self,
        a: mask64x2<Self>,
    ) -> mask64x2<Self>;
    #[doc = "Compute the logical AND of two masks."]
    fn and_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compute the logical OR of two masks."]
    fn or_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compute the logical XOR of two masks."]
    fn xor_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compute the logical NOT of the mask."]
    fn not_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>;
    #[doc = "Reverse the order of the mask's logical lanes."]
    fn reverse_mask64x2(self, a: mask64x2<Self>) -> mask64x2<Self>;
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    fn select_mask64x2(
        self,
        a: mask64x2<Self>,
        b: mask64x2<Self>,
        c: mask64x2<Self>,
    ) -> mask64x2<Self>;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self>;
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x2<Self> {
        self.not_mask64x2(self.simd_eq_mask64x2(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_true_mask64x2(self, a: mask64x2<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_true_mask64x2(self, a: mask64x2<Self>) -> bool;
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_false_mask64x2(self, a: mask64x2<Self>) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_false_mask64x2(self, a: mask64x2<Self>) -> bool;
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask64x4<Self>;
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    fn narrow_mask64x2(self, a: mask64x2<Self>, b: mask64x2<Self>) -> mask32x4<Self>;
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.abs_f32x4(a0), self.abs_f32x4(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_f32x8(self, val: f32) -> f32x8<Self> {
        let half = self.splat_f32x4(val);
        self.combine_f32x4(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.reverse_f32x4(a1), self.reverse_f32x4(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_f32x8<const SHIFT: usize>(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_f32x8<const SHIFT: usize>(
        self,
        a: f32x8<Self>,
        b: f32x8<Self>,
    ) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(
            self.slide_within_blocks_f32x4::<SHIFT>(a0, b0),
            self.slide_within_blocks_f32x4::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_f32x8(self, a: f32x8<Self>, indices: u8x32<Self>) -> f32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_f32x8(self, a: f32x8<Self>, indices: u8x32<Self>) -> f32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_f32x8(self, a: f32x8<Self>, indices: u8x32<Self>) -> f32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_f32x8(
        self,
        a: f32x8<Self>,
        b: f32x8<Self>,
        indices: u8x32<Self>,
    ) -> f32x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_f32x8(
        self,
        a: f32x8<Self>,
        b: f32x8<Self>,
        indices: u8x32<Self>,
    ) -> f32x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_f32x8(self, values: f32x8<Self>, mask: mask32x8<Self>) -> f32x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_f32x8(
        self,
        values: f32x8<Self>,
        mask: mask32x8<Self>,
        merge: f32x8<Self>,
    ) -> f32x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_f32x8(self, values: f32x8<Self>, mask: mask32x8<Self>) -> f32x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_f32x8(
        self,
        values: f32x8<Self>,
        mask: mask32x8<Self>,
        merge: f32x8<Self>,
    ) -> f32x8<Self>;
    #[doc = "Negate each element of the vector."]
    #[inline(always)]
    fn neg_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.neg_f32x4(a0), self.neg_f32x4(a1))
    }
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    #[inline(always)]
    fn sqrt_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.sqrt_f32x4(a0), self.sqrt_f32x4(a1))
    }
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    #[inline(always)]
    fn approximate_recip_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(
            self.approximate_recip_f32x4(a0),
            self.approximate_recip_f32x4(a1),
        )
    }
    #[doc = "Add two vectors element-wise."]
    #[inline(always)]
    fn add_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.add_f32x4(a0, b0), self.add_f32x4(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise."]
    #[inline(always)]
    fn sub_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.sub_f32x4(a0, b0), self.sub_f32x4(a1, b1))
    }
    #[doc = "Multiply two vectors element-wise."]
    #[inline(always)]
    fn mul_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.mul_f32x4(a0, b0), self.mul_f32x4(a1, b1))
    }
    #[doc = "Divide two vectors element-wise."]
    #[inline(always)]
    fn div_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.div_f32x4(a0, b0), self.div_f32x4(a1, b1))
    }
    #[doc = "Return a vector with the magnitude of `a` and the sign of `b` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    #[inline(always)]
    fn copysign_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.copysign_f32x4(a0, b0), self.copysign_f32x4(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_f32x8(self, a: f32x8<Self>) -> f32 {
        let (a0, a1) = self.split_f32x8(a);
        self.reduce_max_f32x4(self.max_f32x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_f32x8(self, a: f32x8<Self>) -> f32 {
        let (a0, a1) = self.split_f32x8(a);
        self.reduce_min_f32x4(self.min_f32x4(a0, a1))
    }
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_max_precise_f32x8(self, a: f32x8<Self>) -> f32 {
        let (a0, a1) = self.split_f32x8(a);
        self.reduce_max_precise_f32x4(self.max_precise_f32x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_min_precise_f32x8(self, a: f32x8<Self>) -> f32 {
        let (a0, a1) = self.split_f32x8(a);
        self.reduce_min_precise_f32x4(self.min_precise_f32x4(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_f32x8(self, a: f32x8<Self>) -> f32 {
        let (a0, a1) = self.split_f32x8(a);
        self.reduce_sum_f32x4(self.add_f32x4(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_f32x8(self, a: f32x8<Self>) -> f32 {
        let (a0, a1) = self.split_f32x8(a);
        self.reduce_product_f32x4(self.mul_f32x4(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.max_f32x4(a0, b0), self.max_f32x4(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.min_f32x4(a0, b0), self.min_f32x4(a1, b1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn max_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(
            self.max_precise_f32x4(a0, b0),
            self.max_precise_f32x4(a1, b1),
        )
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn min_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(
            self.min_precise_f32x4(a0, b0),
            self.min_precise_f32x4(a1, b1),
        )
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_f32x8(self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let (c0, c1) = self.split_f32x8(c);
        self.combine_f32x4(self.clamp_f32x4(a0, b0, c0), self.clamp_f32x4(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_mask32x4(self.simd_eq_f32x4(a0, b0), self.simd_eq_f32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> {
        self.not_mask32x8(self.simd_eq_f32x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_mask32x4(self.simd_lt_f32x4(a0, b0), self.simd_lt_f32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_mask32x4(self.simd_le_f32x4(a0, b0), self.simd_le_f32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> {
        self.simd_le_f32x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> mask32x8<Self> {
        self.simd_lt_f32x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, _) = self.split_f32x8(a);
        let (b0, _) = self.split_f32x8(b);
        self.combine_f32x4(self.zip_low_f32x4(a0, b0), self.zip_high_f32x4(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (_, a1) = self.split_f32x8(a);
        let (_, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.zip_low_f32x4(a1, b1), self.zip_high_f32x4(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.unzip_low_f32x4(a0, a1), self.unzip_low_f32x4(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        self.combine_f32x4(self.unzip_high_f32x4(a0, a1), self.unzip_high_f32x4(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> (f32x8<Self>, f32x8<Self>) {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let lo_lo = self.zip_low_f32x4(a0, b0);
        let lo_hi = self.zip_high_f32x4(a0, b0);
        let hi_lo = self.zip_low_f32x4(a1, b1);
        let hi_hi = self.zip_high_f32x4(a1, b1);
        (
            self.combine_f32x4(lo_lo, lo_hi),
            self.combine_f32x4(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> (f32x8<Self>, f32x8<Self>) {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let lo_even = self.unzip_low_f32x4(a0, a1);
        let lo_odd = self.unzip_high_f32x4(a0, a1);
        let hi_even = self.unzip_low_f32x4(b0, b1);
        let hi_odd = self.unzip_high_f32x4(b0, b1);
        (
            self.combine_f32x4(lo_even, hi_even),
            self.combine_f32x4(lo_odd, hi_odd),
        )
    }
    #[doc = "Compute `(a * b) + c` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_add_f32x8(self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let (c0, c1) = self.split_f32x8(c);
        self.combine_f32x4(
            self.mul_add_f32x4(a0, b0, c0),
            self.mul_add_f32x4(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) + c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_add_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let (c0, c1) = self.split_f32x8(c);
        self.combine_f32x4(
            self.mul_add_precise_f32x4(a0, b0, c0),
            self.mul_add_precise_f32x4(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_sub_f32x8(self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let (c0, c1) = self.split_f32x8(c);
        self.combine_f32x4(
            self.mul_sub_f32x4(a0, b0, c0),
            self.mul_sub_f32x4(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_sub_precise_f32x8(self, a: f32x8<Self>, b: f32x8<Self>, c: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let (c0, c1) = self.split_f32x8(c);
        self.combine_f32x4(
            self.mul_sub_precise_f32x4(a0, b0, c0),
            self.mul_sub_precise_f32x4(a1, b1, c1),
        )
    }
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    #[inline(always)]
    fn floor_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.floor_f32x4(a0), self.floor_f32x4(a1))
    }
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    #[inline(always)]
    fn ceil_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.ceil_f32x4(a0), self.ceil_f32x4(a1))
    }
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    #[inline(always)]
    fn round_ties_even_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(
            self.round_ties_even_f32x4(a0),
            self.round_ties_even_f32x4(a1),
        )
    }
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    #[inline(always)]
    fn round_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.round_f32x4(a0), self.round_f32x4(a1))
    }
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `a - a.trunc()`."]
    #[inline(always)]
    fn fract_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.fract_f32x4(a0), self.fract_f32x4(a1))
    }
    #[doc = "Return the integer part of each element, rounding towards zero."]
    #[inline(always)]
    fn trunc_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.trunc_f32x4(a0), self.trunc_f32x4(a1))
    }
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_degrees_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.to_degrees_f32x4(a0), self.to_degrees_f32x4(a1))
    }
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_radians_f32x8(self, a: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_f32x4(self.to_radians_f32x4(a0), self.to_radians_f32x4(a1))
    }
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative_f32x8(self, a: f32x8<Self>) -> mask32x8<Self>;
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_f32x8(self, a: mask32x8<Self>, b: f32x8<Self>, c: f32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_f32x8(b);
        let (c0, c1) = self.split_f32x8(c);
        self.combine_f32x4(self.select_f32x4(a0, b0, c0), self.select_f32x4(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_f32x8(self, a: f32x8<Self>, b: f32x8<Self>) -> f32x16<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_f32x8(self, a: f32x8<Self>) -> (f32x4<Self>, f32x4<Self>);
    #[doc = "Widen every `f32` lane exactly into two same-width `f64` vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_f32x8(self, a: f32x8<Self>) -> (f64x4<Self>, f64x4<Self>) {
        let (a0, a1) = self.split_f32x8(a);
        let (a00, a01) = self.widen_f32x4(a0);
        let (a10, a11) = self.widen_f32x4(a1);
        (self.combine_f64x2(a00, a01), self.combine_f64x2(a10, a11))
    }
    #[doc = "Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results.\n\nOn x86 platforms below AVX-512, this operation will still be slower than converting to `i32`, because there is no native instruction for converting to `u32`.\nIf you know your values fit within range of an `i32`, you should convert to an `i32` and cast to your desired datatype afterwards."]
    #[inline(always)]
    fn cvt_u32_f32x8(self, a: f32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_u32x4(self.cvt_u32_f32x4(a0), self.cvt_u32_f32x4(a1))
    }
    #[doc = "Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_u32_precise_f32x8(self, a: f32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_u32x4(
            self.cvt_u32_precise_f32x4(a0),
            self.cvt_u32_precise_f32x4(a1),
        )
    }
    #[doc = "Convert each floating-point element to a signed 32-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    #[inline(always)]
    fn cvt_i32_f32x8(self, a: f32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_i32x4(self.cvt_i32_f32x4(a0), self.cvt_i32_f32x4(a1))
    }
    #[doc = "Convert each floating-point element to a signed 32-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_i32_precise_f32x8(self, a: f32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_f32x8(a);
        self.combine_i32x4(
            self.cvt_i32_precise_f32x4(a0),
            self.cvt_i32_precise_f32x4(a1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i8x32(self, a: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.abs_i8x16(a0), self.abs_i8x16(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i8x32(self, val: i8) -> i8x32<Self> {
        let half = self.splat_i8x16(val);
        self.combine_i8x16(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i8x32(self, a: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.reverse_i8x16(a1), self.reverse_i8x16(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i8x32<const SHIFT: usize>(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i8x32<const SHIFT: usize>(
        self,
        a: i8x32<Self>,
        b: i8x32<Self>,
    ) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(
            self.slide_within_blocks_i8x16::<SHIFT>(a0, b0),
            self.slide_within_blocks_i8x16::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i8x32(self, a: i8x32<Self>, indices: u8x32<Self>) -> i8x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i8x32(self, a: i8x32<Self>, indices: u8x32<Self>) -> i8x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i8x32(self, a: i8x32<Self>, indices: u8x32<Self>) -> i8x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i8x32(
        self,
        a: i8x32<Self>,
        b: i8x32<Self>,
        indices: u8x32<Self>,
    ) -> i8x32<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i8x32(
        self,
        a: i8x32<Self>,
        b: i8x32<Self>,
        indices: u8x32<Self>,
    ) -> i8x32<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i8x32(self, values: i8x32<Self>, mask: mask8x32<Self>) -> i8x32<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i8x32(
        self,
        values: i8x32<Self>,
        mask: mask8x32<Self>,
        merge: i8x32<Self>,
    ) -> i8x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i8x32(self, values: i8x32<Self>, mask: mask8x32<Self>) -> i8x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i8x32(
        self,
        values: i8x32<Self>,
        mask: mask8x32<Self>,
        merge: i8x32<Self>,
    ) -> i8x32<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i8x32(self, a: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.count_ones_i8x16(a0), self.count_ones_i8x16(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i8x32(self, a: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.count_zeros_i8x16(a0), self.count_zeros_i8x16(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.add_i8x16(a0, b0), self.add_i8x16(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(
            self.saturating_add_i8x16(a0, b0),
            self.saturating_add_i8x16(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.sub_i8x16(a0, b0), self.sub_i8x16(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(
            self.saturating_sub_i8x16(a0, b0),
            self.saturating_sub_i8x16(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.mul_i8x16(a0, b0), self.mul_i8x16(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.and_i8x16(a0, b0), self.and_i8x16(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.or_i8x16(a0, b0), self.or_i8x16(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.xor_i8x16(a0, b0), self.xor_i8x16(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i8x32(self, a: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.not_i8x16(a0), self.not_i8x16(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.shl_i8x16(a0, shift), self.shl_i8x16(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.shlv_i8x16(a0, b0), self.shlv_i8x16(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i8x32(self, a: i8x32<Self>, shift: u32) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.shr_i8x16(a0, shift), self.shr_i8x16(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.shrv_i8x16(a0, b0), self.shrv_i8x16(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i8x32(self, a: i8x32<Self>) -> i8 {
        let (a0, a1) = self.split_i8x32(a);
        self.reduce_max_i8x16(self.max_i8x16(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i8x32(self, a: i8x32<Self>) -> i8 {
        let (a0, a1) = self.split_i8x32(a);
        self.reduce_min_i8x16(self.min_i8x16(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i8x32(self, a: i8x32<Self>) -> i8 {
        let (a0, a1) = self.split_i8x32(a);
        self.reduce_sum_i8x16(self.add_i8x16(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i8x32(self, a: i8x32<Self>) -> i8 {
        let (a0, a1) = self.split_i8x32(a);
        self.reduce_product_i8x16(self.mul_i8x16(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.max_i8x16(a0, b0), self.max_i8x16(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.min_i8x16(a0, b0), self.min_i8x16(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i8x32(self, a: i8x32<Self>, b: i8x32<Self>, c: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        let (c0, c1) = self.split_i8x32(c);
        self.combine_i8x16(self.clamp_i8x16(a0, b0, c0), self.clamp_i8x16(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_mask8x16(self.simd_eq_i8x16(a0, b0), self.simd_eq_i8x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> {
        self.not_mask8x32(self.simd_eq_i8x32(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_mask8x16(self.simd_lt_i8x16(a0, b0), self.simd_lt_i8x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_mask8x16(self.simd_le_i8x16(a0, b0), self.simd_le_i8x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> {
        self.simd_le_i8x32(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> mask8x32<Self> {
        self.simd_lt_i8x32(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, _) = self.split_i8x32(a);
        let (b0, _) = self.split_i8x32(b);
        self.combine_i8x16(self.zip_low_i8x16(a0, b0), self.zip_high_i8x16(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (_, a1) = self.split_i8x32(a);
        let (_, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.zip_low_i8x16(a1, b1), self.zip_high_i8x16(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.unzip_low_i8x16(a0, a1), self.unzip_low_i8x16(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i8x16(self.unzip_high_i8x16(a0, a1), self.unzip_high_i8x16(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> (i8x32<Self>, i8x32<Self>) {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        let lo_lo = self.zip_low_i8x16(a0, b0);
        let lo_hi = self.zip_high_i8x16(a0, b0);
        let hi_lo = self.zip_low_i8x16(a1, b1);
        let hi_hi = self.zip_high_i8x16(a1, b1);
        (
            self.combine_i8x16(lo_lo, lo_hi),
            self.combine_i8x16(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> (i8x32<Self>, i8x32<Self>) {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        let lo_even = self.unzip_low_i8x16(a0, a1);
        let lo_odd = self.unzip_high_i8x16(a0, a1);
        let hi_even = self.unzip_low_i8x16(b0, b1);
        let hi_odd = self.unzip_high_i8x16(b0, b1);
        (
            self.combine_i8x16(lo_even, hi_even),
            self.combine_i8x16(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i8x32(self, a: mask8x32<Self>, b: i8x32<Self>, c: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        let (c0, c1) = self.split_i8x32(c);
        self.combine_i8x16(self.select_i8x16(a0, b0, c0), self.select_i8x16(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i8x64<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i8x32(self, a: i8x32<Self>) -> (i8x16<Self>, i8x16<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i8x32(self, a: i8x32<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i8x16(self.neg_i8x16(a0), self.neg_i8x16(a1))
    }
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_i8x32(self, a: i8x32<Self>) -> (i16x16<Self>, i16x16<Self>) {
        let (a0, a1) = self.split_i8x32(a);
        let (a00, a01) = self.widen_i8x16(a0);
        let (a10, a11) = self.widen_i8x16(a1);
        (self.combine_i16x8(a00, a01), self.combine_i16x8(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> (i16x16<Self>, i16x16<Self>) {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        let (low0, low1) = self.widening_mul_i8x16(a0, b0);
        let (high0, high1) = self.widening_mul_i8x16(a1, b1);
        (
            self.combine_i16x8(low0, low1),
            self.combine_i16x8(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> (i16x16<Self>, i16x16<Self>) {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        let (low0, low1) = self.widening_add_i8x16(a0, b0);
        let (high0, high1) = self.widening_add_i8x16(a1, b1);
        (
            self.combine_i16x8(low0, low1),
            self.combine_i16x8(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_i8x32(self, a: i8x32<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i8x32(a);
        self.combine_i16x8(
            self.pairwise_widening_add_i8x16(a0),
            self.pairwise_widening_add_i8x16(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_i8x32(self, a: i8x32<Self>, b: i8x32<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i8x32(a);
        let (b0, b1) = self.split_i8x32(b);
        self.combine_i16x8(
            self.pairwise_dot_product_i8x16(a0, b0),
            self.pairwise_dot_product_i8x16(a1, b1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u8x32(self, a: u8x32<Self>) -> u8x32<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u8x32(self, val: u8) -> u8x32<Self> {
        let half = self.splat_u8x16(val);
        self.combine_u8x16(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u8x32(self, a: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u8x16(self.reverse_u8x16(a1), self.reverse_u8x16(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u8x32<const SHIFT: usize>(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u8x32<const SHIFT: usize>(
        self,
        a: u8x32<Self>,
        b: u8x32<Self>,
    ) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(
            self.slide_within_blocks_u8x16::<SHIFT>(a0, b0),
            self.slide_within_blocks_u8x16::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u8x32(self, a: u8x32<Self>, indices: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (indices0, indices1) = self.split_u8x32(indices);
        self.combine_u8x16(
            self.swizzle_dyn_within_blocks_u8x16(a0, indices0),
            self.swizzle_dyn_within_blocks_u8x16(a1, indices1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn swizzle_dyn_u8x32(self, a: u8x32<Self>, indices: u8x32<Self>) -> u8x32<Self>;
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    fn swizzle_dyn_precise_u8x32(self, a: u8x32<Self>, indices: u8x32<Self>) -> u8x32<Self>;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn concat_swizzle_dyn_u8x32(
        self,
        a: u8x32<Self>,
        b: u8x32<Self>,
        indices: u8x32<Self>,
    ) -> u8x32<Self>;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    fn concat_swizzle_dyn_precise_u8x32(
        self,
        a: u8x32<Self>,
        b: u8x32<Self>,
        indices: u8x32<Self>,
    ) -> u8x32<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u8x32(self, values: u8x32<Self>, mask: mask8x32<Self>) -> u8x32<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u8x32(
        self,
        values: u8x32<Self>,
        mask: mask8x32<Self>,
        merge: u8x32<Self>,
    ) -> u8x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u8x32(self, values: u8x32<Self>, mask: mask8x32<Self>) -> u8x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u8x32(
        self,
        values: u8x32<Self>,
        mask: mask8x32<Self>,
        merge: u8x32<Self>,
    ) -> u8x32<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u8x32(self, a: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u8x16(self.count_ones_u8x16(a0), self.count_ones_u8x16(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u8x32(self, a: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u8x16(self.count_zeros_u8x16(a0), self.count_zeros_u8x16(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.add_u8x16(a0, b0), self.add_u8x16(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(
            self.saturating_add_u8x16(a0, b0),
            self.saturating_add_u8x16(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.sub_u8x16(a0, b0), self.sub_u8x16(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(
            self.saturating_sub_u8x16(a0, b0),
            self.saturating_sub_u8x16(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.mul_u8x16(a0, b0), self.mul_u8x16(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.and_u8x16(a0, b0), self.and_u8x16(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.or_u8x16(a0, b0), self.or_u8x16(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.xor_u8x16(a0, b0), self.xor_u8x16(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u8x32(self, a: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u8x16(self.not_u8x16(a0), self.not_u8x16(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u8x16(self.shl_u8x16(a0, shift), self.shl_u8x16(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.shlv_u8x16(a0, b0), self.shlv_u8x16(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u8x32(self, a: u8x32<Self>, shift: u32) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u8x16(self.shr_u8x16(a0, shift), self.shr_u8x16(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.shrv_u8x16(a0, b0), self.shrv_u8x16(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u8x32(self, a: u8x32<Self>) -> u8 {
        let (a0, a1) = self.split_u8x32(a);
        self.reduce_max_u8x16(self.max_u8x16(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u8x32(self, a: u8x32<Self>) -> u8 {
        let (a0, a1) = self.split_u8x32(a);
        self.reduce_min_u8x16(self.min_u8x16(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u8x32(self, a: u8x32<Self>) -> u8 {
        let (a0, a1) = self.split_u8x32(a);
        self.reduce_sum_u8x16(self.add_u8x16(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u8x32(self, a: u8x32<Self>) -> u8 {
        let (a0, a1) = self.split_u8x32(a);
        self.reduce_product_u8x16(self.mul_u8x16(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.max_u8x16(a0, b0), self.max_u8x16(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.min_u8x16(a0, b0), self.min_u8x16(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u8x32(self, a: u8x32<Self>, b: u8x32<Self>, c: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        let (c0, c1) = self.split_u8x32(c);
        self.combine_u8x16(self.clamp_u8x16(a0, b0, c0), self.clamp_u8x16(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_mask8x16(self.simd_eq_u8x16(a0, b0), self.simd_eq_u8x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> {
        self.not_mask8x32(self.simd_eq_u8x32(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_mask8x16(self.simd_lt_u8x16(a0, b0), self.simd_lt_u8x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_mask8x16(self.simd_le_u8x16(a0, b0), self.simd_le_u8x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> {
        self.simd_le_u8x32(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> mask8x32<Self> {
        self.simd_lt_u8x32(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, _) = self.split_u8x32(a);
        let (b0, _) = self.split_u8x32(b);
        self.combine_u8x16(self.zip_low_u8x16(a0, b0), self.zip_high_u8x16(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (_, a1) = self.split_u8x32(a);
        let (_, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.zip_low_u8x16(a1, b1), self.zip_high_u8x16(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.unzip_low_u8x16(a0, a1), self.unzip_low_u8x16(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u8x16(self.unzip_high_u8x16(a0, a1), self.unzip_high_u8x16(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> (u8x32<Self>, u8x32<Self>) {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        let lo_lo = self.zip_low_u8x16(a0, b0);
        let lo_hi = self.zip_high_u8x16(a0, b0);
        let hi_lo = self.zip_low_u8x16(a1, b1);
        let hi_hi = self.zip_high_u8x16(a1, b1);
        (
            self.combine_u8x16(lo_lo, lo_hi),
            self.combine_u8x16(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> (u8x32<Self>, u8x32<Self>) {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        let lo_even = self.unzip_low_u8x16(a0, a1);
        let lo_odd = self.unzip_high_u8x16(a0, a1);
        let hi_even = self.unzip_low_u8x16(b0, b1);
        let hi_odd = self.unzip_high_u8x16(b0, b1);
        (
            self.combine_u8x16(lo_even, hi_even),
            self.combine_u8x16(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u8x32(self, a: mask8x32<Self>, b: u8x32<Self>, c: u8x32<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        let (c0, c1) = self.split_u8x32(c);
        self.combine_u8x16(self.select_u8x16(a0, b0, c0), self.select_u8x16(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u8x64<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u8x32(self, a: u8x32<Self>) -> (u8x16<Self>, u8x16<Self>);
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_u8x32(self, a: u8x32<Self>) -> (u16x16<Self>, u16x16<Self>) {
        let (a0, a1) = self.split_u8x32(a);
        let (a00, a01) = self.widen_u8x16(a0);
        let (a10, a11) = self.widen_u8x16(a1);
        (self.combine_u16x8(a00, a01), self.combine_u16x8(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> (u16x16<Self>, u16x16<Self>) {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        let (low0, low1) = self.widening_mul_u8x16(a0, b0);
        let (high0, high1) = self.widening_mul_u8x16(a1, b1);
        (
            self.combine_u16x8(low0, low1),
            self.combine_u16x8(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> (u16x16<Self>, u16x16<Self>) {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        let (low0, low1) = self.widening_add_u8x16(a0, b0);
        let (high0, high1) = self.widening_add_u8x16(a1, b1);
        (
            self.combine_u16x8(low0, low1),
            self.combine_u16x8(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_u8x32(self, a: u8x32<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u8x32(a);
        self.combine_u16x8(
            self.pairwise_widening_add_u8x16(a0),
            self.pairwise_widening_add_u8x16(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_u8x32(self, a: u8x32<Self>, b: u8x32<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u8x32(a);
        let (b0, b1) = self.split_u8x32(b);
        self.combine_u16x8(
            self.pairwise_dot_product_u8x16(a0, b0),
            self.pairwise_dot_product_u8x16(a1, b1),
        )
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask8x32(self, val: bool) -> mask8x32<Self> {
        let half = self.splat_mask8x16(val);
        self.combine_mask8x16(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask8x32(self, bits: u64) -> mask8x32<Self> {
        let lo = self.from_bitmask_mask8x16(bits);
        let hi = self.from_bitmask_mask8x16(bits >> 16usize);
        self.combine_mask8x16(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask8x32(self, a: mask8x32<Self>) -> u64 {
        let (lo, hi) = self.split_mask8x32(a);
        let lo = self.to_bitmask_mask8x16(lo);
        let hi = self.to_bitmask_mask8x16(hi);
        lo | (hi << 16usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask8x32(self, vector: i8x32<Self>) -> mask8x32<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask8x32(self, a: mask8x32<Self>) -> i8x32<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask8x32(self, a: &mut mask8x32<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask8x32<const OFFSET: usize>(
        self,
        a: mask8x32<Self>,
    ) -> mask8x32<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask8x32<const OFFSET: usize>(
        self,
        a: mask8x32<Self>,
    ) -> mask8x32<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_mask8x32(b);
        self.combine_mask8x16(self.and_mask8x16(a0, b0), self.and_mask8x16(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_mask8x32(b);
        self.combine_mask8x16(self.or_mask8x16(a0, b0), self.or_mask8x16(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_mask8x32(b);
        self.combine_mask8x16(self.xor_mask8x16(a0, b0), self.xor_mask8x16(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        self.combine_mask8x16(self.not_mask8x16(a0), self.not_mask8x16(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask8x32(self, a: mask8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        self.combine_mask8x16(self.reverse_mask8x16(a1), self.reverse_mask8x16(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask8x32(
        self,
        a: mask8x32<Self>,
        b: mask8x32<Self>,
        c: mask8x32<Self>,
    ) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_mask8x32(b);
        let (c0, c1) = self.split_mask8x32(c);
        self.combine_mask8x16(
            self.select_mask8x16(a0, b0, c0),
            self.select_mask8x16(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask8x32(a);
        let (b0, b1) = self.split_mask8x32(b);
        self.combine_mask8x16(self.simd_eq_mask8x16(a0, b0), self.simd_eq_mask8x16(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x32<Self> {
        self.not_mask8x32(self.simd_eq_mask8x32(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask8x32(self, a: mask8x32<Self>) -> bool {
        let (a0, a1) = self.split_mask8x32(a);
        self.any_true_mask8x16(self.or_mask8x16(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask8x32(self, a: mask8x32<Self>) -> bool {
        let (a0, a1) = self.split_mask8x32(a);
        self.all_true_mask8x16(self.and_mask8x16(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask8x32(self, a: mask8x32<Self>) -> bool {
        let (a0, a1) = self.split_mask8x32(a);
        self.any_false_mask8x16(self.and_mask8x16(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask8x32(self, a: mask8x32<Self>) -> bool {
        let (a0, a1) = self.split_mask8x32(a);
        self.all_false_mask8x16(self.or_mask8x16(a0, a1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask8x32(self, a: mask8x32<Self>, b: mask8x32<Self>) -> mask8x64<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask8x32(self, a: mask8x32<Self>) -> (mask8x16<Self>, mask8x16<Self>);
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn widen_mask8x32(self, a: mask8x32<Self>) -> (mask16x16<Self>, mask16x16<Self>) {
        let (a0, a1) = self.split_mask8x32(a);
        let (a00, a01) = self.widen_mask8x16(a0);
        let (a10, a11) = self.widen_mask8x16(a1);
        (
            self.combine_mask16x8(a00, a01),
            self.combine_mask16x8(a10, a11),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i16x16(self, a: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.abs_i16x8(a0), self.abs_i16x8(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i16x16(self, val: i16) -> i16x16<Self> {
        let half = self.splat_i16x8(val);
        self.combine_i16x8(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i16x16(self, a: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.reverse_i16x8(a1), self.reverse_i16x8(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i16x16<const SHIFT: usize>(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i16x16<const SHIFT: usize>(
        self,
        a: i16x16<Self>,
        b: i16x16<Self>,
    ) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(
            self.slide_within_blocks_i16x8::<SHIFT>(a0, b0),
            self.slide_within_blocks_i16x8::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i16x16(
        self,
        a: i16x16<Self>,
        indices: u8x32<Self>,
    ) -> i16x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i16x16(self, a: i16x16<Self>, indices: u8x32<Self>) -> i16x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i16x16(self, a: i16x16<Self>, indices: u8x32<Self>) -> i16x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i16x16(
        self,
        a: i16x16<Self>,
        b: i16x16<Self>,
        indices: u8x32<Self>,
    ) -> i16x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i16x16(
        self,
        a: i16x16<Self>,
        b: i16x16<Self>,
        indices: u8x32<Self>,
    ) -> i16x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i16x16(self, values: i16x16<Self>, mask: mask16x16<Self>) -> i16x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i16x16(
        self,
        values: i16x16<Self>,
        mask: mask16x16<Self>,
        merge: i16x16<Self>,
    ) -> i16x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i16x16(self, values: i16x16<Self>, mask: mask16x16<Self>) -> i16x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i16x16(
        self,
        values: i16x16<Self>,
        mask: mask16x16<Self>,
        merge: i16x16<Self>,
    ) -> i16x16<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i16x16(self, a: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.count_ones_i16x8(a0), self.count_ones_i16x8(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i16x16(self, a: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.count_zeros_i16x8(a0), self.count_zeros_i16x8(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.add_i16x8(a0, b0), self.add_i16x8(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(
            self.saturating_add_i16x8(a0, b0),
            self.saturating_add_i16x8(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.sub_i16x8(a0, b0), self.sub_i16x8(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(
            self.saturating_sub_i16x8(a0, b0),
            self.saturating_sub_i16x8(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.mul_i16x8(a0, b0), self.mul_i16x8(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.and_i16x8(a0, b0), self.and_i16x8(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.or_i16x8(a0, b0), self.or_i16x8(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.xor_i16x8(a0, b0), self.xor_i16x8(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i16x16(self, a: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.not_i16x8(a0), self.not_i16x8(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.shl_i16x8(a0, shift), self.shl_i16x8(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.shlv_i16x8(a0, b0), self.shlv_i16x8(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i16x16(self, a: i16x16<Self>, shift: u32) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.shr_i16x8(a0, shift), self.shr_i16x8(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.shrv_i16x8(a0, b0), self.shrv_i16x8(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i16x16(self, a: i16x16<Self>) -> i16 {
        let (a0, a1) = self.split_i16x16(a);
        self.reduce_max_i16x8(self.max_i16x8(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i16x16(self, a: i16x16<Self>) -> i16 {
        let (a0, a1) = self.split_i16x16(a);
        self.reduce_min_i16x8(self.min_i16x8(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i16x16(self, a: i16x16<Self>) -> i16 {
        let (a0, a1) = self.split_i16x16(a);
        self.reduce_sum_i16x8(self.add_i16x8(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i16x16(self, a: i16x16<Self>) -> i16 {
        let (a0, a1) = self.split_i16x16(a);
        self.reduce_product_i16x8(self.mul_i16x8(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.max_i16x8(a0, b0), self.max_i16x8(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.min_i16x8(a0, b0), self.min_i16x8(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i16x16(self, a: i16x16<Self>, b: i16x16<Self>, c: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        let (c0, c1) = self.split_i16x16(c);
        self.combine_i16x8(self.clamp_i16x8(a0, b0, c0), self.clamp_i16x8(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_mask16x8(self.simd_eq_i16x8(a0, b0), self.simd_eq_i16x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> {
        self.not_mask16x16(self.simd_eq_i16x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_mask16x8(self.simd_lt_i16x8(a0, b0), self.simd_lt_i16x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_mask16x8(self.simd_le_i16x8(a0, b0), self.simd_le_i16x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> {
        self.simd_le_i16x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> mask16x16<Self> {
        self.simd_lt_i16x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, _) = self.split_i16x16(a);
        let (b0, _) = self.split_i16x16(b);
        self.combine_i16x8(self.zip_low_i16x8(a0, b0), self.zip_high_i16x8(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (_, a1) = self.split_i16x16(a);
        let (_, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.zip_low_i16x8(a1, b1), self.zip_high_i16x8(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.unzip_low_i16x8(a0, a1), self.unzip_low_i16x8(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i16x8(self.unzip_high_i16x8(a0, a1), self.unzip_high_i16x8(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> (i16x16<Self>, i16x16<Self>) {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        let lo_lo = self.zip_low_i16x8(a0, b0);
        let lo_hi = self.zip_high_i16x8(a0, b0);
        let hi_lo = self.zip_low_i16x8(a1, b1);
        let hi_hi = self.zip_high_i16x8(a1, b1);
        (
            self.combine_i16x8(lo_lo, lo_hi),
            self.combine_i16x8(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> (i16x16<Self>, i16x16<Self>) {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        let lo_even = self.unzip_low_i16x8(a0, a1);
        let lo_odd = self.unzip_high_i16x8(a0, a1);
        let hi_even = self.unzip_low_i16x8(b0, b1);
        let hi_odd = self.unzip_high_i16x8(b0, b1);
        (
            self.combine_i16x8(lo_even, hi_even),
            self.combine_i16x8(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i16x16(self, a: mask16x16<Self>, b: i16x16<Self>, c: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        let (c0, c1) = self.split_i16x16(c);
        self.combine_i16x8(self.select_i16x8(a0, b0, c0), self.select_i16x8(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i16x32<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i16x16(self, a: i16x16<Self>) -> (i16x8<Self>, i16x8<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i16x16(self, a: i16x16<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i16x8(self.neg_i16x8(a0), self.neg_i16x8(a1))
    }
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_i16x16(self, a: i16x16<Self>) -> (i32x8<Self>, i32x8<Self>) {
        let (a0, a1) = self.split_i16x16(a);
        let (a00, a01) = self.widen_i16x8(a0);
        let (a10, a11) = self.widen_i16x8(a1);
        (self.combine_i32x4(a00, a01), self.combine_i32x4(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> (i32x8<Self>, i32x8<Self>) {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        let (low0, low1) = self.widening_mul_i16x8(a0, b0);
        let (high0, high1) = self.widening_mul_i16x8(a1, b1);
        (
            self.combine_i32x4(low0, low1),
            self.combine_i32x4(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> (i32x8<Self>, i32x8<Self>) {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        let (low0, low1) = self.widening_add_i16x8(a0, b0);
        let (high0, high1) = self.widening_add_i16x8(a1, b1);
        (
            self.combine_i32x4(low0, low1),
            self.combine_i32x4(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_i16x16(self, a: i16x16<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i16x16(a);
        self.combine_i32x4(
            self.pairwise_widening_add_i16x8(a0),
            self.pairwise_widening_add_i16x8(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i32x4(
            self.pairwise_dot_product_i16x8(a0, b0),
            self.pairwise_dot_product_i16x8(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i8x16(self.narrow_i16x8(a0, a1), self.narrow_i16x8(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i8x16(
            self.saturating_narrow_i16x8(a0, a1),
            self.saturating_narrow_i16x8(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_i16x16(self, a: i16x16<Self>, b: i16x16<Self>) -> i8x32<Self> {
        let (a0, a1) = self.split_i16x16(a);
        let (b0, b1) = self.split_i16x16(b);
        self.combine_i8x16(
            self.relaxed_narrow_i16x8(a0, a1),
            self.relaxed_narrow_i16x8(b0, b1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u16x16(self, a: u16x16<Self>) -> u16x16<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u16x16(self, val: u16) -> u16x16<Self> {
        let half = self.splat_u16x8(val);
        self.combine_u16x8(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u16x16(self, a: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u16x8(self.reverse_u16x8(a1), self.reverse_u16x8(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u16x16<const SHIFT: usize>(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u16x16<const SHIFT: usize>(
        self,
        a: u16x16<Self>,
        b: u16x16<Self>,
    ) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(
            self.slide_within_blocks_u16x8::<SHIFT>(a0, b0),
            self.slide_within_blocks_u16x8::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u16x16(
        self,
        a: u16x16<Self>,
        indices: u8x32<Self>,
    ) -> u16x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u16x16(self, a: u16x16<Self>, indices: u8x32<Self>) -> u16x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u16x16(self, a: u16x16<Self>, indices: u8x32<Self>) -> u16x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u16x16(
        self,
        a: u16x16<Self>,
        b: u16x16<Self>,
        indices: u8x32<Self>,
    ) -> u16x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u16x16(
        self,
        a: u16x16<Self>,
        b: u16x16<Self>,
        indices: u8x32<Self>,
    ) -> u16x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u16x16(self, values: u16x16<Self>, mask: mask16x16<Self>) -> u16x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u16x16(
        self,
        values: u16x16<Self>,
        mask: mask16x16<Self>,
        merge: u16x16<Self>,
    ) -> u16x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u16x16(self, values: u16x16<Self>, mask: mask16x16<Self>) -> u16x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u16x16(
        self,
        values: u16x16<Self>,
        mask: mask16x16<Self>,
        merge: u16x16<Self>,
    ) -> u16x16<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u16x16(self, a: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u16x8(self.count_ones_u16x8(a0), self.count_ones_u16x8(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u16x16(self, a: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u16x8(self.count_zeros_u16x8(a0), self.count_zeros_u16x8(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.add_u16x8(a0, b0), self.add_u16x8(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(
            self.saturating_add_u16x8(a0, b0),
            self.saturating_add_u16x8(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.sub_u16x8(a0, b0), self.sub_u16x8(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(
            self.saturating_sub_u16x8(a0, b0),
            self.saturating_sub_u16x8(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.mul_u16x8(a0, b0), self.mul_u16x8(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.and_u16x8(a0, b0), self.and_u16x8(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.or_u16x8(a0, b0), self.or_u16x8(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.xor_u16x8(a0, b0), self.xor_u16x8(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u16x16(self, a: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u16x8(self.not_u16x8(a0), self.not_u16x8(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u16x8(self.shl_u16x8(a0, shift), self.shl_u16x8(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.shlv_u16x8(a0, b0), self.shlv_u16x8(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u16x16(self, a: u16x16<Self>, shift: u32) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u16x8(self.shr_u16x8(a0, shift), self.shr_u16x8(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.shrv_u16x8(a0, b0), self.shrv_u16x8(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u16x16(self, a: u16x16<Self>) -> u16 {
        let (a0, a1) = self.split_u16x16(a);
        self.reduce_max_u16x8(self.max_u16x8(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u16x16(self, a: u16x16<Self>) -> u16 {
        let (a0, a1) = self.split_u16x16(a);
        self.reduce_min_u16x8(self.min_u16x8(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u16x16(self, a: u16x16<Self>) -> u16 {
        let (a0, a1) = self.split_u16x16(a);
        self.reduce_sum_u16x8(self.add_u16x8(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u16x16(self, a: u16x16<Self>) -> u16 {
        let (a0, a1) = self.split_u16x16(a);
        self.reduce_product_u16x8(self.mul_u16x8(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.max_u16x8(a0, b0), self.max_u16x8(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.min_u16x8(a0, b0), self.min_u16x8(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u16x16(self, a: u16x16<Self>, b: u16x16<Self>, c: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        let (c0, c1) = self.split_u16x16(c);
        self.combine_u16x8(self.clamp_u16x8(a0, b0, c0), self.clamp_u16x8(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_mask16x8(self.simd_eq_u16x8(a0, b0), self.simd_eq_u16x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> {
        self.not_mask16x16(self.simd_eq_u16x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_mask16x8(self.simd_lt_u16x8(a0, b0), self.simd_lt_u16x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_mask16x8(self.simd_le_u16x8(a0, b0), self.simd_le_u16x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> {
        self.simd_le_u16x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> mask16x16<Self> {
        self.simd_lt_u16x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, _) = self.split_u16x16(a);
        let (b0, _) = self.split_u16x16(b);
        self.combine_u16x8(self.zip_low_u16x8(a0, b0), self.zip_high_u16x8(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (_, a1) = self.split_u16x16(a);
        let (_, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.zip_low_u16x8(a1, b1), self.zip_high_u16x8(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.unzip_low_u16x8(a0, a1), self.unzip_low_u16x8(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u16x8(self.unzip_high_u16x8(a0, a1), self.unzip_high_u16x8(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> (u16x16<Self>, u16x16<Self>) {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        let lo_lo = self.zip_low_u16x8(a0, b0);
        let lo_hi = self.zip_high_u16x8(a0, b0);
        let hi_lo = self.zip_low_u16x8(a1, b1);
        let hi_hi = self.zip_high_u16x8(a1, b1);
        (
            self.combine_u16x8(lo_lo, lo_hi),
            self.combine_u16x8(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> (u16x16<Self>, u16x16<Self>) {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        let lo_even = self.unzip_low_u16x8(a0, a1);
        let lo_odd = self.unzip_high_u16x8(a0, a1);
        let hi_even = self.unzip_low_u16x8(b0, b1);
        let hi_odd = self.unzip_high_u16x8(b0, b1);
        (
            self.combine_u16x8(lo_even, hi_even),
            self.combine_u16x8(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u16x16(self, a: mask16x16<Self>, b: u16x16<Self>, c: u16x16<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        let (c0, c1) = self.split_u16x16(c);
        self.combine_u16x8(self.select_u16x8(a0, b0, c0), self.select_u16x8(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u16x32<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u16x16(self, a: u16x16<Self>) -> (u16x8<Self>, u16x8<Self>);
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_u16x16(self, a: u16x16<Self>) -> (u32x8<Self>, u32x8<Self>) {
        let (a0, a1) = self.split_u16x16(a);
        let (a00, a01) = self.widen_u16x8(a0);
        let (a10, a11) = self.widen_u16x8(a1);
        (self.combine_u32x4(a00, a01), self.combine_u32x4(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> (u32x8<Self>, u32x8<Self>) {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        let (low0, low1) = self.widening_mul_u16x8(a0, b0);
        let (high0, high1) = self.widening_mul_u16x8(a1, b1);
        (
            self.combine_u32x4(low0, low1),
            self.combine_u32x4(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> (u32x8<Self>, u32x8<Self>) {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        let (low0, low1) = self.widening_add_u16x8(a0, b0);
        let (high0, high1) = self.widening_add_u16x8(a1, b1);
        (
            self.combine_u32x4(low0, low1),
            self.combine_u32x4(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_u16x16(self, a: u16x16<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u16x16(a);
        self.combine_u32x4(
            self.pairwise_widening_add_u16x8(a0),
            self.pairwise_widening_add_u16x8(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u32x4(
            self.pairwise_dot_product_u16x8(a0, b0),
            self.pairwise_dot_product_u16x8(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u8x16(self.narrow_u16x8(a0, a1), self.narrow_u16x8(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u8x16(
            self.saturating_narrow_u16x8(a0, a1),
            self.saturating_narrow_u16x8(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_u16x16(self, a: u16x16<Self>, b: u16x16<Self>) -> u8x32<Self> {
        let (a0, a1) = self.split_u16x16(a);
        let (b0, b1) = self.split_u16x16(b);
        self.combine_u8x16(
            self.relaxed_narrow_u16x8(a0, a1),
            self.relaxed_narrow_u16x8(b0, b1),
        )
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask16x16(self, val: bool) -> mask16x16<Self> {
        let half = self.splat_mask16x8(val);
        self.combine_mask16x8(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask16x16(self, bits: u64) -> mask16x16<Self> {
        let lo = self.from_bitmask_mask16x8(bits);
        let hi = self.from_bitmask_mask16x8(bits >> 8usize);
        self.combine_mask16x8(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask16x16(self, a: mask16x16<Self>) -> u64 {
        let (lo, hi) = self.split_mask16x16(a);
        let lo = self.to_bitmask_mask16x8(lo);
        let hi = self.to_bitmask_mask16x8(hi);
        lo | (hi << 8usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask16x16(self, vector: i16x16<Self>) -> mask16x16<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask16x16(self, a: mask16x16<Self>) -> i16x16<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask16x16(self, a: &mut mask16x16<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask16x16<const OFFSET: usize>(
        self,
        a: mask16x16<Self>,
    ) -> mask16x16<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask16x16<const OFFSET: usize>(
        self,
        a: mask16x16<Self>,
    ) -> mask16x16<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_mask16x16(b);
        self.combine_mask16x8(self.and_mask16x8(a0, b0), self.and_mask16x8(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_mask16x16(b);
        self.combine_mask16x8(self.or_mask16x8(a0, b0), self.or_mask16x8(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_mask16x16(b);
        self.combine_mask16x8(self.xor_mask16x8(a0, b0), self.xor_mask16x8(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        self.combine_mask16x8(self.not_mask16x8(a0), self.not_mask16x8(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask16x16(self, a: mask16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        self.combine_mask16x8(self.reverse_mask16x8(a1), self.reverse_mask16x8(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask16x16(
        self,
        a: mask16x16<Self>,
        b: mask16x16<Self>,
        c: mask16x16<Self>,
    ) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_mask16x16(b);
        let (c0, c1) = self.split_mask16x16(c);
        self.combine_mask16x8(
            self.select_mask16x8(a0, b0, c0),
            self.select_mask16x8(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_mask16x16(b);
        self.combine_mask16x8(self.simd_eq_mask16x8(a0, b0), self.simd_eq_mask16x8(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x16<Self> {
        self.not_mask16x16(self.simd_eq_mask16x16(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask16x16(self, a: mask16x16<Self>) -> bool {
        let (a0, a1) = self.split_mask16x16(a);
        self.any_true_mask16x8(self.or_mask16x8(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask16x16(self, a: mask16x16<Self>) -> bool {
        let (a0, a1) = self.split_mask16x16(a);
        self.all_true_mask16x8(self.and_mask16x8(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask16x16(self, a: mask16x16<Self>) -> bool {
        let (a0, a1) = self.split_mask16x16(a);
        self.any_false_mask16x8(self.and_mask16x8(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask16x16(self, a: mask16x16<Self>) -> bool {
        let (a0, a1) = self.split_mask16x16(a);
        self.all_false_mask16x8(self.or_mask16x8(a0, a1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask16x32<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask16x16(self, a: mask16x16<Self>) -> (mask16x8<Self>, mask16x8<Self>);
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn widen_mask16x16(self, a: mask16x16<Self>) -> (mask32x8<Self>, mask32x8<Self>) {
        let (a0, a1) = self.split_mask16x16(a);
        let (a00, a01) = self.widen_mask16x8(a0);
        let (a10, a11) = self.widen_mask16x8(a1);
        (
            self.combine_mask32x4(a00, a01),
            self.combine_mask32x4(a10, a11),
        )
    }
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn narrow_mask16x16(self, a: mask16x16<Self>, b: mask16x16<Self>) -> mask8x32<Self> {
        let (a0, a1) = self.split_mask16x16(a);
        let (b0, b1) = self.split_mask16x16(b);
        self.combine_mask8x16(self.narrow_mask16x8(a0, a1), self.narrow_mask16x8(b0, b1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i32x8(self, a: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.abs_i32x4(a0), self.abs_i32x4(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i32x8(self, val: i32) -> i32x8<Self> {
        let half = self.splat_i32x4(val);
        self.combine_i32x4(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i32x8(self, a: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.reverse_i32x4(a1), self.reverse_i32x4(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i32x8<const SHIFT: usize>(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i32x8<const SHIFT: usize>(
        self,
        a: i32x8<Self>,
        b: i32x8<Self>,
    ) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(
            self.slide_within_blocks_i32x4::<SHIFT>(a0, b0),
            self.slide_within_blocks_i32x4::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i32x8(self, a: i32x8<Self>, indices: u8x32<Self>) -> i32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i32x8(self, a: i32x8<Self>, indices: u8x32<Self>) -> i32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i32x8(self, a: i32x8<Self>, indices: u8x32<Self>) -> i32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i32x8(
        self,
        a: i32x8<Self>,
        b: i32x8<Self>,
        indices: u8x32<Self>,
    ) -> i32x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i32x8(
        self,
        a: i32x8<Self>,
        b: i32x8<Self>,
        indices: u8x32<Self>,
    ) -> i32x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i32x8(self, values: i32x8<Self>, mask: mask32x8<Self>) -> i32x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i32x8(
        self,
        values: i32x8<Self>,
        mask: mask32x8<Self>,
        merge: i32x8<Self>,
    ) -> i32x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i32x8(self, values: i32x8<Self>, mask: mask32x8<Self>) -> i32x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i32x8(
        self,
        values: i32x8<Self>,
        mask: mask32x8<Self>,
        merge: i32x8<Self>,
    ) -> i32x8<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i32x8(self, a: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.count_ones_i32x4(a0), self.count_ones_i32x4(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i32x8(self, a: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.count_zeros_i32x4(a0), self.count_zeros_i32x4(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.add_i32x4(a0, b0), self.add_i32x4(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(
            self.saturating_add_i32x4(a0, b0),
            self.saturating_add_i32x4(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.sub_i32x4(a0, b0), self.sub_i32x4(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(
            self.saturating_sub_i32x4(a0, b0),
            self.saturating_sub_i32x4(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.mul_i32x4(a0, b0), self.mul_i32x4(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.and_i32x4(a0, b0), self.and_i32x4(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.or_i32x4(a0, b0), self.or_i32x4(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.xor_i32x4(a0, b0), self.xor_i32x4(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i32x8(self, a: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.not_i32x4(a0), self.not_i32x4(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.shl_i32x4(a0, shift), self.shl_i32x4(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.shlv_i32x4(a0, b0), self.shlv_i32x4(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i32x8(self, a: i32x8<Self>, shift: u32) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.shr_i32x4(a0, shift), self.shr_i32x4(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.shrv_i32x4(a0, b0), self.shrv_i32x4(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i32x8(self, a: i32x8<Self>) -> i32 {
        let (a0, a1) = self.split_i32x8(a);
        self.reduce_max_i32x4(self.max_i32x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i32x8(self, a: i32x8<Self>) -> i32 {
        let (a0, a1) = self.split_i32x8(a);
        self.reduce_min_i32x4(self.min_i32x4(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i32x8(self, a: i32x8<Self>) -> i32 {
        let (a0, a1) = self.split_i32x8(a);
        self.reduce_sum_i32x4(self.add_i32x4(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i32x8(self, a: i32x8<Self>) -> i32 {
        let (a0, a1) = self.split_i32x8(a);
        self.reduce_product_i32x4(self.mul_i32x4(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.max_i32x4(a0, b0), self.max_i32x4(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.min_i32x4(a0, b0), self.min_i32x4(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i32x8(self, a: i32x8<Self>, b: i32x8<Self>, c: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        let (c0, c1) = self.split_i32x8(c);
        self.combine_i32x4(self.clamp_i32x4(a0, b0, c0), self.clamp_i32x4(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_mask32x4(self.simd_eq_i32x4(a0, b0), self.simd_eq_i32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> {
        self.not_mask32x8(self.simd_eq_i32x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_mask32x4(self.simd_lt_i32x4(a0, b0), self.simd_lt_i32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_mask32x4(self.simd_le_i32x4(a0, b0), self.simd_le_i32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> {
        self.simd_le_i32x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> mask32x8<Self> {
        self.simd_lt_i32x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, _) = self.split_i32x8(a);
        let (b0, _) = self.split_i32x8(b);
        self.combine_i32x4(self.zip_low_i32x4(a0, b0), self.zip_high_i32x4(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (_, a1) = self.split_i32x8(a);
        let (_, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.zip_low_i32x4(a1, b1), self.zip_high_i32x4(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.unzip_low_i32x4(a0, a1), self.unzip_low_i32x4(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i32x4(self.unzip_high_i32x4(a0, a1), self.unzip_high_i32x4(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> (i32x8<Self>, i32x8<Self>) {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        let lo_lo = self.zip_low_i32x4(a0, b0);
        let lo_hi = self.zip_high_i32x4(a0, b0);
        let hi_lo = self.zip_low_i32x4(a1, b1);
        let hi_hi = self.zip_high_i32x4(a1, b1);
        (
            self.combine_i32x4(lo_lo, lo_hi),
            self.combine_i32x4(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> (i32x8<Self>, i32x8<Self>) {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        let lo_even = self.unzip_low_i32x4(a0, a1);
        let lo_odd = self.unzip_high_i32x4(a0, a1);
        let hi_even = self.unzip_low_i32x4(b0, b1);
        let hi_odd = self.unzip_high_i32x4(b0, b1);
        (
            self.combine_i32x4(lo_even, hi_even),
            self.combine_i32x4(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i32x8(self, a: mask32x8<Self>, b: i32x8<Self>, c: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        let (c0, c1) = self.split_i32x8(c);
        self.combine_i32x4(self.select_i32x4(a0, b0, c0), self.select_i32x4(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i32x16<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i32x8(self, a: i32x8<Self>) -> (i32x4<Self>, i32x4<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i32x8(self, a: i32x8<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i32x4(self.neg_i32x4(a0), self.neg_i32x4(a1))
    }
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_i32x8(self, a: i32x8<Self>) -> (i64x4<Self>, i64x4<Self>) {
        let (a0, a1) = self.split_i32x8(a);
        let (a00, a01) = self.widen_i32x4(a0);
        let (a10, a11) = self.widen_i32x4(a1);
        (self.combine_i64x2(a00, a01), self.combine_i64x2(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> (i64x4<Self>, i64x4<Self>) {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        let (low0, low1) = self.widening_mul_i32x4(a0, b0);
        let (high0, high1) = self.widening_mul_i32x4(a1, b1);
        (
            self.combine_i64x2(low0, low1),
            self.combine_i64x2(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> (i64x4<Self>, i64x4<Self>) {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        let (low0, low1) = self.widening_add_i32x4(a0, b0);
        let (high0, high1) = self.widening_add_i32x4(a1, b1);
        (
            self.combine_i64x2(low0, low1),
            self.combine_i64x2(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_i32x8(self, a: i32x8<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_i64x2(
            self.pairwise_widening_add_i32x4(a0),
            self.pairwise_widening_add_i32x4(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i64x2(
            self.pairwise_dot_product_i32x4(a0, b0),
            self.pairwise_dot_product_i32x4(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i16x8(self.narrow_i32x4(a0, a1), self.narrow_i32x4(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i16x8(
            self.saturating_narrow_i32x4(a0, a1),
            self.saturating_narrow_i32x4(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_i32x8(self, a: i32x8<Self>, b: i32x8<Self>) -> i16x16<Self> {
        let (a0, a1) = self.split_i32x8(a);
        let (b0, b1) = self.split_i32x8(b);
        self.combine_i16x8(
            self.relaxed_narrow_i32x4(a0, a1),
            self.relaxed_narrow_i32x4(b0, b1),
        )
    }
    #[doc = "Convert each signed 32-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f32_i32x8(self, a: i32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_i32x8(a);
        self.combine_f32x4(self.cvt_f32_i32x4(a0), self.cvt_f32_i32x4(a1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u32x8(self, a: u32x8<Self>) -> u32x8<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u32x8(self, val: u32) -> u32x8<Self> {
        let half = self.splat_u32x4(val);
        self.combine_u32x4(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u32x8(self, a: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u32x4(self.reverse_u32x4(a1), self.reverse_u32x4(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u32x8<const SHIFT: usize>(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u32x8<const SHIFT: usize>(
        self,
        a: u32x8<Self>,
        b: u32x8<Self>,
    ) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(
            self.slide_within_blocks_u32x4::<SHIFT>(a0, b0),
            self.slide_within_blocks_u32x4::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u32x8(self, a: u32x8<Self>, indices: u8x32<Self>) -> u32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u32x8(self, a: u32x8<Self>, indices: u8x32<Self>) -> u32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u32x8(self, a: u32x8<Self>, indices: u8x32<Self>) -> u32x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u32x8(
        self,
        a: u32x8<Self>,
        b: u32x8<Self>,
        indices: u8x32<Self>,
    ) -> u32x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u32x8(
        self,
        a: u32x8<Self>,
        b: u32x8<Self>,
        indices: u8x32<Self>,
    ) -> u32x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u32x8(self, values: u32x8<Self>, mask: mask32x8<Self>) -> u32x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u32x8(
        self,
        values: u32x8<Self>,
        mask: mask32x8<Self>,
        merge: u32x8<Self>,
    ) -> u32x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u32x8(self, values: u32x8<Self>, mask: mask32x8<Self>) -> u32x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u32x8(
        self,
        values: u32x8<Self>,
        mask: mask32x8<Self>,
        merge: u32x8<Self>,
    ) -> u32x8<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u32x8(self, a: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u32x4(self.count_ones_u32x4(a0), self.count_ones_u32x4(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u32x8(self, a: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u32x4(self.count_zeros_u32x4(a0), self.count_zeros_u32x4(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.add_u32x4(a0, b0), self.add_u32x4(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(
            self.saturating_add_u32x4(a0, b0),
            self.saturating_add_u32x4(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.sub_u32x4(a0, b0), self.sub_u32x4(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(
            self.saturating_sub_u32x4(a0, b0),
            self.saturating_sub_u32x4(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.mul_u32x4(a0, b0), self.mul_u32x4(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.and_u32x4(a0, b0), self.and_u32x4(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.or_u32x4(a0, b0), self.or_u32x4(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.xor_u32x4(a0, b0), self.xor_u32x4(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u32x8(self, a: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u32x4(self.not_u32x4(a0), self.not_u32x4(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u32x4(self.shl_u32x4(a0, shift), self.shl_u32x4(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.shlv_u32x4(a0, b0), self.shlv_u32x4(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u32x8(self, a: u32x8<Self>, shift: u32) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u32x4(self.shr_u32x4(a0, shift), self.shr_u32x4(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.shrv_u32x4(a0, b0), self.shrv_u32x4(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u32x8(self, a: u32x8<Self>) -> u32 {
        let (a0, a1) = self.split_u32x8(a);
        self.reduce_max_u32x4(self.max_u32x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u32x8(self, a: u32x8<Self>) -> u32 {
        let (a0, a1) = self.split_u32x8(a);
        self.reduce_min_u32x4(self.min_u32x4(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u32x8(self, a: u32x8<Self>) -> u32 {
        let (a0, a1) = self.split_u32x8(a);
        self.reduce_sum_u32x4(self.add_u32x4(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u32x8(self, a: u32x8<Self>) -> u32 {
        let (a0, a1) = self.split_u32x8(a);
        self.reduce_product_u32x4(self.mul_u32x4(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.max_u32x4(a0, b0), self.max_u32x4(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.min_u32x4(a0, b0), self.min_u32x4(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u32x8(self, a: u32x8<Self>, b: u32x8<Self>, c: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        let (c0, c1) = self.split_u32x8(c);
        self.combine_u32x4(self.clamp_u32x4(a0, b0, c0), self.clamp_u32x4(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_mask32x4(self.simd_eq_u32x4(a0, b0), self.simd_eq_u32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> {
        self.not_mask32x8(self.simd_eq_u32x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_mask32x4(self.simd_lt_u32x4(a0, b0), self.simd_lt_u32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_mask32x4(self.simd_le_u32x4(a0, b0), self.simd_le_u32x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> {
        self.simd_le_u32x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> mask32x8<Self> {
        self.simd_lt_u32x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, _) = self.split_u32x8(a);
        let (b0, _) = self.split_u32x8(b);
        self.combine_u32x4(self.zip_low_u32x4(a0, b0), self.zip_high_u32x4(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (_, a1) = self.split_u32x8(a);
        let (_, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.zip_low_u32x4(a1, b1), self.zip_high_u32x4(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.unzip_low_u32x4(a0, a1), self.unzip_low_u32x4(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u32x4(self.unzip_high_u32x4(a0, a1), self.unzip_high_u32x4(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> (u32x8<Self>, u32x8<Self>) {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        let lo_lo = self.zip_low_u32x4(a0, b0);
        let lo_hi = self.zip_high_u32x4(a0, b0);
        let hi_lo = self.zip_low_u32x4(a1, b1);
        let hi_hi = self.zip_high_u32x4(a1, b1);
        (
            self.combine_u32x4(lo_lo, lo_hi),
            self.combine_u32x4(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> (u32x8<Self>, u32x8<Self>) {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        let lo_even = self.unzip_low_u32x4(a0, a1);
        let lo_odd = self.unzip_high_u32x4(a0, a1);
        let hi_even = self.unzip_low_u32x4(b0, b1);
        let hi_odd = self.unzip_high_u32x4(b0, b1);
        (
            self.combine_u32x4(lo_even, hi_even),
            self.combine_u32x4(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u32x8(self, a: mask32x8<Self>, b: u32x8<Self>, c: u32x8<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        let (c0, c1) = self.split_u32x8(c);
        self.combine_u32x4(self.select_u32x4(a0, b0, c0), self.select_u32x4(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u32x16<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u32x8(self, a: u32x8<Self>) -> (u32x4<Self>, u32x4<Self>);
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_u32x8(self, a: u32x8<Self>) -> (u64x4<Self>, u64x4<Self>) {
        let (a0, a1) = self.split_u32x8(a);
        let (a00, a01) = self.widen_u32x4(a0);
        let (a10, a11) = self.widen_u32x4(a1);
        (self.combine_u64x2(a00, a01), self.combine_u64x2(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> (u64x4<Self>, u64x4<Self>) {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        let (low0, low1) = self.widening_mul_u32x4(a0, b0);
        let (high0, high1) = self.widening_mul_u32x4(a1, b1);
        (
            self.combine_u64x2(low0, low1),
            self.combine_u64x2(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> (u64x4<Self>, u64x4<Self>) {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        let (low0, low1) = self.widening_add_u32x4(a0, b0);
        let (high0, high1) = self.widening_add_u32x4(a1, b1);
        (
            self.combine_u64x2(low0, low1),
            self.combine_u64x2(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_u32x8(self, a: u32x8<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_u64x2(
            self.pairwise_widening_add_u32x4(a0),
            self.pairwise_widening_add_u32x4(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u64x2(
            self.pairwise_dot_product_u32x4(a0, b0),
            self.pairwise_dot_product_u32x4(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u16x8(self.narrow_u32x4(a0, a1), self.narrow_u32x4(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u16x8(
            self.saturating_narrow_u32x4(a0, a1),
            self.saturating_narrow_u32x4(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_u32x8(self, a: u32x8<Self>, b: u32x8<Self>) -> u16x16<Self> {
        let (a0, a1) = self.split_u32x8(a);
        let (b0, b1) = self.split_u32x8(b);
        self.combine_u16x8(
            self.relaxed_narrow_u32x4(a0, a1),
            self.relaxed_narrow_u32x4(b0, b1),
        )
    }
    #[doc = "Convert each unsigned 32-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f32_u32x8(self, a: u32x8<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_u32x8(a);
        self.combine_f32x4(self.cvt_f32_u32x4(a0), self.cvt_f32_u32x4(a1))
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask32x8(self, val: bool) -> mask32x8<Self> {
        let half = self.splat_mask32x4(val);
        self.combine_mask32x4(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask32x8(self, bits: u64) -> mask32x8<Self> {
        let lo = self.from_bitmask_mask32x4(bits);
        let hi = self.from_bitmask_mask32x4(bits >> 4usize);
        self.combine_mask32x4(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask32x8(self, a: mask32x8<Self>) -> u64 {
        let (lo, hi) = self.split_mask32x8(a);
        let lo = self.to_bitmask_mask32x4(lo);
        let hi = self.to_bitmask_mask32x4(hi);
        lo | (hi << 4usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask32x8(self, vector: i32x8<Self>) -> mask32x8<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask32x8(self, a: mask32x8<Self>) -> i32x8<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask32x8(self, a: &mut mask32x8<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask32x8<const OFFSET: usize>(
        self,
        a: mask32x8<Self>,
    ) -> mask32x8<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask32x8<const OFFSET: usize>(
        self,
        a: mask32x8<Self>,
    ) -> mask32x8<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_mask32x8(b);
        self.combine_mask32x4(self.and_mask32x4(a0, b0), self.and_mask32x4(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_mask32x8(b);
        self.combine_mask32x4(self.or_mask32x4(a0, b0), self.or_mask32x4(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_mask32x8(b);
        self.combine_mask32x4(self.xor_mask32x4(a0, b0), self.xor_mask32x4(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        self.combine_mask32x4(self.not_mask32x4(a0), self.not_mask32x4(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask32x8(self, a: mask32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        self.combine_mask32x4(self.reverse_mask32x4(a1), self.reverse_mask32x4(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask32x8(
        self,
        a: mask32x8<Self>,
        b: mask32x8<Self>,
        c: mask32x8<Self>,
    ) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_mask32x8(b);
        let (c0, c1) = self.split_mask32x8(c);
        self.combine_mask32x4(
            self.select_mask32x4(a0, b0, c0),
            self.select_mask32x4(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_mask32x8(b);
        self.combine_mask32x4(self.simd_eq_mask32x4(a0, b0), self.simd_eq_mask32x4(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x8<Self> {
        self.not_mask32x8(self.simd_eq_mask32x8(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask32x8(self, a: mask32x8<Self>) -> bool {
        let (a0, a1) = self.split_mask32x8(a);
        self.any_true_mask32x4(self.or_mask32x4(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask32x8(self, a: mask32x8<Self>) -> bool {
        let (a0, a1) = self.split_mask32x8(a);
        self.all_true_mask32x4(self.and_mask32x4(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask32x8(self, a: mask32x8<Self>) -> bool {
        let (a0, a1) = self.split_mask32x8(a);
        self.any_false_mask32x4(self.and_mask32x4(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask32x8(self, a: mask32x8<Self>) -> bool {
        let (a0, a1) = self.split_mask32x8(a);
        self.all_false_mask32x4(self.or_mask32x4(a0, a1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask32x16<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask32x8(self, a: mask32x8<Self>) -> (mask32x4<Self>, mask32x4<Self>);
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn widen_mask32x8(self, a: mask32x8<Self>) -> (mask64x4<Self>, mask64x4<Self>) {
        let (a0, a1) = self.split_mask32x8(a);
        let (a00, a01) = self.widen_mask32x4(a0);
        let (a10, a11) = self.widen_mask32x4(a1);
        (
            self.combine_mask64x2(a00, a01),
            self.combine_mask64x2(a10, a11),
        )
    }
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn narrow_mask32x8(self, a: mask32x8<Self>, b: mask32x8<Self>) -> mask16x16<Self> {
        let (a0, a1) = self.split_mask32x8(a);
        let (b0, b1) = self.split_mask32x8(b);
        self.combine_mask16x8(self.narrow_mask32x4(a0, a1), self.narrow_mask32x4(b0, b1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.abs_f64x2(a0), self.abs_f64x2(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_f64x4(self, val: f64) -> f64x4<Self> {
        let half = self.splat_f64x2(val);
        self.combine_f64x2(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.reverse_f64x2(a1), self.reverse_f64x2(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_f64x4<const SHIFT: usize>(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_f64x4<const SHIFT: usize>(
        self,
        a: f64x4<Self>,
        b: f64x4<Self>,
    ) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(
            self.slide_within_blocks_f64x2::<SHIFT>(a0, b0),
            self.slide_within_blocks_f64x2::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_f64x4(self, a: f64x4<Self>, indices: u8x32<Self>) -> f64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_f64x4(self, a: f64x4<Self>, indices: u8x32<Self>) -> f64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_f64x4(self, a: f64x4<Self>, indices: u8x32<Self>) -> f64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_f64x4(
        self,
        a: f64x4<Self>,
        b: f64x4<Self>,
        indices: u8x32<Self>,
    ) -> f64x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_f64x4(
        self,
        a: f64x4<Self>,
        b: f64x4<Self>,
        indices: u8x32<Self>,
    ) -> f64x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_f64x4(self, values: f64x4<Self>, mask: mask64x4<Self>) -> f64x4<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_f64x4(
        self,
        values: f64x4<Self>,
        mask: mask64x4<Self>,
        merge: f64x4<Self>,
    ) -> f64x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_f64x4(self, values: f64x4<Self>, mask: mask64x4<Self>) -> f64x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_f64x4(
        self,
        values: f64x4<Self>,
        mask: mask64x4<Self>,
        merge: f64x4<Self>,
    ) -> f64x4<Self>;
    #[doc = "Negate each element of the vector."]
    #[inline(always)]
    fn neg_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.neg_f64x2(a0), self.neg_f64x2(a1))
    }
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    #[inline(always)]
    fn sqrt_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.sqrt_f64x2(a0), self.sqrt_f64x2(a1))
    }
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    #[inline(always)]
    fn approximate_recip_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(
            self.approximate_recip_f64x2(a0),
            self.approximate_recip_f64x2(a1),
        )
    }
    #[doc = "Add two vectors element-wise."]
    #[inline(always)]
    fn add_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.add_f64x2(a0, b0), self.add_f64x2(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise."]
    #[inline(always)]
    fn sub_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.sub_f64x2(a0, b0), self.sub_f64x2(a1, b1))
    }
    #[doc = "Multiply two vectors element-wise."]
    #[inline(always)]
    fn mul_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.mul_f64x2(a0, b0), self.mul_f64x2(a1, b1))
    }
    #[doc = "Divide two vectors element-wise."]
    #[inline(always)]
    fn div_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.div_f64x2(a0, b0), self.div_f64x2(a1, b1))
    }
    #[doc = "Return a vector with the magnitude of `a` and the sign of `b` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    #[inline(always)]
    fn copysign_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.copysign_f64x2(a0, b0), self.copysign_f64x2(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_f64x4(self, a: f64x4<Self>) -> f64 {
        let (a0, a1) = self.split_f64x4(a);
        self.reduce_max_f64x2(self.max_f64x2(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_f64x4(self, a: f64x4<Self>) -> f64 {
        let (a0, a1) = self.split_f64x4(a);
        self.reduce_min_f64x2(self.min_f64x2(a0, a1))
    }
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_max_precise_f64x4(self, a: f64x4<Self>) -> f64 {
        let (a0, a1) = self.split_f64x4(a);
        self.reduce_max_precise_f64x2(self.max_precise_f64x2(a0, a1))
    }
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_min_precise_f64x4(self, a: f64x4<Self>) -> f64 {
        let (a0, a1) = self.split_f64x4(a);
        self.reduce_min_precise_f64x2(self.min_precise_f64x2(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_f64x4(self, a: f64x4<Self>) -> f64 {
        let (a0, a1) = self.split_f64x4(a);
        self.reduce_sum_f64x2(self.add_f64x2(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_f64x4(self, a: f64x4<Self>) -> f64 {
        let (a0, a1) = self.split_f64x4(a);
        self.reduce_product_f64x2(self.mul_f64x2(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.max_f64x2(a0, b0), self.max_f64x2(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.min_f64x2(a0, b0), self.min_f64x2(a1, b1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn max_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(
            self.max_precise_f64x2(a0, b0),
            self.max_precise_f64x2(a1, b1),
        )
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn min_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(
            self.min_precise_f64x2(a0, b0),
            self.min_precise_f64x2(a1, b1),
        )
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_f64x4(self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let (c0, c1) = self.split_f64x4(c);
        self.combine_f64x2(self.clamp_f64x2(a0, b0, c0), self.clamp_f64x2(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_mask64x2(self.simd_eq_f64x2(a0, b0), self.simd_eq_f64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> {
        self.not_mask64x4(self.simd_eq_f64x4(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_mask64x2(self.simd_lt_f64x2(a0, b0), self.simd_lt_f64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_mask64x2(self.simd_le_f64x2(a0, b0), self.simd_le_f64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> {
        self.simd_le_f64x4(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> mask64x4<Self> {
        self.simd_lt_f64x4(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, _) = self.split_f64x4(a);
        let (b0, _) = self.split_f64x4(b);
        self.combine_f64x2(self.zip_low_f64x2(a0, b0), self.zip_high_f64x2(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (_, a1) = self.split_f64x4(a);
        let (_, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.zip_low_f64x2(a1, b1), self.zip_high_f64x2(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.unzip_low_f64x2(a0, a1), self.unzip_low_f64x2(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f64x2(self.unzip_high_f64x2(a0, a1), self.unzip_high_f64x2(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> (f64x4<Self>, f64x4<Self>) {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let lo_lo = self.zip_low_f64x2(a0, b0);
        let lo_hi = self.zip_high_f64x2(a0, b0);
        let hi_lo = self.zip_low_f64x2(a1, b1);
        let hi_hi = self.zip_high_f64x2(a1, b1);
        (
            self.combine_f64x2(lo_lo, lo_hi),
            self.combine_f64x2(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> (f64x4<Self>, f64x4<Self>) {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let lo_even = self.unzip_low_f64x2(a0, a1);
        let lo_odd = self.unzip_high_f64x2(a0, a1);
        let hi_even = self.unzip_low_f64x2(b0, b1);
        let hi_odd = self.unzip_high_f64x2(b0, b1);
        (
            self.combine_f64x2(lo_even, hi_even),
            self.combine_f64x2(lo_odd, hi_odd),
        )
    }
    #[doc = "Compute `(a * b) + c` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_add_f64x4(self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let (c0, c1) = self.split_f64x4(c);
        self.combine_f64x2(
            self.mul_add_f64x2(a0, b0, c0),
            self.mul_add_f64x2(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) + c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_add_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let (c0, c1) = self.split_f64x4(c);
        self.combine_f64x2(
            self.mul_add_precise_f64x2(a0, b0, c0),
            self.mul_add_precise_f64x2(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_sub_f64x4(self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let (c0, c1) = self.split_f64x4(c);
        self.combine_f64x2(
            self.mul_sub_f64x2(a0, b0, c0),
            self.mul_sub_f64x2(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_sub_precise_f64x4(self, a: f64x4<Self>, b: f64x4<Self>, c: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let (c0, c1) = self.split_f64x4(c);
        self.combine_f64x2(
            self.mul_sub_precise_f64x2(a0, b0, c0),
            self.mul_sub_precise_f64x2(a1, b1, c1),
        )
    }
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    #[inline(always)]
    fn floor_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.floor_f64x2(a0), self.floor_f64x2(a1))
    }
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    #[inline(always)]
    fn ceil_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.ceil_f64x2(a0), self.ceil_f64x2(a1))
    }
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    #[inline(always)]
    fn round_ties_even_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(
            self.round_ties_even_f64x2(a0),
            self.round_ties_even_f64x2(a1),
        )
    }
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    #[inline(always)]
    fn round_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.round_f64x2(a0), self.round_f64x2(a1))
    }
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `a - a.trunc()`."]
    #[inline(always)]
    fn fract_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.fract_f64x2(a0), self.fract_f64x2(a1))
    }
    #[doc = "Return the integer part of each element, rounding towards zero."]
    #[inline(always)]
    fn trunc_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.trunc_f64x2(a0), self.trunc_f64x2(a1))
    }
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_degrees_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.to_degrees_f64x2(a0), self.to_degrees_f64x2(a1))
    }
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_radians_f64x4(self, a: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_f64x2(self.to_radians_f64x2(a0), self.to_radians_f64x2(a1))
    }
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative_f64x4(self, a: f64x4<Self>) -> mask64x4<Self>;
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_f64x4(self, a: mask64x4<Self>, b: f64x4<Self>, c: f64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        let (c0, c1) = self.split_f64x4(c);
        self.combine_f64x2(self.select_f64x2(a0, b0, c0), self.select_f64x2(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f64x8<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_f64x4(self, a: f64x4<Self>) -> (f64x2<Self>, f64x2<Self>);
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nValues are rounded to the nearest representable `f32`, with ties resolved to even; overflow produces signed infinity.This is the same as the `as` operator, and follows the IEEE 754 narrowing behavior in round-to-even mode.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f32x4(self.narrow_f64x2(a0, a1), self.narrow_f64x2(b0, b1))
    }
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nFor floating-point vectors this is identical to `narrow`, including its rounding and overflow behavior.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f32x4(
            self.saturating_narrow_f64x2(a0, a1),
            self.saturating_narrow_f64x2(b0, b1),
        )
    }
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nFor floating-point vectors this is identical to `narrow`, including its rounding and overflow behavior.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_f64x4(self, a: f64x4<Self>, b: f64x4<Self>) -> f32x8<Self> {
        let (a0, a1) = self.split_f64x4(a);
        let (b0, b1) = self.split_f64x4(b);
        self.combine_f32x4(
            self.relaxed_narrow_f64x2(a0, a1),
            self.relaxed_narrow_f64x2(b0, b1),
        )
    }
    #[doc = "Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    #[inline(always)]
    fn cvt_u64_f64x4(self, a: f64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_u64x2(self.cvt_u64_f64x2(a0), self.cvt_u64_f64x2(a1))
    }
    #[doc = "Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_u64_precise_f64x4(self, a: f64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_u64x2(
            self.cvt_u64_precise_f64x2(a0),
            self.cvt_u64_precise_f64x2(a1),
        )
    }
    #[doc = "Convert each floating-point element to a signed 64-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    #[inline(always)]
    fn cvt_i64_f64x4(self, a: f64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_i64x2(self.cvt_i64_f64x2(a0), self.cvt_i64_f64x2(a1))
    }
    #[doc = "Convert each floating-point element to a signed 64-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_i64_precise_f64x4(self, a: f64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_f64x4(a);
        self.combine_i64x2(
            self.cvt_i64_precise_f64x2(a0),
            self.cvt_i64_precise_f64x2(a1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i64x4(self, a: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.abs_i64x2(a0), self.abs_i64x2(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i64x4(self, val: i64) -> i64x4<Self> {
        let half = self.splat_i64x2(val);
        self.combine_i64x2(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i64x4(self, a: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.reverse_i64x2(a1), self.reverse_i64x2(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i64x4<const SHIFT: usize>(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i64x4<const SHIFT: usize>(
        self,
        a: i64x4<Self>,
        b: i64x4<Self>,
    ) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(
            self.slide_within_blocks_i64x2::<SHIFT>(a0, b0),
            self.slide_within_blocks_i64x2::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i64x4(self, a: i64x4<Self>, indices: u8x32<Self>) -> i64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i64x4(self, a: i64x4<Self>, indices: u8x32<Self>) -> i64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i64x4(self, a: i64x4<Self>, indices: u8x32<Self>) -> i64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i64x4(
        self,
        a: i64x4<Self>,
        b: i64x4<Self>,
        indices: u8x32<Self>,
    ) -> i64x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i64x4(
        self,
        a: i64x4<Self>,
        b: i64x4<Self>,
        indices: u8x32<Self>,
    ) -> i64x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i64x4(self, values: i64x4<Self>, mask: mask64x4<Self>) -> i64x4<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i64x4(
        self,
        values: i64x4<Self>,
        mask: mask64x4<Self>,
        merge: i64x4<Self>,
    ) -> i64x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i64x4(self, values: i64x4<Self>, mask: mask64x4<Self>) -> i64x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i64x4(
        self,
        values: i64x4<Self>,
        mask: mask64x4<Self>,
        merge: i64x4<Self>,
    ) -> i64x4<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i64x4(self, a: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.count_ones_i64x2(a0), self.count_ones_i64x2(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i64x4(self, a: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.count_zeros_i64x2(a0), self.count_zeros_i64x2(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.add_i64x2(a0, b0), self.add_i64x2(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(
            self.saturating_add_i64x2(a0, b0),
            self.saturating_add_i64x2(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.sub_i64x2(a0, b0), self.sub_i64x2(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(
            self.saturating_sub_i64x2(a0, b0),
            self.saturating_sub_i64x2(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.mul_i64x2(a0, b0), self.mul_i64x2(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.and_i64x2(a0, b0), self.and_i64x2(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.or_i64x2(a0, b0), self.or_i64x2(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.xor_i64x2(a0, b0), self.xor_i64x2(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i64x4(self, a: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.not_i64x2(a0), self.not_i64x2(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.shl_i64x2(a0, shift), self.shl_i64x2(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.shlv_i64x2(a0, b0), self.shlv_i64x2(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i64x4(self, a: i64x4<Self>, shift: u32) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.shr_i64x2(a0, shift), self.shr_i64x2(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.shrv_i64x2(a0, b0), self.shrv_i64x2(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i64x4(self, a: i64x4<Self>) -> i64 {
        let (a0, a1) = self.split_i64x4(a);
        self.reduce_max_i64x2(self.max_i64x2(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i64x4(self, a: i64x4<Self>) -> i64 {
        let (a0, a1) = self.split_i64x4(a);
        self.reduce_min_i64x2(self.min_i64x2(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i64x4(self, a: i64x4<Self>) -> i64 {
        let (a0, a1) = self.split_i64x4(a);
        self.reduce_sum_i64x2(self.add_i64x2(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i64x4(self, a: i64x4<Self>) -> i64 {
        let (a0, a1) = self.split_i64x4(a);
        self.reduce_product_i64x2(self.mul_i64x2(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.max_i64x2(a0, b0), self.max_i64x2(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.min_i64x2(a0, b0), self.min_i64x2(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i64x4(self, a: i64x4<Self>, b: i64x4<Self>, c: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        let (c0, c1) = self.split_i64x4(c);
        self.combine_i64x2(self.clamp_i64x2(a0, b0, c0), self.clamp_i64x2(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_mask64x2(self.simd_eq_i64x2(a0, b0), self.simd_eq_i64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> {
        self.not_mask64x4(self.simd_eq_i64x4(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_mask64x2(self.simd_lt_i64x2(a0, b0), self.simd_lt_i64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_mask64x2(self.simd_le_i64x2(a0, b0), self.simd_le_i64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> {
        self.simd_le_i64x4(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> mask64x4<Self> {
        self.simd_lt_i64x4(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, _) = self.split_i64x4(a);
        let (b0, _) = self.split_i64x4(b);
        self.combine_i64x2(self.zip_low_i64x2(a0, b0), self.zip_high_i64x2(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (_, a1) = self.split_i64x4(a);
        let (_, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.zip_low_i64x2(a1, b1), self.zip_high_i64x2(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.unzip_low_i64x2(a0, a1), self.unzip_low_i64x2(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i64x2(self.unzip_high_i64x2(a0, a1), self.unzip_high_i64x2(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> (i64x4<Self>, i64x4<Self>) {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        let lo_lo = self.zip_low_i64x2(a0, b0);
        let lo_hi = self.zip_high_i64x2(a0, b0);
        let hi_lo = self.zip_low_i64x2(a1, b1);
        let hi_hi = self.zip_high_i64x2(a1, b1);
        (
            self.combine_i64x2(lo_lo, lo_hi),
            self.combine_i64x2(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> (i64x4<Self>, i64x4<Self>) {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        let lo_even = self.unzip_low_i64x2(a0, a1);
        let lo_odd = self.unzip_high_i64x2(a0, a1);
        let hi_even = self.unzip_low_i64x2(b0, b1);
        let hi_odd = self.unzip_high_i64x2(b0, b1);
        (
            self.combine_i64x2(lo_even, hi_even),
            self.combine_i64x2(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i64x4(self, a: mask64x4<Self>, b: i64x4<Self>, c: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        let (c0, c1) = self.split_i64x4(c);
        self.combine_i64x2(self.select_i64x2(a0, b0, c0), self.select_i64x2(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i64x8<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i64x4(self, a: i64x4<Self>) -> (i64x2<Self>, i64x2<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i64x4(self, a: i64x4<Self>) -> i64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_i64x2(self.neg_i64x2(a0), self.neg_i64x2(a1))
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i32x4(self.narrow_i64x2(a0, a1), self.narrow_i64x2(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i32x4(
            self.saturating_narrow_i64x2(a0, a1),
            self.saturating_narrow_i64x2(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_i64x4(self, a: i64x4<Self>, b: i64x4<Self>) -> i32x8<Self> {
        let (a0, a1) = self.split_i64x4(a);
        let (b0, b1) = self.split_i64x4(b);
        self.combine_i32x4(
            self.relaxed_narrow_i64x2(a0, a1),
            self.relaxed_narrow_i64x2(b0, b1),
        )
    }
    #[doc = "Convert each signed 64-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f64_i64x4(self, a: i64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_i64x4(a);
        self.combine_f64x2(self.cvt_f64_i64x2(a0), self.cvt_f64_i64x2(a1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u64x4(self, a: u64x4<Self>) -> u64x4<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u64x4(self, val: u64) -> u64x4<Self> {
        let half = self.splat_u64x2(val);
        self.combine_u64x2(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u64x4(self, a: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_u64x2(self.reverse_u64x2(a1), self.reverse_u64x2(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u64x4<const SHIFT: usize>(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u64x4<const SHIFT: usize>(
        self,
        a: u64x4<Self>,
        b: u64x4<Self>,
    ) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(
            self.slide_within_blocks_u64x2::<SHIFT>(a0, b0),
            self.slide_within_blocks_u64x2::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u64x4(self, a: u64x4<Self>, indices: u8x32<Self>) -> u64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u64x4(self, a: u64x4<Self>, indices: u8x32<Self>) -> u64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u64x4(self, a: u64x4<Self>, indices: u8x32<Self>) -> u64x4<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x32(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u64x4(
        self,
        a: u64x4<Self>,
        b: u64x4<Self>,
        indices: u8x32<Self>,
    ) -> u64x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u64x4(
        self,
        a: u64x4<Self>,
        b: u64x4<Self>,
        indices: u8x32<Self>,
    ) -> u64x4<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x32(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u64x4(self, values: u64x4<Self>, mask: mask64x4<Self>) -> u64x4<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u64x4(
        self,
        values: u64x4<Self>,
        mask: mask64x4<Self>,
        merge: u64x4<Self>,
    ) -> u64x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u64x4(self, values: u64x4<Self>, mask: mask64x4<Self>) -> u64x4<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u64x4(
        self,
        values: u64x4<Self>,
        mask: mask64x4<Self>,
        merge: u64x4<Self>,
    ) -> u64x4<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u64x4(self, a: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_u64x2(self.count_ones_u64x2(a0), self.count_ones_u64x2(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u64x4(self, a: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_u64x2(self.count_zeros_u64x2(a0), self.count_zeros_u64x2(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.add_u64x2(a0, b0), self.add_u64x2(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(
            self.saturating_add_u64x2(a0, b0),
            self.saturating_add_u64x2(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.sub_u64x2(a0, b0), self.sub_u64x2(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(
            self.saturating_sub_u64x2(a0, b0),
            self.saturating_sub_u64x2(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.mul_u64x2(a0, b0), self.mul_u64x2(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.and_u64x2(a0, b0), self.and_u64x2(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.or_u64x2(a0, b0), self.or_u64x2(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.xor_u64x2(a0, b0), self.xor_u64x2(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u64x4(self, a: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_u64x2(self.not_u64x2(a0), self.not_u64x2(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_u64x2(self.shl_u64x2(a0, shift), self.shl_u64x2(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.shlv_u64x2(a0, b0), self.shlv_u64x2(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u64x4(self, a: u64x4<Self>, shift: u32) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_u64x2(self.shr_u64x2(a0, shift), self.shr_u64x2(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.shrv_u64x2(a0, b0), self.shrv_u64x2(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u64x4(self, a: u64x4<Self>) -> u64 {
        let (a0, a1) = self.split_u64x4(a);
        self.reduce_max_u64x2(self.max_u64x2(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u64x4(self, a: u64x4<Self>) -> u64 {
        let (a0, a1) = self.split_u64x4(a);
        self.reduce_min_u64x2(self.min_u64x2(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u64x4(self, a: u64x4<Self>) -> u64 {
        let (a0, a1) = self.split_u64x4(a);
        self.reduce_sum_u64x2(self.add_u64x2(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u64x4(self, a: u64x4<Self>) -> u64 {
        let (a0, a1) = self.split_u64x4(a);
        self.reduce_product_u64x2(self.mul_u64x2(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.max_u64x2(a0, b0), self.max_u64x2(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.min_u64x2(a0, b0), self.min_u64x2(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u64x4(self, a: u64x4<Self>, b: u64x4<Self>, c: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        let (c0, c1) = self.split_u64x4(c);
        self.combine_u64x2(self.clamp_u64x2(a0, b0, c0), self.clamp_u64x2(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_mask64x2(self.simd_eq_u64x2(a0, b0), self.simd_eq_u64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> {
        self.not_mask64x4(self.simd_eq_u64x4(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_mask64x2(self.simd_lt_u64x2(a0, b0), self.simd_lt_u64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_mask64x2(self.simd_le_u64x2(a0, b0), self.simd_le_u64x2(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> {
        self.simd_le_u64x4(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> mask64x4<Self> {
        self.simd_lt_u64x4(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, _) = self.split_u64x4(a);
        let (b0, _) = self.split_u64x4(b);
        self.combine_u64x2(self.zip_low_u64x2(a0, b0), self.zip_high_u64x2(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (_, a1) = self.split_u64x4(a);
        let (_, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.zip_low_u64x2(a1, b1), self.zip_high_u64x2(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.unzip_low_u64x2(a0, a1), self.unzip_low_u64x2(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u64x2(self.unzip_high_u64x2(a0, a1), self.unzip_high_u64x2(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> (u64x4<Self>, u64x4<Self>) {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        let lo_lo = self.zip_low_u64x2(a0, b0);
        let lo_hi = self.zip_high_u64x2(a0, b0);
        let hi_lo = self.zip_low_u64x2(a1, b1);
        let hi_hi = self.zip_high_u64x2(a1, b1);
        (
            self.combine_u64x2(lo_lo, lo_hi),
            self.combine_u64x2(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> (u64x4<Self>, u64x4<Self>) {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        let lo_even = self.unzip_low_u64x2(a0, a1);
        let lo_odd = self.unzip_high_u64x2(a0, a1);
        let hi_even = self.unzip_low_u64x2(b0, b1);
        let hi_odd = self.unzip_high_u64x2(b0, b1);
        (
            self.combine_u64x2(lo_even, hi_even),
            self.combine_u64x2(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u64x4(self, a: mask64x4<Self>, b: u64x4<Self>, c: u64x4<Self>) -> u64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        let (c0, c1) = self.split_u64x4(c);
        self.combine_u64x2(self.select_u64x2(a0, b0, c0), self.select_u64x2(a1, b1, c1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u64x8<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u64x4(self, a: u64x4<Self>) -> (u64x2<Self>, u64x2<Self>);
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u32x4(self.narrow_u64x2(a0, a1), self.narrow_u64x2(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u32x4(
            self.saturating_narrow_u64x2(a0, a1),
            self.saturating_narrow_u64x2(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_u64x4(self, a: u64x4<Self>, b: u64x4<Self>) -> u32x8<Self> {
        let (a0, a1) = self.split_u64x4(a);
        let (b0, b1) = self.split_u64x4(b);
        self.combine_u32x4(
            self.relaxed_narrow_u64x2(a0, a1),
            self.relaxed_narrow_u64x2(b0, b1),
        )
    }
    #[doc = "Convert each unsigned 64-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f64_u64x4(self, a: u64x4<Self>) -> f64x4<Self> {
        let (a0, a1) = self.split_u64x4(a);
        self.combine_f64x2(self.cvt_f64_u64x2(a0), self.cvt_f64_u64x2(a1))
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask64x4(self, val: bool) -> mask64x4<Self> {
        let half = self.splat_mask64x2(val);
        self.combine_mask64x2(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask64x4(self, bits: u64) -> mask64x4<Self> {
        let lo = self.from_bitmask_mask64x2(bits);
        let hi = self.from_bitmask_mask64x2(bits >> 2usize);
        self.combine_mask64x2(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask64x4(self, a: mask64x4<Self>) -> u64 {
        let (lo, hi) = self.split_mask64x4(a);
        let lo = self.to_bitmask_mask64x2(lo);
        let hi = self.to_bitmask_mask64x2(hi);
        lo | (hi << 2usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask64x4(self, vector: i64x4<Self>) -> mask64x4<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask64x4(self, a: mask64x4<Self>) -> i64x4<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask64x4(self, a: &mut mask64x4<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask64x4<const OFFSET: usize>(
        self,
        a: mask64x4<Self>,
    ) -> mask64x4<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask64x4<const OFFSET: usize>(
        self,
        a: mask64x4<Self>,
    ) -> mask64x4<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_mask64x4(b);
        self.combine_mask64x2(self.and_mask64x2(a0, b0), self.and_mask64x2(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_mask64x4(b);
        self.combine_mask64x2(self.or_mask64x2(a0, b0), self.or_mask64x2(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_mask64x4(b);
        self.combine_mask64x2(self.xor_mask64x2(a0, b0), self.xor_mask64x2(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        self.combine_mask64x2(self.not_mask64x2(a0), self.not_mask64x2(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask64x4(self, a: mask64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        self.combine_mask64x2(self.reverse_mask64x2(a1), self.reverse_mask64x2(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask64x4(
        self,
        a: mask64x4<Self>,
        b: mask64x4<Self>,
        c: mask64x4<Self>,
    ) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_mask64x4(b);
        let (c0, c1) = self.split_mask64x4(c);
        self.combine_mask64x2(
            self.select_mask64x2(a0, b0, c0),
            self.select_mask64x2(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_mask64x4(b);
        self.combine_mask64x2(self.simd_eq_mask64x2(a0, b0), self.simd_eq_mask64x2(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x4<Self> {
        self.not_mask64x4(self.simd_eq_mask64x4(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask64x4(self, a: mask64x4<Self>) -> bool {
        let (a0, a1) = self.split_mask64x4(a);
        self.any_true_mask64x2(self.or_mask64x2(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask64x4(self, a: mask64x4<Self>) -> bool {
        let (a0, a1) = self.split_mask64x4(a);
        self.all_true_mask64x2(self.and_mask64x2(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask64x4(self, a: mask64x4<Self>) -> bool {
        let (a0, a1) = self.split_mask64x4(a);
        self.any_false_mask64x2(self.and_mask64x2(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask64x4(self, a: mask64x4<Self>) -> bool {
        let (a0, a1) = self.split_mask64x4(a);
        self.all_false_mask64x2(self.or_mask64x2(a0, a1))
    }
    #[doc = "Combine two vectors into a single vector with twice the width.\n\n`a` provides the lower elements and `b` provides the upper elements."]
    fn combine_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask64x8<Self>;
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask64x4(self, a: mask64x4<Self>) -> (mask64x2<Self>, mask64x2<Self>);
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn narrow_mask64x4(self, a: mask64x4<Self>, b: mask64x4<Self>) -> mask32x8<Self> {
        let (a0, a1) = self.split_mask64x4(a);
        let (b0, b1) = self.split_mask64x4(b);
        self.combine_mask32x4(self.narrow_mask64x2(a0, a1), self.narrow_mask64x2(b0, b1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.abs_f32x8(a0), self.abs_f32x8(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_f32x16(self, val: f32) -> f32x16<Self> {
        let half = self.splat_f32x8(val);
        self.combine_f32x8(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.reverse_f32x8(a1), self.reverse_f32x8(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_f32x16<const SHIFT: usize>(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_f32x16<const SHIFT: usize>(
        self,
        a: f32x16<Self>,
        b: f32x16<Self>,
    ) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(
            self.slide_within_blocks_f32x8::<SHIFT>(a0, b0),
            self.slide_within_blocks_f32x8::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_f32x16(
        self,
        a: f32x16<Self>,
        indices: u8x64<Self>,
    ) -> f32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_f32x16(self, a: f32x16<Self>, indices: u8x64<Self>) -> f32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_f32x16(self, a: f32x16<Self>, indices: u8x64<Self>) -> f32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_f32x16(
        self,
        a: f32x16<Self>,
        b: f32x16<Self>,
        indices: u8x64<Self>,
    ) -> f32x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_f32x16(
        self,
        a: f32x16<Self>,
        b: f32x16<Self>,
        indices: u8x64<Self>,
    ) -> f32x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_f32x16(self, values: f32x16<Self>, mask: mask32x16<Self>) -> f32x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_f32x16(
        self,
        values: f32x16<Self>,
        mask: mask32x16<Self>,
        merge: f32x16<Self>,
    ) -> f32x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_f32x16(self, values: f32x16<Self>, mask: mask32x16<Self>) -> f32x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_f32x16(
        self,
        values: f32x16<Self>,
        mask: mask32x16<Self>,
        merge: f32x16<Self>,
    ) -> f32x16<Self>;
    #[doc = "Negate each element of the vector."]
    #[inline(always)]
    fn neg_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.neg_f32x8(a0), self.neg_f32x8(a1))
    }
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    #[inline(always)]
    fn sqrt_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.sqrt_f32x8(a0), self.sqrt_f32x8(a1))
    }
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    #[inline(always)]
    fn approximate_recip_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(
            self.approximate_recip_f32x8(a0),
            self.approximate_recip_f32x8(a1),
        )
    }
    #[doc = "Add two vectors element-wise."]
    #[inline(always)]
    fn add_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.add_f32x8(a0, b0), self.add_f32x8(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise."]
    #[inline(always)]
    fn sub_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.sub_f32x8(a0, b0), self.sub_f32x8(a1, b1))
    }
    #[doc = "Multiply two vectors element-wise."]
    #[inline(always)]
    fn mul_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.mul_f32x8(a0, b0), self.mul_f32x8(a1, b1))
    }
    #[doc = "Divide two vectors element-wise."]
    #[inline(always)]
    fn div_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.div_f32x8(a0, b0), self.div_f32x8(a1, b1))
    }
    #[doc = "Return a vector with the magnitude of `a` and the sign of `b` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    #[inline(always)]
    fn copysign_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.copysign_f32x8(a0, b0), self.copysign_f32x8(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_f32x16(self, a: f32x16<Self>) -> f32 {
        let (a0, a1) = self.split_f32x16(a);
        self.reduce_max_f32x8(self.max_f32x8(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_f32x16(self, a: f32x16<Self>) -> f32 {
        let (a0, a1) = self.split_f32x16(a);
        self.reduce_min_f32x8(self.min_f32x8(a0, a1))
    }
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_max_precise_f32x16(self, a: f32x16<Self>) -> f32 {
        let (a0, a1) = self.split_f32x16(a);
        self.reduce_max_precise_f32x8(self.max_precise_f32x8(a0, a1))
    }
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_min_precise_f32x16(self, a: f32x16<Self>) -> f32 {
        let (a0, a1) = self.split_f32x16(a);
        self.reduce_min_precise_f32x8(self.min_precise_f32x8(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_f32x16(self, a: f32x16<Self>) -> f32 {
        let (a0, a1) = self.split_f32x16(a);
        self.reduce_sum_f32x8(self.add_f32x8(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_f32x16(self, a: f32x16<Self>) -> f32 {
        let (a0, a1) = self.split_f32x16(a);
        self.reduce_product_f32x8(self.mul_f32x8(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.max_f32x8(a0, b0), self.max_f32x8(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.min_f32x8(a0, b0), self.min_f32x8(a1, b1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn max_precise_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(
            self.max_precise_f32x8(a0, b0),
            self.max_precise_f32x8(a1, b1),
        )
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn min_precise_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(
            self.min_precise_f32x8(a0, b0),
            self.min_precise_f32x8(a1, b1),
        )
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_f32x16(self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let (c0, c1) = self.split_f32x16(c);
        self.combine_f32x8(self.clamp_f32x8(a0, b0, c0), self.clamp_f32x8(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_mask32x8(self.simd_eq_f32x8(a0, b0), self.simd_eq_f32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> {
        self.not_mask32x16(self.simd_eq_f32x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_mask32x8(self.simd_lt_f32x8(a0, b0), self.simd_lt_f32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_mask32x8(self.simd_le_f32x8(a0, b0), self.simd_le_f32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> {
        self.simd_le_f32x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> mask32x16<Self> {
        self.simd_lt_f32x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, _) = self.split_f32x16(a);
        let (b0, _) = self.split_f32x16(b);
        self.combine_f32x8(self.zip_low_f32x8(a0, b0), self.zip_high_f32x8(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (_, a1) = self.split_f32x16(a);
        let (_, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.zip_low_f32x8(a1, b1), self.zip_high_f32x8(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.unzip_low_f32x8(a0, a1), self.unzip_low_f32x8(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        self.combine_f32x8(self.unzip_high_f32x8(a0, a1), self.unzip_high_f32x8(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> (f32x16<Self>, f32x16<Self>) {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let lo_lo = self.zip_low_f32x8(a0, b0);
        let lo_hi = self.zip_high_f32x8(a0, b0);
        let hi_lo = self.zip_low_f32x8(a1, b1);
        let hi_hi = self.zip_high_f32x8(a1, b1);
        (
            self.combine_f32x8(lo_lo, lo_hi),
            self.combine_f32x8(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_f32x16(self, a: f32x16<Self>, b: f32x16<Self>) -> (f32x16<Self>, f32x16<Self>) {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let lo_even = self.unzip_low_f32x8(a0, a1);
        let lo_odd = self.unzip_high_f32x8(a0, a1);
        let hi_even = self.unzip_low_f32x8(b0, b1);
        let hi_odd = self.unzip_high_f32x8(b0, b1);
        (
            self.combine_f32x8(lo_even, hi_even),
            self.combine_f32x8(lo_odd, hi_odd),
        )
    }
    #[doc = "Compute `(a * b) + c` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_add_f32x16(self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let (c0, c1) = self.split_f32x16(c);
        self.combine_f32x8(
            self.mul_add_f32x8(a0, b0, c0),
            self.mul_add_f32x8(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) + c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_add_precise_f32x16(
        self,
        a: f32x16<Self>,
        b: f32x16<Self>,
        c: f32x16<Self>,
    ) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let (c0, c1) = self.split_f32x16(c);
        self.combine_f32x8(
            self.mul_add_precise_f32x8(a0, b0, c0),
            self.mul_add_precise_f32x8(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_sub_f32x16(self, a: f32x16<Self>, b: f32x16<Self>, c: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let (c0, c1) = self.split_f32x16(c);
        self.combine_f32x8(
            self.mul_sub_f32x8(a0, b0, c0),
            self.mul_sub_f32x8(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_sub_precise_f32x16(
        self,
        a: f32x16<Self>,
        b: f32x16<Self>,
        c: f32x16<Self>,
    ) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let (c0, c1) = self.split_f32x16(c);
        self.combine_f32x8(
            self.mul_sub_precise_f32x8(a0, b0, c0),
            self.mul_sub_precise_f32x8(a1, b1, c1),
        )
    }
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    #[inline(always)]
    fn floor_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.floor_f32x8(a0), self.floor_f32x8(a1))
    }
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    #[inline(always)]
    fn ceil_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.ceil_f32x8(a0), self.ceil_f32x8(a1))
    }
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    #[inline(always)]
    fn round_ties_even_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(
            self.round_ties_even_f32x8(a0),
            self.round_ties_even_f32x8(a1),
        )
    }
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    #[inline(always)]
    fn round_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.round_f32x8(a0), self.round_f32x8(a1))
    }
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `a - a.trunc()`."]
    #[inline(always)]
    fn fract_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.fract_f32x8(a0), self.fract_f32x8(a1))
    }
    #[doc = "Return the integer part of each element, rounding towards zero."]
    #[inline(always)]
    fn trunc_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.trunc_f32x8(a0), self.trunc_f32x8(a1))
    }
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_degrees_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.to_degrees_f32x8(a0), self.to_degrees_f32x8(a1))
    }
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_radians_f32x16(self, a: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_f32x8(self.to_radians_f32x8(a0), self.to_radians_f32x8(a1))
    }
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative_f32x16(self, a: f32x16<Self>) -> mask32x16<Self>;
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_f32x16(self, a: mask32x16<Self>, b: f32x16<Self>, c: f32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_f32x16(b);
        let (c0, c1) = self.split_f32x16(c);
        self.combine_f32x8(self.select_f32x8(a0, b0, c0), self.select_f32x8(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_f32x16(self, a: f32x16<Self>) -> (f32x8<Self>, f32x8<Self>);
    #[doc = "Widen every `f32` lane exactly into two same-width `f64` vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_f32x16(self, a: f32x16<Self>) -> (f64x8<Self>, f64x8<Self>) {
        let (a0, a1) = self.split_f32x16(a);
        let (a00, a01) = self.widen_f32x8(a0);
        let (a10, a11) = self.widen_f32x8(a1);
        (self.combine_f64x4(a00, a01), self.combine_f64x4(a10, a11))
    }
    #[doc = "Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results.\n\nOn x86 platforms below AVX-512, this operation will still be slower than converting to `i32`, because there is no native instruction for converting to `u32`.\nIf you know your values fit within range of an `i32`, you should convert to an `i32` and cast to your desired datatype afterwards."]
    #[inline(always)]
    fn cvt_u32_f32x16(self, a: f32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_u32x8(self.cvt_u32_f32x8(a0), self.cvt_u32_f32x8(a1))
    }
    #[doc = "Convert each floating-point element to an unsigned 32-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_u32_precise_f32x16(self, a: f32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_u32x8(
            self.cvt_u32_precise_f32x8(a0),
            self.cvt_u32_precise_f32x8(a1),
        )
    }
    #[doc = "Convert each floating-point element to a signed 32-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    #[inline(always)]
    fn cvt_i32_f32x16(self, a: f32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_i32x8(self.cvt_i32_f32x8(a0), self.cvt_i32_f32x8(a1))
    }
    #[doc = "Convert each floating-point element to a signed 32-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_i32_precise_f32x16(self, a: f32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_f32x16(a);
        self.combine_i32x8(
            self.cvt_i32_precise_f32x8(a0),
            self.cvt_i32_precise_f32x8(a1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i8x64(self, a: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.abs_i8x32(a0), self.abs_i8x32(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i8x64(self, val: i8) -> i8x64<Self> {
        let half = self.splat_i8x32(val);
        self.combine_i8x32(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i8x64(self, a: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.reverse_i8x32(a1), self.reverse_i8x32(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i8x64<const SHIFT: usize>(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i8x64<const SHIFT: usize>(
        self,
        a: i8x64<Self>,
        b: i8x64<Self>,
    ) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(
            self.slide_within_blocks_i8x32::<SHIFT>(a0, b0),
            self.slide_within_blocks_i8x32::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i8x64(self, a: i8x64<Self>, indices: u8x64<Self>) -> i8x64<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i8x64(self, a: i8x64<Self>, indices: u8x64<Self>) -> i8x64<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i8x64(self, a: i8x64<Self>, indices: u8x64<Self>) -> i8x64<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i8x64(
        self,
        a: i8x64<Self>,
        b: i8x64<Self>,
        indices: u8x64<Self>,
    ) -> i8x64<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i8x64(
        self,
        a: i8x64<Self>,
        b: i8x64<Self>,
        indices: u8x64<Self>,
    ) -> i8x64<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i8x64(self, values: i8x64<Self>, mask: mask8x64<Self>) -> i8x64<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i8x64(
        self,
        values: i8x64<Self>,
        mask: mask8x64<Self>,
        merge: i8x64<Self>,
    ) -> i8x64<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i8x64(self, values: i8x64<Self>, mask: mask8x64<Self>) -> i8x64<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i8x64(
        self,
        values: i8x64<Self>,
        mask: mask8x64<Self>,
        merge: i8x64<Self>,
    ) -> i8x64<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i8x64(self, a: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.count_ones_i8x32(a0), self.count_ones_i8x32(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i8x64(self, a: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.count_zeros_i8x32(a0), self.count_zeros_i8x32(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.add_i8x32(a0, b0), self.add_i8x32(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(
            self.saturating_add_i8x32(a0, b0),
            self.saturating_add_i8x32(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.sub_i8x32(a0, b0), self.sub_i8x32(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(
            self.saturating_sub_i8x32(a0, b0),
            self.saturating_sub_i8x32(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.mul_i8x32(a0, b0), self.mul_i8x32(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.and_i8x32(a0, b0), self.and_i8x32(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.or_i8x32(a0, b0), self.or_i8x32(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.xor_i8x32(a0, b0), self.xor_i8x32(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i8x64(self, a: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.not_i8x32(a0), self.not_i8x32(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.shl_i8x32(a0, shift), self.shl_i8x32(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.shlv_i8x32(a0, b0), self.shlv_i8x32(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i8x64(self, a: i8x64<Self>, shift: u32) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.shr_i8x32(a0, shift), self.shr_i8x32(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.shrv_i8x32(a0, b0), self.shrv_i8x32(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i8x64(self, a: i8x64<Self>) -> i8 {
        let (a0, a1) = self.split_i8x64(a);
        self.reduce_max_i8x32(self.max_i8x32(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i8x64(self, a: i8x64<Self>) -> i8 {
        let (a0, a1) = self.split_i8x64(a);
        self.reduce_min_i8x32(self.min_i8x32(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i8x64(self, a: i8x64<Self>) -> i8 {
        let (a0, a1) = self.split_i8x64(a);
        self.reduce_sum_i8x32(self.add_i8x32(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i8x64(self, a: i8x64<Self>) -> i8 {
        let (a0, a1) = self.split_i8x64(a);
        self.reduce_product_i8x32(self.mul_i8x32(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.max_i8x32(a0, b0), self.max_i8x32(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.min_i8x32(a0, b0), self.min_i8x32(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i8x64(self, a: i8x64<Self>, b: i8x64<Self>, c: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        let (c0, c1) = self.split_i8x64(c);
        self.combine_i8x32(self.clamp_i8x32(a0, b0, c0), self.clamp_i8x32(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_mask8x32(self.simd_eq_i8x32(a0, b0), self.simd_eq_i8x32(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> {
        self.not_mask8x64(self.simd_eq_i8x64(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_mask8x32(self.simd_lt_i8x32(a0, b0), self.simd_lt_i8x32(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_mask8x32(self.simd_le_i8x32(a0, b0), self.simd_le_i8x32(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> {
        self.simd_le_i8x64(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> mask8x64<Self> {
        self.simd_lt_i8x64(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, _) = self.split_i8x64(a);
        let (b0, _) = self.split_i8x64(b);
        self.combine_i8x32(self.zip_low_i8x32(a0, b0), self.zip_high_i8x32(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (_, a1) = self.split_i8x64(a);
        let (_, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.zip_low_i8x32(a1, b1), self.zip_high_i8x32(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.unzip_low_i8x32(a0, a1), self.unzip_low_i8x32(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i8x32(self.unzip_high_i8x32(a0, a1), self.unzip_high_i8x32(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> (i8x64<Self>, i8x64<Self>) {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        let lo_lo = self.zip_low_i8x32(a0, b0);
        let lo_hi = self.zip_high_i8x32(a0, b0);
        let hi_lo = self.zip_low_i8x32(a1, b1);
        let hi_hi = self.zip_high_i8x32(a1, b1);
        (
            self.combine_i8x32(lo_lo, lo_hi),
            self.combine_i8x32(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> (i8x64<Self>, i8x64<Self>) {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        let lo_even = self.unzip_low_i8x32(a0, a1);
        let lo_odd = self.unzip_high_i8x32(a0, a1);
        let hi_even = self.unzip_low_i8x32(b0, b1);
        let hi_odd = self.unzip_high_i8x32(b0, b1);
        (
            self.combine_i8x32(lo_even, hi_even),
            self.combine_i8x32(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i8x64(self, a: mask8x64<Self>, b: i8x64<Self>, c: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        let (c0, c1) = self.split_i8x64(c);
        self.combine_i8x32(self.select_i8x32(a0, b0, c0), self.select_i8x32(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i8x64(self, a: i8x64<Self>) -> (i8x32<Self>, i8x32<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i8x64(self, a: i8x64<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i8x32(self.neg_i8x32(a0), self.neg_i8x32(a1))
    }
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_i8x64(self, a: i8x64<Self>) -> (i16x32<Self>, i16x32<Self>) {
        let (a0, a1) = self.split_i8x64(a);
        let (a00, a01) = self.widen_i8x32(a0);
        let (a10, a11) = self.widen_i8x32(a1);
        (self.combine_i16x16(a00, a01), self.combine_i16x16(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> (i16x32<Self>, i16x32<Self>) {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        let (low0, low1) = self.widening_mul_i8x32(a0, b0);
        let (high0, high1) = self.widening_mul_i8x32(a1, b1);
        (
            self.combine_i16x16(low0, low1),
            self.combine_i16x16(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> (i16x32<Self>, i16x32<Self>) {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        let (low0, low1) = self.widening_add_i8x32(a0, b0);
        let (high0, high1) = self.widening_add_i8x32(a1, b1);
        (
            self.combine_i16x16(low0, low1),
            self.combine_i16x16(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_i8x64(self, a: i8x64<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i8x64(a);
        self.combine_i16x16(
            self.pairwise_widening_add_i8x32(a0),
            self.pairwise_widening_add_i8x32(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_i8x64(self, a: i8x64<Self>, b: i8x64<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i8x64(a);
        let (b0, b1) = self.split_i8x64(b);
        self.combine_i16x16(
            self.pairwise_dot_product_i8x32(a0, b0),
            self.pairwise_dot_product_i8x32(a1, b1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u8x64(self, a: u8x64<Self>) -> u8x64<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u8x64(self, val: u8) -> u8x64<Self> {
        let half = self.splat_u8x32(val);
        self.combine_u8x32(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u8x64(self, a: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u8x32(self.reverse_u8x32(a1), self.reverse_u8x32(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u8x64<const SHIFT: usize>(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u8x64<const SHIFT: usize>(
        self,
        a: u8x64<Self>,
        b: u8x64<Self>,
    ) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(
            self.slide_within_blocks_u8x32::<SHIFT>(a0, b0),
            self.slide_within_blocks_u8x32::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u8x64(self, a: u8x64<Self>, indices: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (indices0, indices1) = self.split_u8x64(indices);
        self.combine_u8x32(
            self.swizzle_dyn_within_blocks_u8x32(a0, indices0),
            self.swizzle_dyn_within_blocks_u8x32(a1, indices1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn swizzle_dyn_u8x64(self, a: u8x64<Self>, indices: u8x64<Self>) -> u8x64<Self>;
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    fn swizzle_dyn_precise_u8x64(self, a: u8x64<Self>, indices: u8x64<Self>) -> u8x64<Self>;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn concat_swizzle_dyn_u8x64(
        self,
        a: u8x64<Self>,
        b: u8x64<Self>,
        indices: u8x64<Self>,
    ) -> u8x64<Self>;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    fn concat_swizzle_dyn_precise_u8x64(
        self,
        a: u8x64<Self>,
        b: u8x64<Self>,
        indices: u8x64<Self>,
    ) -> u8x64<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u8x64(self, values: u8x64<Self>, mask: mask8x64<Self>) -> u8x64<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u8x64(
        self,
        values: u8x64<Self>,
        mask: mask8x64<Self>,
        merge: u8x64<Self>,
    ) -> u8x64<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u8x64(self, values: u8x64<Self>, mask: mask8x64<Self>) -> u8x64<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u8x64(
        self,
        values: u8x64<Self>,
        mask: mask8x64<Self>,
        merge: u8x64<Self>,
    ) -> u8x64<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u8x64(self, a: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u8x32(self.count_ones_u8x32(a0), self.count_ones_u8x32(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u8x64(self, a: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u8x32(self.count_zeros_u8x32(a0), self.count_zeros_u8x32(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.add_u8x32(a0, b0), self.add_u8x32(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(
            self.saturating_add_u8x32(a0, b0),
            self.saturating_add_u8x32(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.sub_u8x32(a0, b0), self.sub_u8x32(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(
            self.saturating_sub_u8x32(a0, b0),
            self.saturating_sub_u8x32(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.mul_u8x32(a0, b0), self.mul_u8x32(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.and_u8x32(a0, b0), self.and_u8x32(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.or_u8x32(a0, b0), self.or_u8x32(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.xor_u8x32(a0, b0), self.xor_u8x32(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u8x64(self, a: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u8x32(self.not_u8x32(a0), self.not_u8x32(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u8x32(self.shl_u8x32(a0, shift), self.shl_u8x32(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.shlv_u8x32(a0, b0), self.shlv_u8x32(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u8x64(self, a: u8x64<Self>, shift: u32) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u8x32(self.shr_u8x32(a0, shift), self.shr_u8x32(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.shrv_u8x32(a0, b0), self.shrv_u8x32(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u8x64(self, a: u8x64<Self>) -> u8 {
        let (a0, a1) = self.split_u8x64(a);
        self.reduce_max_u8x32(self.max_u8x32(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u8x64(self, a: u8x64<Self>) -> u8 {
        let (a0, a1) = self.split_u8x64(a);
        self.reduce_min_u8x32(self.min_u8x32(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u8x64(self, a: u8x64<Self>) -> u8 {
        let (a0, a1) = self.split_u8x64(a);
        self.reduce_sum_u8x32(self.add_u8x32(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u8x64(self, a: u8x64<Self>) -> u8 {
        let (a0, a1) = self.split_u8x64(a);
        self.reduce_product_u8x32(self.mul_u8x32(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.max_u8x32(a0, b0), self.max_u8x32(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.min_u8x32(a0, b0), self.min_u8x32(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u8x64(self, a: u8x64<Self>, b: u8x64<Self>, c: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        let (c0, c1) = self.split_u8x64(c);
        self.combine_u8x32(self.clamp_u8x32(a0, b0, c0), self.clamp_u8x32(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_mask8x32(self.simd_eq_u8x32(a0, b0), self.simd_eq_u8x32(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> {
        self.not_mask8x64(self.simd_eq_u8x64(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_mask8x32(self.simd_lt_u8x32(a0, b0), self.simd_lt_u8x32(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_mask8x32(self.simd_le_u8x32(a0, b0), self.simd_le_u8x32(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> {
        self.simd_le_u8x64(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> mask8x64<Self> {
        self.simd_lt_u8x64(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, _) = self.split_u8x64(a);
        let (b0, _) = self.split_u8x64(b);
        self.combine_u8x32(self.zip_low_u8x32(a0, b0), self.zip_high_u8x32(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (_, a1) = self.split_u8x64(a);
        let (_, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.zip_low_u8x32(a1, b1), self.zip_high_u8x32(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.unzip_low_u8x32(a0, a1), self.unzip_low_u8x32(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u8x32(self.unzip_high_u8x32(a0, a1), self.unzip_high_u8x32(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> (u8x64<Self>, u8x64<Self>) {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        let lo_lo = self.zip_low_u8x32(a0, b0);
        let lo_hi = self.zip_high_u8x32(a0, b0);
        let hi_lo = self.zip_low_u8x32(a1, b1);
        let hi_hi = self.zip_high_u8x32(a1, b1);
        (
            self.combine_u8x32(lo_lo, lo_hi),
            self.combine_u8x32(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> (u8x64<Self>, u8x64<Self>) {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        let lo_even = self.unzip_low_u8x32(a0, a1);
        let lo_odd = self.unzip_high_u8x32(a0, a1);
        let hi_even = self.unzip_low_u8x32(b0, b1);
        let hi_odd = self.unzip_high_u8x32(b0, b1);
        (
            self.combine_u8x32(lo_even, hi_even),
            self.combine_u8x32(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u8x64(self, a: mask8x64<Self>, b: u8x64<Self>, c: u8x64<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        let (c0, c1) = self.split_u8x64(c);
        self.combine_u8x32(self.select_u8x32(a0, b0, c0), self.select_u8x32(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u8x64(self, a: u8x64<Self>) -> (u8x32<Self>, u8x32<Self>);
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_u8x64(self, a: u8x64<Self>) -> (u16x32<Self>, u16x32<Self>) {
        let (a0, a1) = self.split_u8x64(a);
        let (a00, a01) = self.widen_u8x32(a0);
        let (a10, a11) = self.widen_u8x32(a1);
        (self.combine_u16x16(a00, a01), self.combine_u16x16(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> (u16x32<Self>, u16x32<Self>) {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        let (low0, low1) = self.widening_mul_u8x32(a0, b0);
        let (high0, high1) = self.widening_mul_u8x32(a1, b1);
        (
            self.combine_u16x16(low0, low1),
            self.combine_u16x16(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> (u16x32<Self>, u16x32<Self>) {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        let (low0, low1) = self.widening_add_u8x32(a0, b0);
        let (high0, high1) = self.widening_add_u8x32(a1, b1);
        (
            self.combine_u16x16(low0, low1),
            self.combine_u16x16(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_u8x64(self, a: u8x64<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u8x64(a);
        self.combine_u16x16(
            self.pairwise_widening_add_u8x32(a0),
            self.pairwise_widening_add_u8x32(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_u8x64(self, a: u8x64<Self>, b: u8x64<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u8x64(a);
        let (b0, b1) = self.split_u8x64(b);
        self.combine_u16x16(
            self.pairwise_dot_product_u8x32(a0, b0),
            self.pairwise_dot_product_u8x32(a1, b1),
        )
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask8x64(self, val: bool) -> mask8x64<Self> {
        let half = self.splat_mask8x32(val);
        self.combine_mask8x32(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask8x64(self, bits: u64) -> mask8x64<Self> {
        let lo = self.from_bitmask_mask8x32(bits);
        let hi = self.from_bitmask_mask8x32(bits >> 32usize);
        self.combine_mask8x32(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask8x64(self, a: mask8x64<Self>) -> u64 {
        let (lo, hi) = self.split_mask8x64(a);
        let lo = self.to_bitmask_mask8x32(lo);
        let hi = self.to_bitmask_mask8x32(hi);
        lo | (hi << 32usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask8x64(self, vector: i8x64<Self>) -> mask8x64<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask8x64(self, a: mask8x64<Self>) -> i8x64<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask8x64(self, a: &mut mask8x64<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask8x64<const OFFSET: usize>(
        self,
        a: mask8x64<Self>,
    ) -> mask8x64<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask8x64<const OFFSET: usize>(
        self,
        a: mask8x64<Self>,
    ) -> mask8x64<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_mask8x64(b);
        self.combine_mask8x32(self.and_mask8x32(a0, b0), self.and_mask8x32(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_mask8x64(b);
        self.combine_mask8x32(self.or_mask8x32(a0, b0), self.or_mask8x32(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_mask8x64(b);
        self.combine_mask8x32(self.xor_mask8x32(a0, b0), self.xor_mask8x32(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        self.combine_mask8x32(self.not_mask8x32(a0), self.not_mask8x32(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask8x64(self, a: mask8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        self.combine_mask8x32(self.reverse_mask8x32(a1), self.reverse_mask8x32(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask8x64(
        self,
        a: mask8x64<Self>,
        b: mask8x64<Self>,
        c: mask8x64<Self>,
    ) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_mask8x64(b);
        let (c0, c1) = self.split_mask8x64(c);
        self.combine_mask8x32(
            self.select_mask8x32(a0, b0, c0),
            self.select_mask8x32(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask8x64(a);
        let (b0, b1) = self.split_mask8x64(b);
        self.combine_mask8x32(self.simd_eq_mask8x32(a0, b0), self.simd_eq_mask8x32(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask8x64(self, a: mask8x64<Self>, b: mask8x64<Self>) -> mask8x64<Self> {
        self.not_mask8x64(self.simd_eq_mask8x64(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask8x64(self, a: mask8x64<Self>) -> bool {
        let (a0, a1) = self.split_mask8x64(a);
        self.any_true_mask8x32(self.or_mask8x32(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask8x64(self, a: mask8x64<Self>) -> bool {
        let (a0, a1) = self.split_mask8x64(a);
        self.all_true_mask8x32(self.and_mask8x32(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask8x64(self, a: mask8x64<Self>) -> bool {
        let (a0, a1) = self.split_mask8x64(a);
        self.any_false_mask8x32(self.and_mask8x32(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask8x64(self, a: mask8x64<Self>) -> bool {
        let (a0, a1) = self.split_mask8x64(a);
        self.all_false_mask8x32(self.or_mask8x32(a0, a1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask8x64(self, a: mask8x64<Self>) -> (mask8x32<Self>, mask8x32<Self>);
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn widen_mask8x64(self, a: mask8x64<Self>) -> (mask16x32<Self>, mask16x32<Self>) {
        let (a0, a1) = self.split_mask8x64(a);
        let (a00, a01) = self.widen_mask8x32(a0);
        let (a10, a11) = self.widen_mask8x32(a1);
        (
            self.combine_mask16x16(a00, a01),
            self.combine_mask16x16(a10, a11),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i16x32(self, a: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.abs_i16x16(a0), self.abs_i16x16(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i16x32(self, val: i16) -> i16x32<Self> {
        let half = self.splat_i16x16(val);
        self.combine_i16x16(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i16x32(self, a: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.reverse_i16x16(a1), self.reverse_i16x16(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i16x32<const SHIFT: usize>(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i16x32<const SHIFT: usize>(
        self,
        a: i16x32<Self>,
        b: i16x32<Self>,
    ) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(
            self.slide_within_blocks_i16x16::<SHIFT>(a0, b0),
            self.slide_within_blocks_i16x16::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i16x32(
        self,
        a: i16x32<Self>,
        indices: u8x64<Self>,
    ) -> i16x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i16x32(self, a: i16x32<Self>, indices: u8x64<Self>) -> i16x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i16x32(self, a: i16x32<Self>, indices: u8x64<Self>) -> i16x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i16x32(
        self,
        a: i16x32<Self>,
        b: i16x32<Self>,
        indices: u8x64<Self>,
    ) -> i16x32<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i16x32(
        self,
        a: i16x32<Self>,
        b: i16x32<Self>,
        indices: u8x64<Self>,
    ) -> i16x32<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i16x32(self, values: i16x32<Self>, mask: mask16x32<Self>) -> i16x32<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i16x32(
        self,
        values: i16x32<Self>,
        mask: mask16x32<Self>,
        merge: i16x32<Self>,
    ) -> i16x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i16x32(self, values: i16x32<Self>, mask: mask16x32<Self>) -> i16x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i16x32(
        self,
        values: i16x32<Self>,
        mask: mask16x32<Self>,
        merge: i16x32<Self>,
    ) -> i16x32<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i16x32(self, a: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.count_ones_i16x16(a0), self.count_ones_i16x16(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i16x32(self, a: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.count_zeros_i16x16(a0), self.count_zeros_i16x16(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.add_i16x16(a0, b0), self.add_i16x16(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(
            self.saturating_add_i16x16(a0, b0),
            self.saturating_add_i16x16(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.sub_i16x16(a0, b0), self.sub_i16x16(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(
            self.saturating_sub_i16x16(a0, b0),
            self.saturating_sub_i16x16(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.mul_i16x16(a0, b0), self.mul_i16x16(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.and_i16x16(a0, b0), self.and_i16x16(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.or_i16x16(a0, b0), self.or_i16x16(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.xor_i16x16(a0, b0), self.xor_i16x16(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i16x32(self, a: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.not_i16x16(a0), self.not_i16x16(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.shl_i16x16(a0, shift), self.shl_i16x16(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.shlv_i16x16(a0, b0), self.shlv_i16x16(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i16x32(self, a: i16x32<Self>, shift: u32) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.shr_i16x16(a0, shift), self.shr_i16x16(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.shrv_i16x16(a0, b0), self.shrv_i16x16(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i16x32(self, a: i16x32<Self>) -> i16 {
        let (a0, a1) = self.split_i16x32(a);
        self.reduce_max_i16x16(self.max_i16x16(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i16x32(self, a: i16x32<Self>) -> i16 {
        let (a0, a1) = self.split_i16x32(a);
        self.reduce_min_i16x16(self.min_i16x16(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i16x32(self, a: i16x32<Self>) -> i16 {
        let (a0, a1) = self.split_i16x32(a);
        self.reduce_sum_i16x16(self.add_i16x16(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i16x32(self, a: i16x32<Self>) -> i16 {
        let (a0, a1) = self.split_i16x32(a);
        self.reduce_product_i16x16(self.mul_i16x16(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.max_i16x16(a0, b0), self.max_i16x16(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.min_i16x16(a0, b0), self.min_i16x16(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i16x32(self, a: i16x32<Self>, b: i16x32<Self>, c: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        let (c0, c1) = self.split_i16x32(c);
        self.combine_i16x16(self.clamp_i16x16(a0, b0, c0), self.clamp_i16x16(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_mask16x16(self.simd_eq_i16x16(a0, b0), self.simd_eq_i16x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> {
        self.not_mask16x32(self.simd_eq_i16x32(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_mask16x16(self.simd_lt_i16x16(a0, b0), self.simd_lt_i16x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_mask16x16(self.simd_le_i16x16(a0, b0), self.simd_le_i16x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> {
        self.simd_le_i16x32(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> mask16x32<Self> {
        self.simd_lt_i16x32(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, _) = self.split_i16x32(a);
        let (b0, _) = self.split_i16x32(b);
        self.combine_i16x16(self.zip_low_i16x16(a0, b0), self.zip_high_i16x16(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (_, a1) = self.split_i16x32(a);
        let (_, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.zip_low_i16x16(a1, b1), self.zip_high_i16x16(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(self.unzip_low_i16x16(a0, a1), self.unzip_low_i16x16(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i16x16(
            self.unzip_high_i16x16(a0, a1),
            self.unzip_high_i16x16(b0, b1),
        )
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> (i16x32<Self>, i16x32<Self>) {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        let lo_lo = self.zip_low_i16x16(a0, b0);
        let lo_hi = self.zip_high_i16x16(a0, b0);
        let hi_lo = self.zip_low_i16x16(a1, b1);
        let hi_hi = self.zip_high_i16x16(a1, b1);
        (
            self.combine_i16x16(lo_lo, lo_hi),
            self.combine_i16x16(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> (i16x32<Self>, i16x32<Self>) {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        let lo_even = self.unzip_low_i16x16(a0, a1);
        let lo_odd = self.unzip_high_i16x16(a0, a1);
        let hi_even = self.unzip_low_i16x16(b0, b1);
        let hi_odd = self.unzip_high_i16x16(b0, b1);
        (
            self.combine_i16x16(lo_even, hi_even),
            self.combine_i16x16(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i16x32(self, a: mask16x32<Self>, b: i16x32<Self>, c: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        let (c0, c1) = self.split_i16x32(c);
        self.combine_i16x16(
            self.select_i16x16(a0, b0, c0),
            self.select_i16x16(a1, b1, c1),
        )
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i16x32(self, a: i16x32<Self>) -> (i16x16<Self>, i16x16<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i16x32(self, a: i16x32<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i16x16(self.neg_i16x16(a0), self.neg_i16x16(a1))
    }
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_i16x32(self, a: i16x32<Self>) -> (i32x16<Self>, i32x16<Self>) {
        let (a0, a1) = self.split_i16x32(a);
        let (a00, a01) = self.widen_i16x16(a0);
        let (a10, a11) = self.widen_i16x16(a1);
        (self.combine_i32x8(a00, a01), self.combine_i32x8(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> (i32x16<Self>, i32x16<Self>) {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        let (low0, low1) = self.widening_mul_i16x16(a0, b0);
        let (high0, high1) = self.widening_mul_i16x16(a1, b1);
        (
            self.combine_i32x8(low0, low1),
            self.combine_i32x8(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> (i32x16<Self>, i32x16<Self>) {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        let (low0, low1) = self.widening_add_i16x16(a0, b0);
        let (high0, high1) = self.widening_add_i16x16(a1, b1);
        (
            self.combine_i32x8(low0, low1),
            self.combine_i32x8(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_i16x32(self, a: i16x32<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i16x32(a);
        self.combine_i32x8(
            self.pairwise_widening_add_i16x16(a0),
            self.pairwise_widening_add_i16x16(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i32x8(
            self.pairwise_dot_product_i16x16(a0, b0),
            self.pairwise_dot_product_i16x16(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i8x32(self.narrow_i16x16(a0, a1), self.narrow_i16x16(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i8x32(
            self.saturating_narrow_i16x16(a0, a1),
            self.saturating_narrow_i16x16(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_i16x32(self, a: i16x32<Self>, b: i16x32<Self>) -> i8x64<Self> {
        let (a0, a1) = self.split_i16x32(a);
        let (b0, b1) = self.split_i16x32(b);
        self.combine_i8x32(
            self.relaxed_narrow_i16x16(a0, a1),
            self.relaxed_narrow_i16x16(b0, b1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u16x32(self, a: u16x32<Self>) -> u16x32<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u16x32(self, val: u16) -> u16x32<Self> {
        let half = self.splat_u16x16(val);
        self.combine_u16x16(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u16x32(self, a: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u16x16(self.reverse_u16x16(a1), self.reverse_u16x16(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u16x32<const SHIFT: usize>(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u16x32<const SHIFT: usize>(
        self,
        a: u16x32<Self>,
        b: u16x32<Self>,
    ) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(
            self.slide_within_blocks_u16x16::<SHIFT>(a0, b0),
            self.slide_within_blocks_u16x16::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u16x32(
        self,
        a: u16x32<Self>,
        indices: u8x64<Self>,
    ) -> u16x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u16x32(self, a: u16x32<Self>, indices: u8x64<Self>) -> u16x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u16x32(self, a: u16x32<Self>, indices: u8x64<Self>) -> u16x32<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u16x32(
        self,
        a: u16x32<Self>,
        b: u16x32<Self>,
        indices: u8x64<Self>,
    ) -> u16x32<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u16x32(
        self,
        a: u16x32<Self>,
        b: u16x32<Self>,
        indices: u8x64<Self>,
    ) -> u16x32<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u16x32(self, values: u16x32<Self>, mask: mask16x32<Self>) -> u16x32<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u16x32(
        self,
        values: u16x32<Self>,
        mask: mask16x32<Self>,
        merge: u16x32<Self>,
    ) -> u16x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u16x32(self, values: u16x32<Self>, mask: mask16x32<Self>) -> u16x32<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u16x32(
        self,
        values: u16x32<Self>,
        mask: mask16x32<Self>,
        merge: u16x32<Self>,
    ) -> u16x32<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u16x32(self, a: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u16x16(self.count_ones_u16x16(a0), self.count_ones_u16x16(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u16x32(self, a: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u16x16(self.count_zeros_u16x16(a0), self.count_zeros_u16x16(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.add_u16x16(a0, b0), self.add_u16x16(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(
            self.saturating_add_u16x16(a0, b0),
            self.saturating_add_u16x16(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.sub_u16x16(a0, b0), self.sub_u16x16(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(
            self.saturating_sub_u16x16(a0, b0),
            self.saturating_sub_u16x16(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.mul_u16x16(a0, b0), self.mul_u16x16(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.and_u16x16(a0, b0), self.and_u16x16(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.or_u16x16(a0, b0), self.or_u16x16(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.xor_u16x16(a0, b0), self.xor_u16x16(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u16x32(self, a: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u16x16(self.not_u16x16(a0), self.not_u16x16(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u16x16(self.shl_u16x16(a0, shift), self.shl_u16x16(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.shlv_u16x16(a0, b0), self.shlv_u16x16(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u16x32(self, a: u16x32<Self>, shift: u32) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u16x16(self.shr_u16x16(a0, shift), self.shr_u16x16(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.shrv_u16x16(a0, b0), self.shrv_u16x16(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u16x32(self, a: u16x32<Self>) -> u16 {
        let (a0, a1) = self.split_u16x32(a);
        self.reduce_max_u16x16(self.max_u16x16(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u16x32(self, a: u16x32<Self>) -> u16 {
        let (a0, a1) = self.split_u16x32(a);
        self.reduce_min_u16x16(self.min_u16x16(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u16x32(self, a: u16x32<Self>) -> u16 {
        let (a0, a1) = self.split_u16x32(a);
        self.reduce_sum_u16x16(self.add_u16x16(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u16x32(self, a: u16x32<Self>) -> u16 {
        let (a0, a1) = self.split_u16x32(a);
        self.reduce_product_u16x16(self.mul_u16x16(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.max_u16x16(a0, b0), self.max_u16x16(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.min_u16x16(a0, b0), self.min_u16x16(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u16x32(self, a: u16x32<Self>, b: u16x32<Self>, c: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        let (c0, c1) = self.split_u16x32(c);
        self.combine_u16x16(self.clamp_u16x16(a0, b0, c0), self.clamp_u16x16(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_mask16x16(self.simd_eq_u16x16(a0, b0), self.simd_eq_u16x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> {
        self.not_mask16x32(self.simd_eq_u16x32(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_mask16x16(self.simd_lt_u16x16(a0, b0), self.simd_lt_u16x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_mask16x16(self.simd_le_u16x16(a0, b0), self.simd_le_u16x16(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> {
        self.simd_le_u16x32(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> mask16x32<Self> {
        self.simd_lt_u16x32(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, _) = self.split_u16x32(a);
        let (b0, _) = self.split_u16x32(b);
        self.combine_u16x16(self.zip_low_u16x16(a0, b0), self.zip_high_u16x16(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (_, a1) = self.split_u16x32(a);
        let (_, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.zip_low_u16x16(a1, b1), self.zip_high_u16x16(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(self.unzip_low_u16x16(a0, a1), self.unzip_low_u16x16(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u16x16(
            self.unzip_high_u16x16(a0, a1),
            self.unzip_high_u16x16(b0, b1),
        )
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> (u16x32<Self>, u16x32<Self>) {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        let lo_lo = self.zip_low_u16x16(a0, b0);
        let lo_hi = self.zip_high_u16x16(a0, b0);
        let hi_lo = self.zip_low_u16x16(a1, b1);
        let hi_hi = self.zip_high_u16x16(a1, b1);
        (
            self.combine_u16x16(lo_lo, lo_hi),
            self.combine_u16x16(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> (u16x32<Self>, u16x32<Self>) {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        let lo_even = self.unzip_low_u16x16(a0, a1);
        let lo_odd = self.unzip_high_u16x16(a0, a1);
        let hi_even = self.unzip_low_u16x16(b0, b1);
        let hi_odd = self.unzip_high_u16x16(b0, b1);
        (
            self.combine_u16x16(lo_even, hi_even),
            self.combine_u16x16(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u16x32(self, a: mask16x32<Self>, b: u16x32<Self>, c: u16x32<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        let (c0, c1) = self.split_u16x32(c);
        self.combine_u16x16(
            self.select_u16x16(a0, b0, c0),
            self.select_u16x16(a1, b1, c1),
        )
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u16x32(self, a: u16x32<Self>) -> (u16x16<Self>, u16x16<Self>);
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_u16x32(self, a: u16x32<Self>) -> (u32x16<Self>, u32x16<Self>) {
        let (a0, a1) = self.split_u16x32(a);
        let (a00, a01) = self.widen_u16x16(a0);
        let (a10, a11) = self.widen_u16x16(a1);
        (self.combine_u32x8(a00, a01), self.combine_u32x8(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> (u32x16<Self>, u32x16<Self>) {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        let (low0, low1) = self.widening_mul_u16x16(a0, b0);
        let (high0, high1) = self.widening_mul_u16x16(a1, b1);
        (
            self.combine_u32x8(low0, low1),
            self.combine_u32x8(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> (u32x16<Self>, u32x16<Self>) {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        let (low0, low1) = self.widening_add_u16x16(a0, b0);
        let (high0, high1) = self.widening_add_u16x16(a1, b1);
        (
            self.combine_u32x8(low0, low1),
            self.combine_u32x8(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_u16x32(self, a: u16x32<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u16x32(a);
        self.combine_u32x8(
            self.pairwise_widening_add_u16x16(a0),
            self.pairwise_widening_add_u16x16(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u32x8(
            self.pairwise_dot_product_u16x16(a0, b0),
            self.pairwise_dot_product_u16x16(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u8x32(self.narrow_u16x16(a0, a1), self.narrow_u16x16(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u8x32(
            self.saturating_narrow_u16x16(a0, a1),
            self.saturating_narrow_u16x16(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_u16x32(self, a: u16x32<Self>, b: u16x32<Self>) -> u8x64<Self> {
        let (a0, a1) = self.split_u16x32(a);
        let (b0, b1) = self.split_u16x32(b);
        self.combine_u8x32(
            self.relaxed_narrow_u16x16(a0, a1),
            self.relaxed_narrow_u16x16(b0, b1),
        )
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask16x32(self, val: bool) -> mask16x32<Self> {
        let half = self.splat_mask16x16(val);
        self.combine_mask16x16(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask16x32(self, bits: u64) -> mask16x32<Self> {
        let lo = self.from_bitmask_mask16x16(bits);
        let hi = self.from_bitmask_mask16x16(bits >> 16usize);
        self.combine_mask16x16(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask16x32(self, a: mask16x32<Self>) -> u64 {
        let (lo, hi) = self.split_mask16x32(a);
        let lo = self.to_bitmask_mask16x16(lo);
        let hi = self.to_bitmask_mask16x16(hi);
        lo | (hi << 16usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask16x32(self, vector: i16x32<Self>) -> mask16x32<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask16x32(self, a: mask16x32<Self>) -> i16x32<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask16x32(self, a: &mut mask16x32<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask16x32<const OFFSET: usize>(
        self,
        a: mask16x32<Self>,
    ) -> mask16x32<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask16x32<const OFFSET: usize>(
        self,
        a: mask16x32<Self>,
    ) -> mask16x32<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_mask16x32(b);
        self.combine_mask16x16(self.and_mask16x16(a0, b0), self.and_mask16x16(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_mask16x32(b);
        self.combine_mask16x16(self.or_mask16x16(a0, b0), self.or_mask16x16(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_mask16x32(b);
        self.combine_mask16x16(self.xor_mask16x16(a0, b0), self.xor_mask16x16(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        self.combine_mask16x16(self.not_mask16x16(a0), self.not_mask16x16(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask16x32(self, a: mask16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        self.combine_mask16x16(self.reverse_mask16x16(a1), self.reverse_mask16x16(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask16x32(
        self,
        a: mask16x32<Self>,
        b: mask16x32<Self>,
        c: mask16x32<Self>,
    ) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_mask16x32(b);
        let (c0, c1) = self.split_mask16x32(c);
        self.combine_mask16x16(
            self.select_mask16x16(a0, b0, c0),
            self.select_mask16x16(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_mask16x32(b);
        self.combine_mask16x16(
            self.simd_eq_mask16x16(a0, b0),
            self.simd_eq_mask16x16(a1, b1),
        )
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask16x32<Self> {
        self.not_mask16x32(self.simd_eq_mask16x32(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask16x32(self, a: mask16x32<Self>) -> bool {
        let (a0, a1) = self.split_mask16x32(a);
        self.any_true_mask16x16(self.or_mask16x16(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask16x32(self, a: mask16x32<Self>) -> bool {
        let (a0, a1) = self.split_mask16x32(a);
        self.all_true_mask16x16(self.and_mask16x16(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask16x32(self, a: mask16x32<Self>) -> bool {
        let (a0, a1) = self.split_mask16x32(a);
        self.any_false_mask16x16(self.and_mask16x16(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask16x32(self, a: mask16x32<Self>) -> bool {
        let (a0, a1) = self.split_mask16x32(a);
        self.all_false_mask16x16(self.or_mask16x16(a0, a1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask16x32(self, a: mask16x32<Self>) -> (mask16x16<Self>, mask16x16<Self>);
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn widen_mask16x32(self, a: mask16x32<Self>) -> (mask32x16<Self>, mask32x16<Self>) {
        let (a0, a1) = self.split_mask16x32(a);
        let (a00, a01) = self.widen_mask16x16(a0);
        let (a10, a11) = self.widen_mask16x16(a1);
        (
            self.combine_mask32x8(a00, a01),
            self.combine_mask32x8(a10, a11),
        )
    }
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn narrow_mask16x32(self, a: mask16x32<Self>, b: mask16x32<Self>) -> mask8x64<Self> {
        let (a0, a1) = self.split_mask16x32(a);
        let (b0, b1) = self.split_mask16x32(b);
        self.combine_mask8x32(self.narrow_mask16x16(a0, a1), self.narrow_mask16x16(b0, b1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i32x16(self, a: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.abs_i32x8(a0), self.abs_i32x8(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i32x16(self, val: i32) -> i32x16<Self> {
        let half = self.splat_i32x8(val);
        self.combine_i32x8(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i32x16(self, a: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.reverse_i32x8(a1), self.reverse_i32x8(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i32x16<const SHIFT: usize>(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i32x16<const SHIFT: usize>(
        self,
        a: i32x16<Self>,
        b: i32x16<Self>,
    ) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(
            self.slide_within_blocks_i32x8::<SHIFT>(a0, b0),
            self.slide_within_blocks_i32x8::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i32x16(
        self,
        a: i32x16<Self>,
        indices: u8x64<Self>,
    ) -> i32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i32x16(self, a: i32x16<Self>, indices: u8x64<Self>) -> i32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i32x16(self, a: i32x16<Self>, indices: u8x64<Self>) -> i32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i32x16(
        self,
        a: i32x16<Self>,
        b: i32x16<Self>,
        indices: u8x64<Self>,
    ) -> i32x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i32x16(
        self,
        a: i32x16<Self>,
        b: i32x16<Self>,
        indices: u8x64<Self>,
    ) -> i32x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i32x16(self, values: i32x16<Self>, mask: mask32x16<Self>) -> i32x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i32x16(
        self,
        values: i32x16<Self>,
        mask: mask32x16<Self>,
        merge: i32x16<Self>,
    ) -> i32x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i32x16(self, values: i32x16<Self>, mask: mask32x16<Self>) -> i32x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i32x16(
        self,
        values: i32x16<Self>,
        mask: mask32x16<Self>,
        merge: i32x16<Self>,
    ) -> i32x16<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i32x16(self, a: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.count_ones_i32x8(a0), self.count_ones_i32x8(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i32x16(self, a: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.count_zeros_i32x8(a0), self.count_zeros_i32x8(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.add_i32x8(a0, b0), self.add_i32x8(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(
            self.saturating_add_i32x8(a0, b0),
            self.saturating_add_i32x8(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.sub_i32x8(a0, b0), self.sub_i32x8(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(
            self.saturating_sub_i32x8(a0, b0),
            self.saturating_sub_i32x8(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.mul_i32x8(a0, b0), self.mul_i32x8(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.and_i32x8(a0, b0), self.and_i32x8(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.or_i32x8(a0, b0), self.or_i32x8(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.xor_i32x8(a0, b0), self.xor_i32x8(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i32x16(self, a: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.not_i32x8(a0), self.not_i32x8(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.shl_i32x8(a0, shift), self.shl_i32x8(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.shlv_i32x8(a0, b0), self.shlv_i32x8(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i32x16(self, a: i32x16<Self>, shift: u32) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.shr_i32x8(a0, shift), self.shr_i32x8(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.shrv_i32x8(a0, b0), self.shrv_i32x8(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i32x16(self, a: i32x16<Self>) -> i32 {
        let (a0, a1) = self.split_i32x16(a);
        self.reduce_max_i32x8(self.max_i32x8(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i32x16(self, a: i32x16<Self>) -> i32 {
        let (a0, a1) = self.split_i32x16(a);
        self.reduce_min_i32x8(self.min_i32x8(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i32x16(self, a: i32x16<Self>) -> i32 {
        let (a0, a1) = self.split_i32x16(a);
        self.reduce_sum_i32x8(self.add_i32x8(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i32x16(self, a: i32x16<Self>) -> i32 {
        let (a0, a1) = self.split_i32x16(a);
        self.reduce_product_i32x8(self.mul_i32x8(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.max_i32x8(a0, b0), self.max_i32x8(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.min_i32x8(a0, b0), self.min_i32x8(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i32x16(self, a: i32x16<Self>, b: i32x16<Self>, c: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        let (c0, c1) = self.split_i32x16(c);
        self.combine_i32x8(self.clamp_i32x8(a0, b0, c0), self.clamp_i32x8(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_mask32x8(self.simd_eq_i32x8(a0, b0), self.simd_eq_i32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> {
        self.not_mask32x16(self.simd_eq_i32x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_mask32x8(self.simd_lt_i32x8(a0, b0), self.simd_lt_i32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_mask32x8(self.simd_le_i32x8(a0, b0), self.simd_le_i32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> {
        self.simd_le_i32x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> mask32x16<Self> {
        self.simd_lt_i32x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, _) = self.split_i32x16(a);
        let (b0, _) = self.split_i32x16(b);
        self.combine_i32x8(self.zip_low_i32x8(a0, b0), self.zip_high_i32x8(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (_, a1) = self.split_i32x16(a);
        let (_, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.zip_low_i32x8(a1, b1), self.zip_high_i32x8(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.unzip_low_i32x8(a0, a1), self.unzip_low_i32x8(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i32x8(self.unzip_high_i32x8(a0, a1), self.unzip_high_i32x8(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> (i32x16<Self>, i32x16<Self>) {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        let lo_lo = self.zip_low_i32x8(a0, b0);
        let lo_hi = self.zip_high_i32x8(a0, b0);
        let hi_lo = self.zip_low_i32x8(a1, b1);
        let hi_hi = self.zip_high_i32x8(a1, b1);
        (
            self.combine_i32x8(lo_lo, lo_hi),
            self.combine_i32x8(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> (i32x16<Self>, i32x16<Self>) {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        let lo_even = self.unzip_low_i32x8(a0, a1);
        let lo_odd = self.unzip_high_i32x8(a0, a1);
        let hi_even = self.unzip_low_i32x8(b0, b1);
        let hi_odd = self.unzip_high_i32x8(b0, b1);
        (
            self.combine_i32x8(lo_even, hi_even),
            self.combine_i32x8(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i32x16(self, a: mask32x16<Self>, b: i32x16<Self>, c: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        let (c0, c1) = self.split_i32x16(c);
        self.combine_i32x8(self.select_i32x8(a0, b0, c0), self.select_i32x8(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i32x16(self, a: i32x16<Self>) -> (i32x8<Self>, i32x8<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i32x16(self, a: i32x16<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i32x8(self.neg_i32x8(a0), self.neg_i32x8(a1))
    }
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_i32x16(self, a: i32x16<Self>) -> (i64x8<Self>, i64x8<Self>) {
        let (a0, a1) = self.split_i32x16(a);
        let (a00, a01) = self.widen_i32x8(a0);
        let (a10, a11) = self.widen_i32x8(a1);
        (self.combine_i64x4(a00, a01), self.combine_i64x4(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> (i64x8<Self>, i64x8<Self>) {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        let (low0, low1) = self.widening_mul_i32x8(a0, b0);
        let (high0, high1) = self.widening_mul_i32x8(a1, b1);
        (
            self.combine_i64x4(low0, low1),
            self.combine_i64x4(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> (i64x8<Self>, i64x8<Self>) {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        let (low0, low1) = self.widening_add_i32x8(a0, b0);
        let (high0, high1) = self.widening_add_i32x8(a1, b1);
        (
            self.combine_i64x4(low0, low1),
            self.combine_i64x4(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_i32x16(self, a: i32x16<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_i64x4(
            self.pairwise_widening_add_i32x8(a0),
            self.pairwise_widening_add_i32x8(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i64x4(
            self.pairwise_dot_product_i32x8(a0, b0),
            self.pairwise_dot_product_i32x8(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i16x16(self.narrow_i32x8(a0, a1), self.narrow_i32x8(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i16x16(
            self.saturating_narrow_i32x8(a0, a1),
            self.saturating_narrow_i32x8(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_i32x16(self, a: i32x16<Self>, b: i32x16<Self>) -> i16x32<Self> {
        let (a0, a1) = self.split_i32x16(a);
        let (b0, b1) = self.split_i32x16(b);
        self.combine_i16x16(
            self.relaxed_narrow_i32x8(a0, a1),
            self.relaxed_narrow_i32x8(b0, b1),
        )
    }
    #[doc = "Convert each signed 32-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f32_i32x16(self, a: i32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_i32x16(a);
        self.combine_f32x8(self.cvt_f32_i32x8(a0), self.cvt_f32_i32x8(a1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u32x16(self, a: u32x16<Self>) -> u32x16<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u32x16(self, val: u32) -> u32x16<Self> {
        let half = self.splat_u32x8(val);
        self.combine_u32x8(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u32x16(self, a: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u32x8(self.reverse_u32x8(a1), self.reverse_u32x8(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u32x16<const SHIFT: usize>(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u32x16<const SHIFT: usize>(
        self,
        a: u32x16<Self>,
        b: u32x16<Self>,
    ) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(
            self.slide_within_blocks_u32x8::<SHIFT>(a0, b0),
            self.slide_within_blocks_u32x8::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u32x16(
        self,
        a: u32x16<Self>,
        indices: u8x64<Self>,
    ) -> u32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u32x16(self, a: u32x16<Self>, indices: u8x64<Self>) -> u32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u32x16(self, a: u32x16<Self>, indices: u8x64<Self>) -> u32x16<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u32x16(
        self,
        a: u32x16<Self>,
        b: u32x16<Self>,
        indices: u8x64<Self>,
    ) -> u32x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u32x16(
        self,
        a: u32x16<Self>,
        b: u32x16<Self>,
        indices: u8x64<Self>,
    ) -> u32x16<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u32x16(self, values: u32x16<Self>, mask: mask32x16<Self>) -> u32x16<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u32x16(
        self,
        values: u32x16<Self>,
        mask: mask32x16<Self>,
        merge: u32x16<Self>,
    ) -> u32x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u32x16(self, values: u32x16<Self>, mask: mask32x16<Self>) -> u32x16<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u32x16(
        self,
        values: u32x16<Self>,
        mask: mask32x16<Self>,
        merge: u32x16<Self>,
    ) -> u32x16<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u32x16(self, a: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u32x8(self.count_ones_u32x8(a0), self.count_ones_u32x8(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u32x16(self, a: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u32x8(self.count_zeros_u32x8(a0), self.count_zeros_u32x8(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.add_u32x8(a0, b0), self.add_u32x8(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(
            self.saturating_add_u32x8(a0, b0),
            self.saturating_add_u32x8(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.sub_u32x8(a0, b0), self.sub_u32x8(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(
            self.saturating_sub_u32x8(a0, b0),
            self.saturating_sub_u32x8(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.mul_u32x8(a0, b0), self.mul_u32x8(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.and_u32x8(a0, b0), self.and_u32x8(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.or_u32x8(a0, b0), self.or_u32x8(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.xor_u32x8(a0, b0), self.xor_u32x8(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u32x16(self, a: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u32x8(self.not_u32x8(a0), self.not_u32x8(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u32x8(self.shl_u32x8(a0, shift), self.shl_u32x8(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.shlv_u32x8(a0, b0), self.shlv_u32x8(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u32x16(self, a: u32x16<Self>, shift: u32) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u32x8(self.shr_u32x8(a0, shift), self.shr_u32x8(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.shrv_u32x8(a0, b0), self.shrv_u32x8(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u32x16(self, a: u32x16<Self>) -> u32 {
        let (a0, a1) = self.split_u32x16(a);
        self.reduce_max_u32x8(self.max_u32x8(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u32x16(self, a: u32x16<Self>) -> u32 {
        let (a0, a1) = self.split_u32x16(a);
        self.reduce_min_u32x8(self.min_u32x8(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u32x16(self, a: u32x16<Self>) -> u32 {
        let (a0, a1) = self.split_u32x16(a);
        self.reduce_sum_u32x8(self.add_u32x8(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u32x16(self, a: u32x16<Self>) -> u32 {
        let (a0, a1) = self.split_u32x16(a);
        self.reduce_product_u32x8(self.mul_u32x8(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.max_u32x8(a0, b0), self.max_u32x8(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.min_u32x8(a0, b0), self.min_u32x8(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u32x16(self, a: u32x16<Self>, b: u32x16<Self>, c: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        let (c0, c1) = self.split_u32x16(c);
        self.combine_u32x8(self.clamp_u32x8(a0, b0, c0), self.clamp_u32x8(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_mask32x8(self.simd_eq_u32x8(a0, b0), self.simd_eq_u32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> {
        self.not_mask32x16(self.simd_eq_u32x16(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_mask32x8(self.simd_lt_u32x8(a0, b0), self.simd_lt_u32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_mask32x8(self.simd_le_u32x8(a0, b0), self.simd_le_u32x8(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> {
        self.simd_le_u32x16(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> mask32x16<Self> {
        self.simd_lt_u32x16(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, _) = self.split_u32x16(a);
        let (b0, _) = self.split_u32x16(b);
        self.combine_u32x8(self.zip_low_u32x8(a0, b0), self.zip_high_u32x8(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (_, a1) = self.split_u32x16(a);
        let (_, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.zip_low_u32x8(a1, b1), self.zip_high_u32x8(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.unzip_low_u32x8(a0, a1), self.unzip_low_u32x8(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u32x8(self.unzip_high_u32x8(a0, a1), self.unzip_high_u32x8(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> (u32x16<Self>, u32x16<Self>) {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        let lo_lo = self.zip_low_u32x8(a0, b0);
        let lo_hi = self.zip_high_u32x8(a0, b0);
        let hi_lo = self.zip_low_u32x8(a1, b1);
        let hi_hi = self.zip_high_u32x8(a1, b1);
        (
            self.combine_u32x8(lo_lo, lo_hi),
            self.combine_u32x8(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> (u32x16<Self>, u32x16<Self>) {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        let lo_even = self.unzip_low_u32x8(a0, a1);
        let lo_odd = self.unzip_high_u32x8(a0, a1);
        let hi_even = self.unzip_low_u32x8(b0, b1);
        let hi_odd = self.unzip_high_u32x8(b0, b1);
        (
            self.combine_u32x8(lo_even, hi_even),
            self.combine_u32x8(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u32x16(self, a: mask32x16<Self>, b: u32x16<Self>, c: u32x16<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        let (c0, c1) = self.split_u32x16(c);
        self.combine_u32x8(self.select_u32x8(a0, b0, c0), self.select_u32x8(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u32x16(self, a: u32x16<Self>) -> (u32x8<Self>, u32x8<Self>);
    #[doc = "Widen every lane into two same-width vectors.\n\nThe first result contains the widened lower lanes and the second contains the widened upper lanes."]
    #[inline(always)]
    fn widen_u32x16(self, a: u32x16<Self>) -> (u64x8<Self>, u64x8<Self>) {
        let (a0, a1) = self.split_u32x16(a);
        let (a00, a01) = self.widen_u32x8(a0);
        let (a10, a11) = self.widen_u32x8(a1);
        (self.combine_u64x4(a00, a01), self.combine_u64x4(a10, a11))
    }
    #[doc = "Multiply corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_mul_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> (u64x8<Self>, u64x8<Self>) {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        let (low0, low1) = self.widening_mul_u32x8(a0, b0);
        let (high0, high1) = self.widening_mul_u32x8(a1, b1);
        (
            self.combine_u64x4(low0, low1),
            self.combine_u64x4(high0, high1),
        )
    }
    #[doc = "Add corresponding integer lanes exactly into twice-wide lanes. The first result contains the lower lanes and the second contains the upper lanes."]
    #[inline(always)]
    fn widening_add_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> (u64x8<Self>, u64x8<Self>) {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        let (low0, low1) = self.widening_add_u32x8(a0, b0);
        let (high0, high1) = self.widening_add_u32x8(a1, b1);
        (
            self.combine_u64x4(low0, low1),
            self.combine_u64x4(high0, high1),
        )
    }
    #[doc = "Add adjacent integer lanes exactly into twice-wide lanes.\n\nOutput lane `i` is `widen(a[2*i]) + widen(a[2*i+1])`. The result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. The sum cannot overflow the widened type.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` produces `[3, 7, 11, 15]`. See [`SimdIntWiden::pairwise_widening_add`] for supported types and examples."]
    #[inline(always)]
    fn pairwise_widening_add_u32x16(self, a: u32x16<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_u64x4(
            self.pairwise_widening_add_u32x8(a0),
            self.pairwise_widening_add_u32x8(a1),
        )
    }
    #[doc = "Multiply corresponding integer lanes exactly in the widened type, then sum adjacent pairs of products.\n\nThe result has half as many lanes, twice the lane width, and unchanged signedness and total bit width. Lane `i` is `widen(a[2*i]) * widen(b[2*i]) + widen(a[2*i+1]) * widen(b[2*i+1])`; addition wraps in the destination type, including in debug builds.\n\nFor example, `[1, 2, 3, 4, 5, 6, 7, 8]` and `[10, 20, 30, 40, 50, 60, 70, 80]` produce `[50, 250, 610, 1130]`. See [`SimdIntWiden::pairwise_dot_product`] for examples."]
    #[inline(always)]
    fn pairwise_dot_product_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u64x4(
            self.pairwise_dot_product_u32x8(a0, b0),
            self.pairwise_dot_product_u32x8(a1, b1),
        )
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u16x16(self.narrow_u32x8(a0, a1), self.narrow_u32x8(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u16x16(
            self.saturating_narrow_u32x8(a0, a1),
            self.saturating_narrow_u32x8(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_u32x16(self, a: u32x16<Self>, b: u32x16<Self>) -> u16x32<Self> {
        let (a0, a1) = self.split_u32x16(a);
        let (b0, b1) = self.split_u32x16(b);
        self.combine_u16x16(
            self.relaxed_narrow_u32x8(a0, a1),
            self.relaxed_narrow_u32x8(b0, b1),
        )
    }
    #[doc = "Convert each unsigned 32-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f32_u32x16(self, a: u32x16<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_u32x16(a);
        self.combine_f32x8(self.cvt_f32_u32x8(a0), self.cvt_f32_u32x8(a1))
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask32x16(self, val: bool) -> mask32x16<Self> {
        let half = self.splat_mask32x8(val);
        self.combine_mask32x8(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask32x16(self, bits: u64) -> mask32x16<Self> {
        let lo = self.from_bitmask_mask32x8(bits);
        let hi = self.from_bitmask_mask32x8(bits >> 8usize);
        self.combine_mask32x8(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask32x16(self, a: mask32x16<Self>) -> u64 {
        let (lo, hi) = self.split_mask32x16(a);
        let lo = self.to_bitmask_mask32x8(lo);
        let hi = self.to_bitmask_mask32x8(hi);
        lo | (hi << 8usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask32x16(self, vector: i32x16<Self>) -> mask32x16<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask32x16(self, a: mask32x16<Self>) -> i32x16<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask32x16(self, a: &mut mask32x16<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask32x16<const OFFSET: usize>(
        self,
        a: mask32x16<Self>,
    ) -> mask32x16<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask32x16<const OFFSET: usize>(
        self,
        a: mask32x16<Self>,
    ) -> mask32x16<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_mask32x16(b);
        self.combine_mask32x8(self.and_mask32x8(a0, b0), self.and_mask32x8(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_mask32x16(b);
        self.combine_mask32x8(self.or_mask32x8(a0, b0), self.or_mask32x8(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_mask32x16(b);
        self.combine_mask32x8(self.xor_mask32x8(a0, b0), self.xor_mask32x8(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        self.combine_mask32x8(self.not_mask32x8(a0), self.not_mask32x8(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask32x16(self, a: mask32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        self.combine_mask32x8(self.reverse_mask32x8(a1), self.reverse_mask32x8(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask32x16(
        self,
        a: mask32x16<Self>,
        b: mask32x16<Self>,
        c: mask32x16<Self>,
    ) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_mask32x16(b);
        let (c0, c1) = self.split_mask32x16(c);
        self.combine_mask32x8(
            self.select_mask32x8(a0, b0, c0),
            self.select_mask32x8(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_mask32x16(b);
        self.combine_mask32x8(self.simd_eq_mask32x8(a0, b0), self.simd_eq_mask32x8(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask32x16<Self> {
        self.not_mask32x16(self.simd_eq_mask32x16(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask32x16(self, a: mask32x16<Self>) -> bool {
        let (a0, a1) = self.split_mask32x16(a);
        self.any_true_mask32x8(self.or_mask32x8(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask32x16(self, a: mask32x16<Self>) -> bool {
        let (a0, a1) = self.split_mask32x16(a);
        self.all_true_mask32x8(self.and_mask32x8(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask32x16(self, a: mask32x16<Self>) -> bool {
        let (a0, a1) = self.split_mask32x16(a);
        self.any_false_mask32x8(self.and_mask32x8(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask32x16(self, a: mask32x16<Self>) -> bool {
        let (a0, a1) = self.split_mask32x16(a);
        self.all_false_mask32x8(self.or_mask32x8(a0, a1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask32x16(self, a: mask32x16<Self>) -> (mask32x8<Self>, mask32x8<Self>);
    #[doc = "Widen each boolean lane into two masks of the same logical width, preserving its value.\n\nThe first result contains the lower lanes and the second contains the upper lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn widen_mask32x16(self, a: mask32x16<Self>) -> (mask64x8<Self>, mask64x8<Self>) {
        let (a0, a1) = self.split_mask32x16(a);
        let (a00, a01) = self.widen_mask32x8(a0);
        let (a10, a11) = self.widen_mask32x8(a1);
        (
            self.combine_mask64x4(a00, a01),
            self.combine_mask64x4(a10, a11),
        )
    }
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn narrow_mask32x16(self, a: mask32x16<Self>, b: mask32x16<Self>) -> mask16x32<Self> {
        let (a0, a1) = self.split_mask32x16(a);
        let (b0, b1) = self.split_mask32x16(b);
        self.combine_mask16x16(self.narrow_mask32x8(a0, a1), self.narrow_mask32x8(b0, b1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.abs_f64x4(a0), self.abs_f64x4(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_f64x8(self, val: f64) -> f64x8<Self> {
        let half = self.splat_f64x4(val);
        self.combine_f64x4(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.reverse_f64x4(a1), self.reverse_f64x4(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_f64x8<const SHIFT: usize>(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_f64x8<const SHIFT: usize>(
        self,
        a: f64x8<Self>,
        b: f64x8<Self>,
    ) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(
            self.slide_within_blocks_f64x4::<SHIFT>(a0, b0),
            self.slide_within_blocks_f64x4::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_f64x8(self, a: f64x8<Self>, indices: u8x64<Self>) -> f64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_f64x8(self, a: f64x8<Self>, indices: u8x64<Self>) -> f64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_f64x8(self, a: f64x8<Self>, indices: u8x64<Self>) -> f64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_f64x8(
        self,
        a: f64x8<Self>,
        b: f64x8<Self>,
        indices: u8x64<Self>,
    ) -> f64x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_f64x8(
        self,
        a: f64x8<Self>,
        b: f64x8<Self>,
        indices: u8x64<Self>,
    ) -> f64x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_f64x8(self, values: f64x8<Self>, mask: mask64x8<Self>) -> f64x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_f64x8(
        self,
        values: f64x8<Self>,
        mask: mask64x8<Self>,
        merge: f64x8<Self>,
    ) -> f64x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_f64x8(self, values: f64x8<Self>, mask: mask64x8<Self>) -> f64x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_f64x8(
        self,
        values: f64x8<Self>,
        mask: mask64x8<Self>,
        merge: f64x8<Self>,
    ) -> f64x8<Self>;
    #[doc = "Negate each element of the vector."]
    #[inline(always)]
    fn neg_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.neg_f64x4(a0), self.neg_f64x4(a1))
    }
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    #[inline(always)]
    fn sqrt_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.sqrt_f64x4(a0), self.sqrt_f64x4(a1))
    }
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    #[inline(always)]
    fn approximate_recip_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(
            self.approximate_recip_f64x4(a0),
            self.approximate_recip_f64x4(a1),
        )
    }
    #[doc = "Add two vectors element-wise."]
    #[inline(always)]
    fn add_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.add_f64x4(a0, b0), self.add_f64x4(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise."]
    #[inline(always)]
    fn sub_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.sub_f64x4(a0, b0), self.sub_f64x4(a1, b1))
    }
    #[doc = "Multiply two vectors element-wise."]
    #[inline(always)]
    fn mul_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.mul_f64x4(a0, b0), self.mul_f64x4(a1, b1))
    }
    #[doc = "Divide two vectors element-wise."]
    #[inline(always)]
    fn div_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.div_f64x4(a0, b0), self.div_f64x4(a1, b1))
    }
    #[doc = "Return a vector with the magnitude of `a` and the sign of `b` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    #[inline(always)]
    fn copysign_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.copysign_f64x4(a0, b0), self.copysign_f64x4(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_f64x8(self, a: f64x8<Self>) -> f64 {
        let (a0, a1) = self.split_f64x8(a);
        self.reduce_max_f64x4(self.max_f64x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_f64x8(self, a: f64x8<Self>) -> f64 {
        let (a0, a1) = self.split_f64x8(a);
        self.reduce_min_f64x4(self.min_f64x4(a0, a1))
    }
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_max_precise_f64x8(self, a: f64x8<Self>) -> f64 {
        let (a0, a1) = self.split_f64x8(a);
        self.reduce_max_precise_f64x4(self.max_precise_f64x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn reduce_min_precise_f64x8(self, a: f64x8<Self>) -> f64 {
        let (a0, a1) = self.split_f64x8(a);
        self.reduce_min_precise_f64x4(self.min_precise_f64x4(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_f64x8(self, a: f64x8<Self>) -> f64 {
        let (a0, a1) = self.split_f64x8(a);
        self.reduce_sum_f64x4(self.add_f64x4(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_f64x8(self, a: f64x8<Self>) -> f64 {
        let (a0, a1) = self.split_f64x8(a);
        self.reduce_product_f64x4(self.mul_f64x4(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.max_f64x4(a0, b0), self.max_f64x4(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.min_f64x4(a0, b0), self.min_f64x4(a1, b1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn max_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(
            self.max_precise_f64x4(a0, b0),
            self.max_precise_f64x4(a1, b1),
        )
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    #[inline(always)]
    fn min_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(
            self.min_precise_f64x4(a0, b0),
            self.min_precise_f64x4(a1, b1),
        )
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_f64x8(self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let (c0, c1) = self.split_f64x8(c);
        self.combine_f64x4(self.clamp_f64x4(a0, b0, c0), self.clamp_f64x4(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_mask64x4(self.simd_eq_f64x4(a0, b0), self.simd_eq_f64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> {
        self.not_mask64x8(self.simd_eq_f64x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_mask64x4(self.simd_lt_f64x4(a0, b0), self.simd_lt_f64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_mask64x4(self.simd_le_f64x4(a0, b0), self.simd_le_f64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> {
        self.simd_le_f64x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> mask64x8<Self> {
        self.simd_lt_f64x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, _) = self.split_f64x8(a);
        let (b0, _) = self.split_f64x8(b);
        self.combine_f64x4(self.zip_low_f64x4(a0, b0), self.zip_high_f64x4(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (_, a1) = self.split_f64x8(a);
        let (_, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.zip_low_f64x4(a1, b1), self.zip_high_f64x4(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.unzip_low_f64x4(a0, a1), self.unzip_low_f64x4(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f64x4(self.unzip_high_f64x4(a0, a1), self.unzip_high_f64x4(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> (f64x8<Self>, f64x8<Self>) {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let lo_lo = self.zip_low_f64x4(a0, b0);
        let lo_hi = self.zip_high_f64x4(a0, b0);
        let hi_lo = self.zip_low_f64x4(a1, b1);
        let hi_hi = self.zip_high_f64x4(a1, b1);
        (
            self.combine_f64x4(lo_lo, lo_hi),
            self.combine_f64x4(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> (f64x8<Self>, f64x8<Self>) {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let lo_even = self.unzip_low_f64x4(a0, a1);
        let lo_odd = self.unzip_high_f64x4(a0, a1);
        let hi_even = self.unzip_low_f64x4(b0, b1);
        let hi_odd = self.unzip_high_f64x4(b0, b1);
        (
            self.combine_f64x4(lo_even, hi_even),
            self.combine_f64x4(lo_odd, hi_odd),
        )
    }
    #[doc = "Compute `(a * b) + c` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_add_f64x8(self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let (c0, c1) = self.split_f64x8(c);
        self.combine_f64x4(
            self.mul_add_f64x4(a0, b0, c0),
            self.mul_add_f64x4(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) + c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_add_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let (c0, c1) = self.split_f64x8(c);
        self.combine_f64x4(
            self.mul_add_precise_f64x4(a0, b0, c0),
            self.mul_add_precise_f64x4(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    #[inline(always)]
    fn mul_sub_f64x8(self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let (c0, c1) = self.split_f64x8(c);
        self.combine_f64x4(
            self.mul_sub_f64x4(a0, b0, c0),
            self.mul_sub_f64x4(a1, b1, c1),
        )
    }
    #[doc = "Compute `(a * b) - c` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    #[inline(always)]
    fn mul_sub_precise_f64x8(self, a: f64x8<Self>, b: f64x8<Self>, c: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let (c0, c1) = self.split_f64x8(c);
        self.combine_f64x4(
            self.mul_sub_precise_f64x4(a0, b0, c0),
            self.mul_sub_precise_f64x4(a1, b1, c1),
        )
    }
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    #[inline(always)]
    fn floor_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.floor_f64x4(a0), self.floor_f64x4(a1))
    }
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    #[inline(always)]
    fn ceil_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.ceil_f64x4(a0), self.ceil_f64x4(a1))
    }
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    #[inline(always)]
    fn round_ties_even_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(
            self.round_ties_even_f64x4(a0),
            self.round_ties_even_f64x4(a1),
        )
    }
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    #[inline(always)]
    fn round_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.round_f64x4(a0), self.round_f64x4(a1))
    }
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `a - a.trunc()`."]
    #[inline(always)]
    fn fract_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.fract_f64x4(a0), self.fract_f64x4(a1))
    }
    #[doc = "Return the integer part of each element, rounding towards zero."]
    #[inline(always)]
    fn trunc_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.trunc_f64x4(a0), self.trunc_f64x4(a1))
    }
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_degrees_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.to_degrees_f64x4(a0), self.to_degrees_f64x4(a1))
    }
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    #[inline(always)]
    fn to_radians_f64x8(self, a: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_f64x4(self.to_radians_f64x4(a0), self.to_radians_f64x4(a1))
    }
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative_f64x8(self, a: f64x8<Self>) -> mask64x8<Self>;
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_f64x8(self, a: mask64x8<Self>, b: f64x8<Self>, c: f64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        let (c0, c1) = self.split_f64x8(c);
        self.combine_f64x4(self.select_f64x4(a0, b0, c0), self.select_f64x4(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_f64x8(self, a: f64x8<Self>) -> (f64x4<Self>, f64x4<Self>);
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nValues are rounded to the nearest representable `f32`, with ties resolved to even; overflow produces signed infinity.This is the same as the `as` operator, and follows the IEEE 754 narrowing behavior in round-to-even mode.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f32x8(self.narrow_f64x4(a0, a1), self.narrow_f64x4(b0, b1))
    }
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nFor floating-point vectors this is identical to `narrow`, including its rounding and overflow behavior.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f32x8(
            self.saturating_narrow_f64x4(a0, a1),
            self.saturating_narrow_f64x4(b0, b1),
        )
    }
    #[doc = "Convert the lanes of two `f64` vectors to `f32` and concatenate them into one same-width vector.\n\nFor floating-point vectors this is identical to `narrow`, including its rounding and overflow behavior.\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_f64x8(self, a: f64x8<Self>, b: f64x8<Self>) -> f32x16<Self> {
        let (a0, a1) = self.split_f64x8(a);
        let (b0, b1) = self.split_f64x8(b);
        self.combine_f32x8(
            self.relaxed_narrow_f64x4(a0, a1),
            self.relaxed_narrow_f64x4(b0, b1),
        )
    }
    #[doc = "Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    #[inline(always)]
    fn cvt_u64_f64x8(self, a: f64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_u64x4(self.cvt_u64_f64x4(a0), self.cvt_u64_f64x4(a1))
    }
    #[doc = "Convert each floating-point element to an unsigned 64-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_u64_precise_f64x8(self, a: f64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_u64x4(
            self.cvt_u64_precise_f64x4(a0),
            self.cvt_u64_precise_f64x4(a1),
        )
    }
    #[doc = "Convert each floating-point element to a signed 64-bit integer, truncating towards zero.\n\nOut-of-range values or NaN will produce implementation-defined results."]
    #[inline(always)]
    fn cvt_i64_f64x8(self, a: f64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_i64x4(self.cvt_i64_f64x4(a0), self.cvt_i64_f64x4(a1))
    }
    #[doc = "Convert each floating-point element to a signed 64-bit integer, truncating towards zero.\n\nOut-of-range values are saturated to the closest in-range value. NaN becomes 0."]
    #[inline(always)]
    fn cvt_i64_precise_f64x8(self, a: f64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_f64x8(a);
        self.combine_i64x4(
            self.cvt_i64_precise_f64x4(a0),
            self.cvt_i64_precise_f64x4(a1),
        )
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_i64x8(self, a: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.abs_i64x4(a0), self.abs_i64x4(a1))
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_i64x8(self, val: i64) -> i64x8<Self> {
        let half = self.splat_i64x4(val);
        self.combine_i64x4(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_i64x8(self, a: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.reverse_i64x4(a1), self.reverse_i64x4(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_i64x8<const SHIFT: usize>(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_i64x8<const SHIFT: usize>(
        self,
        a: i64x8<Self>,
        b: i64x8<Self>,
    ) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(
            self.slide_within_blocks_i64x4::<SHIFT>(a0, b0),
            self.slide_within_blocks_i64x4::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_i64x8(self, a: i64x8<Self>, indices: u8x64<Self>) -> i64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_i64x8(self, a: i64x8<Self>, indices: u8x64<Self>) -> i64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_i64x8(self, a: i64x8<Self>, indices: u8x64<Self>) -> i64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_i64x8(
        self,
        a: i64x8<Self>,
        b: i64x8<Self>,
        indices: u8x64<Self>,
    ) -> i64x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_i64x8(
        self,
        a: i64x8<Self>,
        b: i64x8<Self>,
        indices: u8x64<Self>,
    ) -> i64x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_i64x8(self, values: i64x8<Self>, mask: mask64x8<Self>) -> i64x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_i64x8(
        self,
        values: i64x8<Self>,
        mask: mask64x8<Self>,
        merge: i64x8<Self>,
    ) -> i64x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_i64x8(self, values: i64x8<Self>, mask: mask64x8<Self>) -> i64x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_i64x8(
        self,
        values: i64x8<Self>,
        mask: mask64x8<Self>,
        merge: i64x8<Self>,
    ) -> i64x8<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_i64x8(self, a: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.count_ones_i64x4(a0), self.count_ones_i64x4(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_i64x8(self, a: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.count_zeros_i64x4(a0), self.count_zeros_i64x4(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.add_i64x4(a0, b0), self.add_i64x4(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(
            self.saturating_add_i64x4(a0, b0),
            self.saturating_add_i64x4(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.sub_i64x4(a0, b0), self.sub_i64x4(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(
            self.saturating_sub_i64x4(a0, b0),
            self.saturating_sub_i64x4(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.mul_i64x4(a0, b0), self.mul_i64x4(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.and_i64x4(a0, b0), self.and_i64x4(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.or_i64x4(a0, b0), self.or_i64x4(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.xor_i64x4(a0, b0), self.xor_i64x4(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_i64x8(self, a: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.not_i64x4(a0), self.not_i64x4(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.shl_i64x4(a0, shift), self.shl_i64x4(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.shlv_i64x4(a0, b0), self.shlv_i64x4(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_i64x8(self, a: i64x8<Self>, shift: u32) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.shr_i64x4(a0, shift), self.shr_i64x4(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.shrv_i64x4(a0, b0), self.shrv_i64x4(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_i64x8(self, a: i64x8<Self>) -> i64 {
        let (a0, a1) = self.split_i64x8(a);
        self.reduce_max_i64x4(self.max_i64x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_i64x8(self, a: i64x8<Self>) -> i64 {
        let (a0, a1) = self.split_i64x8(a);
        self.reduce_min_i64x4(self.min_i64x4(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_i64x8(self, a: i64x8<Self>) -> i64 {
        let (a0, a1) = self.split_i64x8(a);
        self.reduce_sum_i64x4(self.add_i64x4(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_i64x8(self, a: i64x8<Self>) -> i64 {
        let (a0, a1) = self.split_i64x8(a);
        self.reduce_product_i64x4(self.mul_i64x4(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.max_i64x4(a0, b0), self.max_i64x4(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.min_i64x4(a0, b0), self.min_i64x4(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_i64x8(self, a: i64x8<Self>, b: i64x8<Self>, c: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        let (c0, c1) = self.split_i64x8(c);
        self.combine_i64x4(self.clamp_i64x4(a0, b0, c0), self.clamp_i64x4(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_mask64x4(self.simd_eq_i64x4(a0, b0), self.simd_eq_i64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> {
        self.not_mask64x8(self.simd_eq_i64x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_mask64x4(self.simd_lt_i64x4(a0, b0), self.simd_lt_i64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_mask64x4(self.simd_le_i64x4(a0, b0), self.simd_le_i64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> {
        self.simd_le_i64x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> mask64x8<Self> {
        self.simd_lt_i64x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, _) = self.split_i64x8(a);
        let (b0, _) = self.split_i64x8(b);
        self.combine_i64x4(self.zip_low_i64x4(a0, b0), self.zip_high_i64x4(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (_, a1) = self.split_i64x8(a);
        let (_, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.zip_low_i64x4(a1, b1), self.zip_high_i64x4(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.unzip_low_i64x4(a0, a1), self.unzip_low_i64x4(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i64x4(self.unzip_high_i64x4(a0, a1), self.unzip_high_i64x4(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> (i64x8<Self>, i64x8<Self>) {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        let lo_lo = self.zip_low_i64x4(a0, b0);
        let lo_hi = self.zip_high_i64x4(a0, b0);
        let hi_lo = self.zip_low_i64x4(a1, b1);
        let hi_hi = self.zip_high_i64x4(a1, b1);
        (
            self.combine_i64x4(lo_lo, lo_hi),
            self.combine_i64x4(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> (i64x8<Self>, i64x8<Self>) {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        let lo_even = self.unzip_low_i64x4(a0, a1);
        let lo_odd = self.unzip_high_i64x4(a0, a1);
        let hi_even = self.unzip_low_i64x4(b0, b1);
        let hi_odd = self.unzip_high_i64x4(b0, b1);
        (
            self.combine_i64x4(lo_even, hi_even),
            self.combine_i64x4(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_i64x8(self, a: mask64x8<Self>, b: i64x8<Self>, c: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        let (c0, c1) = self.split_i64x8(c);
        self.combine_i64x4(self.select_i64x4(a0, b0, c0), self.select_i64x4(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_i64x8(self, a: i64x8<Self>) -> (i64x4<Self>, i64x4<Self>);
    #[doc = "Negate each element of the vector, wrapping on overflow."]
    #[inline(always)]
    fn neg_i64x8(self, a: i64x8<Self>) -> i64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_i64x4(self.neg_i64x4(a0), self.neg_i64x4(a1))
    }
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i32x8(self.narrow_i64x4(a0, a1), self.narrow_i64x4(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i32x8(
            self.saturating_narrow_i64x4(a0, a1),
            self.saturating_narrow_i64x4(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_i64x8(self, a: i64x8<Self>, b: i64x8<Self>) -> i32x16<Self> {
        let (a0, a1) = self.split_i64x8(a);
        let (b0, b1) = self.split_i64x8(b);
        self.combine_i32x8(
            self.relaxed_narrow_i64x4(a0, a1),
            self.relaxed_narrow_i64x4(b0, b1),
        )
    }
    #[doc = "Convert each signed 64-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f64_i64x8(self, a: i64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_i64x8(a);
        self.combine_f64x4(self.cvt_f64_i64x4(a0), self.cvt_f64_i64x4(a1))
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    #[inline(always)]
    fn abs_u64x8(self, a: u64x8<Self>) -> u64x8<Self> {
        a
    }
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    #[inline(always)]
    fn splat_u64x8(self, val: u64) -> u64x8<Self> {
        let half = self.splat_u64x4(val);
        self.combine_u64x4(half, half)
    }
    #[doc = "Reverse the order of the vector's elements."]
    #[inline(always)]
    fn reverse_u64x8(self, a: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_u64x4(self.reverse_u64x4(a1), self.reverse_u64x4(a0))
    }
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide_u64x8<const SHIFT: usize>(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self>;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    #[inline(always)]
    fn slide_within_blocks_u64x8<const SHIFT: usize>(
        self,
        a: u64x8<Self>,
        b: u64x8<Self>,
    ) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(
            self.slide_within_blocks_u64x4::<SHIFT>(a0, b0),
            self.slide_within_blocks_u64x4::<SHIFT>(a1, b1),
        )
    }
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    #[inline(always)]
    fn swizzle_dyn_within_blocks_u64x8(self, a: u64x8<Self>, indices: u8x64<Self>) -> u64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_within_blocks_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn swizzle_dyn_u64x8(self, a: u64x8<Self>, indices: u8x64<Self>) -> u64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    #[inline(always)]
    fn swizzle_dyn_precise_u64x8(self, a: u64x8<Self>, indices: u8x64<Self>) -> u64x8<Self> {
        Bytes::from_bytes(self.swizzle_dyn_precise_u8x64(Bytes::to_bytes(a), indices))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_u64x8(
        self,
        a: u64x8<Self>,
        b: u64x8<Self>,
        indices: u8x64<Self>,
    ) -> u64x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    #[inline(always)]
    fn concat_swizzle_dyn_precise_u64x8(
        self,
        a: u64x8<Self>,
        b: u64x8<Self>,
        indices: u8x64<Self>,
    ) -> u64x8<Self> {
        Bytes::from_bytes(self.concat_swizzle_dyn_precise_u8x64(
            Bytes::to_bytes(a),
            Bytes::to_bytes(b),
            indices,
        ))
    }
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress_u64x8(self, values: u64x8<Self>, mask: mask64x8<Self>) -> u64x8<Self>;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = values[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge_u64x8(
        self,
        values: u64x8<Self>,
        mask: mask64x8<Self>,
        merge: u64x8<Self>,
    ) -> u64x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand_u64x8(self, values: u64x8<Self>, mask: mask64x8<Self>) -> u64x8<Self>;
    #[doc = "Expand consecutive low elements from `values` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = values[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge_u64x8(
        self,
        values: u64x8<Self>,
        mask: mask64x8<Self>,
        merge: u64x8<Self>,
    ) -> u64x8<Self>;
    #[doc = "Return the number of ones in the binary representation of each element."]
    #[inline(always)]
    fn count_ones_u64x8(self, a: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_u64x4(self.count_ones_u64x4(a0), self.count_ones_u64x4(a1))
    }
    #[doc = "Return the number of zeros in the binary representation of each element."]
    #[inline(always)]
    fn count_zeros_u64x8(self, a: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_u64x4(self.count_zeros_u64x4(a0), self.count_zeros_u64x4(a1))
    }
    #[doc = "Add two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.add_u64x4(a0, b0), self.add_u64x4(a1, b1))
    }
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    #[inline(always)]
    fn saturating_add_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(
            self.saturating_add_u64x4(a0, b0),
            self.saturating_add_u64x4(a1, b1),
        )
    }
    #[doc = "Subtract two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.sub_u64x4(a0, b0), self.sub_u64x4(a1, b1))
    }
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    #[inline(always)]
    fn saturating_sub_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(
            self.saturating_sub_u64x4(a0, b0),
            self.saturating_sub_u64x4(a1, b1),
        )
    }
    #[doc = "Multiply two vectors element-wise, wrapping on overflow."]
    #[inline(always)]
    fn mul_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.mul_u64x4(a0, b0), self.mul_u64x4(a1, b1))
    }
    #[doc = "Compute the bitwise AND of two vectors."]
    #[inline(always)]
    fn and_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.and_u64x4(a0, b0), self.and_u64x4(a1, b1))
    }
    #[doc = "Compute the bitwise OR of two vectors."]
    #[inline(always)]
    fn or_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.or_u64x4(a0, b0), self.or_u64x4(a1, b1))
    }
    #[doc = "Compute the bitwise XOR of two vectors."]
    #[inline(always)]
    fn xor_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.xor_u64x4(a0, b0), self.xor_u64x4(a1, b1))
    }
    #[doc = "Compute the bitwise NOT of the vector."]
    #[inline(always)]
    fn not_u64x8(self, a: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_u64x4(self.not_u64x4(a0), self.not_u64x4(a1))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shl_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_u64x4(self.shl_u64x4(a0, shift), self.shl_u64x4(a1, shift))
    }
    #[doc = "Shift each element left by the given number of bits.\n\nBits shifted out of the left side are discarded, and zeros are shifted in on the right.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shlv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.shlv_u64x4(a0, b0), self.shlv_u64x4(a1, b1))
    }
    #[doc = "Shift each element right by the given number of bits.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform."]
    #[inline(always)]
    fn shr_u64x8(self, a: u64x8<Self>, shift: u32) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_u64x4(self.shr_u64x4(a0, shift), self.shr_u64x4(a1, shift))
    }
    #[doc = "Shift each element right by the corresponding element in another vector.\n\nFor unsigned integers, zeros are shifted in on the left. For signed integers, the sign bit is replicated.\n\nWhen shifting out of bounds (e.g. shifting a 32-bit value by 32 or more), the result is implementation-defined and may vary by platform.\n\n# Performance\nThis per-lane shift is slower than shifting the entire vector by a scalar. It is not vectorized at all on WebAssembly, SSE4.2, and for `u8` and `i8` elements on AVX2. Prefer shifting by a single scalar value instead of by a vector whenever possible."]
    #[inline(always)]
    fn shrv_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.shrv_u64x4(a0, b0), self.shrv_u64x4(a1, b1))
    }
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_max_u64x8(self, a: u64x8<Self>) -> u64 {
        let (a0, a1) = self.split_u64x8(a);
        self.reduce_max_u64x4(self.max_u64x4(a0, a1))
    }
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    #[inline(always)]
    fn reduce_min_u64x8(self, a: u64x8<Self>) -> u64 {
        let (a0, a1) = self.split_u64x8(a);
        self.reduce_min_u64x4(self.min_u64x4(a0, a1))
    }
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    #[inline(always)]
    fn reduce_sum_u64x8(self, a: u64x8<Self>) -> u64 {
        let (a0, a1) = self.split_u64x8(a);
        self.reduce_sum_u64x4(self.add_u64x4(a0, a1))
    }
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    #[inline(always)]
    fn reduce_product_u64x8(self, a: u64x8<Self>) -> u64 {
        let (a0, a1) = self.split_u64x8(a);
        self.reduce_product_u64x4(self.mul_u64x4(a0, a1))
    }
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn max_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.max_u64x4(a0, b0), self.max_u64x4(a1, b1))
    }
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    #[inline(always)]
    fn min_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.min_u64x4(a0, b0), self.min_u64x4(a1, b1))
    }
    #[doc = "Clamp each element to the interval `[b, c]`.\n\nIf `b > c`, or `b` or `c` are NaN, the result is implementation-defined for that lane.\n\nIf `a` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `b > c` for any element or any element of `b` or `c` is NaN."]
    #[inline(always)]
    fn clamp_u64x8(self, a: u64x8<Self>, b: u64x8<Self>, c: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        let (c0, c1) = self.split_u64x8(c);
        self.combine_u64x4(self.clamp_u64x4(a0, b0, c0), self.clamp_u64x4(a1, b1, c1))
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_mask64x4(self.simd_eq_u64x4(a0, b0), self.simd_eq_u64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> {
        self.not_mask64x8(self.simd_eq_u64x8(a, b))
    }
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `a` is less than `b`, and false if not."]
    #[inline(always)]
    fn simd_lt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_mask64x4(self.simd_lt_u64x4(a0, b0), self.simd_lt_u64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `a` is less than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_le_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_mask64x4(self.simd_le_u64x4(a0, b0), self.simd_le_u64x4(a1, b1))
    }
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `a` is greater than or equal to `b`, and false if not."]
    #[inline(always)]
    fn simd_ge_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> {
        self.simd_le_u64x8(b, a)
    }
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `a` is greater than `b`, and false if not."]
    #[inline(always)]
    fn simd_gt_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> mask64x8<Self> {
        self.simd_lt_u64x8(b, a)
    }
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, _) = self.split_u64x8(a);
        let (b0, _) = self.split_u64x8(b);
        self.combine_u64x4(self.zip_low_u64x4(a0, b0), self.zip_high_u64x4(a0, b0))
    }
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    #[inline(always)]
    fn zip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (_, a1) = self.split_u64x8(a);
        let (_, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.zip_low_u64x4(a1, b1), self.zip_high_u64x4(a1, b1))
    }
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_low_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.unzip_low_u64x4(a0, a1), self.unzip_low_u64x4(b0, b1))
    }
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    #[inline(always)]
    fn unzip_high_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u64x4(self.unzip_high_u64x4(a0, a1), self.unzip_high_u64x4(b0, b1))
    }
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `a` and `b`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    #[inline(always)]
    fn interleave_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> (u64x8<Self>, u64x8<Self>) {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        let lo_lo = self.zip_low_u64x4(a0, b0);
        let lo_hi = self.zip_high_u64x4(a0, b0);
        let hi_lo = self.zip_low_u64x4(a1, b1);
        let hi_hi = self.zip_high_u64x4(a1, b1);
        (
            self.combine_u64x4(lo_lo, lo_hi),
            self.combine_u64x4(hi_lo, hi_hi),
        )
    }
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `a` followed by all even-indexed elements from `b`. The second result contains all odd-indexed elements from `a` followed by all odd-indexed elements from `b`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    #[inline(always)]
    fn deinterleave_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> (u64x8<Self>, u64x8<Self>) {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        let lo_even = self.unzip_low_u64x4(a0, a1);
        let lo_odd = self.unzip_high_u64x4(a0, a1);
        let hi_even = self.unzip_low_u64x4(b0, b1);
        let hi_odd = self.unzip_high_u64x4(b0, b1);
        (
            self.combine_u64x4(lo_even, hi_even),
            self.combine_u64x4(lo_odd, hi_odd),
        )
    }
    #[doc = "Select elements from b and c based on the mask operand a.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_u64x8(self, a: mask64x8<Self>, b: u64x8<Self>, c: u64x8<Self>) -> u64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        let (c0, c1) = self.split_u64x8(c);
        self.combine_u64x4(self.select_u64x4(a0, b0, c0), self.select_u64x4(a1, b1, c1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_u64x8(self, a: u64x8<Self>) -> (u64x4<Self>, u64x4<Self>);
    #[doc = "Truncate the lanes of two vectors and concatenate them into one same-width vector.\n\nEach lane retains its low destination-width bits. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u32x8(self.narrow_u64x4(a0, a1), self.narrow_u64x4(b0, b1))
    }
    #[doc = "Narrow the lanes of two vectors with saturation and concatenate them into one same-width vector.\n\nEach lane is clamped to the destination type's range. `a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn saturating_narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u32x8(
            self.saturating_narrow_u64x4(a0, a1),
            self.saturating_narrow_u64x4(b0, b1),
        )
    }
    #[doc = "Narrow the lanes of two vectors using the cheapest operation for the active SIMD backend and concatenate them into one same-width vector.\n\nInputs must fit in the destination type; in debug mode this function will panic if any of the inputs do not fit. Out-of-range results in release builds produce arbitrary values (but remain memory-safe).\n\n`a` provides the lower result lanes and `b` provides the upper result lanes."]
    #[inline(always)]
    fn relaxed_narrow_u64x8(self, a: u64x8<Self>, b: u64x8<Self>) -> u32x16<Self> {
        let (a0, a1) = self.split_u64x8(a);
        let (b0, b1) = self.split_u64x8(b);
        self.combine_u32x8(
            self.relaxed_narrow_u64x4(a0, a1),
            self.relaxed_narrow_u64x4(b0, b1),
        )
    }
    #[doc = "Convert each unsigned 64-bit integer element to a floating-point value.\n\nValues that cannot be exactly represented are rounded to the nearest representable value."]
    #[inline(always)]
    fn cvt_f64_u64x8(self, a: u64x8<Self>) -> f64x8<Self> {
        let (a0, a1) = self.split_u64x8(a);
        self.combine_f64x4(self.cvt_f64_u64x4(a0), self.cvt_f64_u64x4(a1))
    }
    #[doc = "Create a SIMD mask with all lanes set from the given boolean value."]
    #[inline(always)]
    fn splat_mask64x8(self, val: bool) -> mask64x8<Self> {
        let half = self.splat_mask64x4(val);
        self.combine_mask64x4(half, half)
    }
    #[doc = "Create a SIMD mask from a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are ignored."]
    #[inline(always)]
    fn from_bitmask_mask64x8(self, bits: u64) -> mask64x8<Self> {
        let lo = self.from_bitmask_mask64x4(bits);
        let hi = self.from_bitmask_mask64x4(bits >> 4usize);
        self.combine_mask64x4(lo, hi)
    }
    #[doc = "Convert a SIMD mask to a compact bitmask.\n\nBit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above the number of lanes in this mask are cleared."]
    #[inline(always)]
    fn to_bitmask_mask64x8(self, a: mask64x8<Self>) -> u64 {
        let (lo, hi) = self.split_mask64x8(a);
        let lo = self.to_bitmask_mask64x4(lo);
        let hi = self.to_bitmask_mask64x4(hi);
        lo | (hi << 4usize)
    }
    #[doc = "Create a SIMD mask from an integer vector of the same width.\n\nA lane value of -1 means \"true\", a lane value of 0 means \"false\", and all other lane values result in unspecified behavior."]
    fn from_vector_mask64x8(self, vector: i64x8<Self>) -> mask64x8<Self>;
    #[doc = "Convert a SIMD mask to an integer vector of the same width.\n\n\"True\" maps to -1 and \"false\" maps to 0."]
    fn to_vector_mask64x8(self, a: mask64x8<Self>) -> i64x8<Self>;
    #[doc = "Set one logical lane of a SIMD mask."]
    fn set_mask64x8(self, a: &mut mask64x8<Self>, index: usize, value: bool) -> ();
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left_mask64x8<const OFFSET: usize>(
        self,
        a: mask64x8<Self>,
    ) -> mask64x8<Self>;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right_mask64x8<const OFFSET: usize>(
        self,
        a: mask64x8<Self>,
    ) -> mask64x8<Self>;
    #[doc = "Compute the logical AND of two masks."]
    #[inline(always)]
    fn and_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_mask64x8(b);
        self.combine_mask64x4(self.and_mask64x4(a0, b0), self.and_mask64x4(a1, b1))
    }
    #[doc = "Compute the logical OR of two masks."]
    #[inline(always)]
    fn or_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_mask64x8(b);
        self.combine_mask64x4(self.or_mask64x4(a0, b0), self.or_mask64x4(a1, b1))
    }
    #[doc = "Compute the logical XOR of two masks."]
    #[inline(always)]
    fn xor_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_mask64x8(b);
        self.combine_mask64x4(self.xor_mask64x4(a0, b0), self.xor_mask64x4(a1, b1))
    }
    #[doc = "Compute the logical NOT of the mask."]
    #[inline(always)]
    fn not_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        self.combine_mask64x4(self.not_mask64x4(a0), self.not_mask64x4(a1))
    }
    #[doc = "Reverse the order of the mask's logical lanes."]
    #[inline(always)]
    fn reverse_mask64x8(self, a: mask64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        self.combine_mask64x4(self.reverse_mask64x4(a1), self.reverse_mask64x4(a0))
    }
    #[doc = "Select elements from `b` and `c` based on the mask operand `a`.\n\nThis operation's behavior is unspecified if a was constructed from signed integer lanes that are neither all-zeroes (integer value 0) nor all-ones (integer value -1). See the [`Select`] trait's documentation for more information."]
    #[inline(always)]
    fn select_mask64x8(
        self,
        a: mask64x8<Self>,
        b: mask64x8<Self>,
        c: mask64x8<Self>,
    ) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_mask64x8(b);
        let (c0, c1) = self.split_mask64x8(c);
        self.combine_mask64x4(
            self.select_mask64x4(a0, b0, c0),
            self.select_mask64x4(a1, b1, c1),
        )
    }
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    #[inline(always)]
    fn simd_eq_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_mask64x8(b);
        self.combine_mask64x4(self.simd_eq_mask64x4(a0, b0), self.simd_eq_mask64x4(a1, b1))
    }
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    #[inline(always)]
    fn simd_ne_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask64x8<Self> {
        self.not_mask64x8(self.simd_eq_mask64x8(a, b))
    }
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_true_mask64x8(self, a: mask64x8<Self>) -> bool {
        let (a0, a1) = self.split_mask64x8(a);
        self.any_true_mask64x4(self.or_mask64x4(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_true_mask64x8(self, a: mask64x8<Self>) -> bool {
        let (a0, a1) = self.split_mask64x8(a);
        self.all_true_mask64x4(self.and_mask64x4(a0, a1))
    }
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn any_false_mask64x8(self, a: mask64x8<Self>) -> bool {
        let (a0, a1) = self.split_mask64x8(a);
        self.any_false_mask64x4(self.and_mask64x4(a0, a1))
    }
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    #[inline(always)]
    fn all_false_mask64x8(self, a: mask64x8<Self>) -> bool {
        let (a0, a1) = self.split_mask64x8(a);
        self.all_false_mask64x4(self.or_mask64x4(a0, a1))
    }
    #[doc = "Split a vector into two vectors of half the width.\n\nReturns a tuple of (lower half, upper half)."]
    fn split_mask64x8(self, a: mask64x8<Self>) -> (mask64x4<Self>, mask64x4<Self>);
    #[doc = "Narrow each boolean lane of two masks and concatenate them into one mask of the same logical width, preserving each value.\n\n`a` supplies the lower result lanes and `b` supplies the upper result lanes. Masks constructed from integer lanes other than 0 or -1 have unspecified behavior."]
    #[inline(always)]
    fn narrow_mask64x8(self, a: mask64x8<Self>, b: mask64x8<Self>) -> mask32x16<Self> {
        let (a0, a1) = self.split_mask64x8(a);
        let (b0, b1) = self.split_mask64x8(b);
        self.combine_mask32x8(self.narrow_mask64x4(a0, a1), self.narrow_mask64x4(b0, b1))
    }
}
pub(crate) mod arch_types {
    use crate::transmute::SimdPod;
    #[expect(
        unnameable_types,
        reason = "The native vector types that back a `Simd` implementation are an internal implementation detail, and intentionally kept private"
    )]
    pub trait ArchTypes: Sized {
        type f32x4: Copy + Send + Sync + SimdPod;
        type i8x16: Copy + Send + Sync + SimdPod;
        type u8x16: Copy + Send + Sync + SimdPod;
        type mask8x16: Copy + Send + Sync + SimdPod;
        type i16x8: Copy + Send + Sync + SimdPod;
        type u16x8: Copy + Send + Sync + SimdPod;
        type mask16x8: Copy + Send + Sync + SimdPod;
        type i32x4: Copy + Send + Sync + SimdPod;
        type u32x4: Copy + Send + Sync + SimdPod;
        type mask32x4: Copy + Send + Sync + SimdPod;
        type f64x2: Copy + Send + Sync + SimdPod;
        type i64x2: Copy + Send + Sync + SimdPod;
        type u64x2: Copy + Send + Sync + SimdPod;
        type mask64x2: Copy + Send + Sync + SimdPod;
        type f32x8: Copy + Send + Sync + SimdPod;
        type i8x32: Copy + Send + Sync + SimdPod;
        type u8x32: Copy + Send + Sync + SimdPod;
        type mask8x32: Copy + Send + Sync + SimdPod;
        type i16x16: Copy + Send + Sync + SimdPod;
        type u16x16: Copy + Send + Sync + SimdPod;
        type mask16x16: Copy + Send + Sync + SimdPod;
        type i32x8: Copy + Send + Sync + SimdPod;
        type u32x8: Copy + Send + Sync + SimdPod;
        type mask32x8: Copy + Send + Sync + SimdPod;
        type f64x4: Copy + Send + Sync + SimdPod;
        type i64x4: Copy + Send + Sync + SimdPod;
        type u64x4: Copy + Send + Sync + SimdPod;
        type mask64x4: Copy + Send + Sync + SimdPod;
        type f32x16: Copy + Send + Sync + SimdPod;
        type i8x64: Copy + Send + Sync + SimdPod;
        type u8x64: Copy + Send + Sync + SimdPod;
        type mask8x64: Copy + Send + Sync + SimdPod;
        type i16x32: Copy + Send + Sync + SimdPod;
        type u16x32: Copy + Send + Sync + SimdPod;
        type mask16x32: Copy + Send + Sync + SimdPod;
        type i32x16: Copy + Send + Sync + SimdPod;
        type u32x16: Copy + Send + Sync + SimdPod;
        type mask32x16: Copy + Send + Sync + SimdPod;
        type f64x8: Copy + Send + Sync + SimdPod;
        type i64x8: Copy + Send + Sync + SimdPod;
        type u64x8: Copy + Send + Sync + SimdPod;
        type mask64x8: Copy + Send + Sync + SimdPod;
        #[inline(always)]
        fn mask8x16_from_array(self, val: [i8; 16usize]) -> Self::mask8x16 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask8x16_to_array(self, val: Self::mask8x16) -> [i8; 16usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask16x8_from_array(self, val: [i16; 8usize]) -> Self::mask16x8 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask16x8_to_array(self, val: Self::mask16x8) -> [i16; 8usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask32x4_from_array(self, val: [i32; 4usize]) -> Self::mask32x4 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask32x4_to_array(self, val: Self::mask32x4) -> [i32; 4usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask64x2_from_array(self, val: [i64; 2usize]) -> Self::mask64x2 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask64x2_to_array(self, val: Self::mask64x2) -> [i64; 2usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask8x32_from_array(self, val: [i8; 32usize]) -> Self::mask8x32 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask8x32_to_array(self, val: Self::mask8x32) -> [i8; 32usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask16x16_from_array(self, val: [i16; 16usize]) -> Self::mask16x16 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask16x16_to_array(self, val: Self::mask16x16) -> [i16; 16usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask32x8_from_array(self, val: [i32; 8usize]) -> Self::mask32x8 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask32x8_to_array(self, val: Self::mask32x8) -> [i32; 8usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask64x4_from_array(self, val: [i64; 4usize]) -> Self::mask64x4 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask64x4_to_array(self, val: Self::mask64x4) -> [i64; 4usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask8x64_from_array(self, val: [i8; 64usize]) -> Self::mask8x64 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask8x64_to_array(self, val: Self::mask8x64) -> [i8; 64usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask16x32_from_array(self, val: [i16; 32usize]) -> Self::mask16x32 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask16x32_to_array(self, val: Self::mask16x32) -> [i16; 32usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask32x16_from_array(self, val: [i32; 16usize]) -> Self::mask32x16 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask32x16_to_array(self, val: Self::mask32x16) -> [i32; 16usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask64x8_from_array(self, val: [i64; 8usize]) -> Self::mask64x8 {
            crate::transmute::checked_transmute_copy(&val)
        }
        #[inline(always)]
        fn mask64x8_to_array(self, val: Self::mask64x8) -> [i64; 8usize] {
            crate::transmute::checked_transmute_copy(&val)
        }
    }
}
#[doc = r" Base functionality implemented by all SIMD vectors."]
pub trait SimdBase<S: Simd>:
    ExtractToken<S = S>
    + Copy
    + Sync
    + Send
    + Debug
    + 'static
    + Seal
    + Bytes<Bytes = Self::ByteVector>
    + SimdFrom<Self::Element, S>
    + SimdFrom<Self::Array, S>
    + core::ops::Index<usize, Output = Self::Element>
    + core::ops::IndexMut<usize, Output = Self::Element>
    + core::ops::Deref<Target = Self::Array>
    + core::ops::DerefMut<Target = Self::Array>
    + core::ops::Add<Output = Self>
    + core::ops::AddAssign
    + core::ops::Add<Self::Element, Output = Self>
    + core::ops::AddAssign<Self::Element>
    + core::ops::Sub<Output = Self>
    + core::ops::SubAssign
    + core::ops::Sub<Self::Element, Output = Self>
    + core::ops::SubAssign<Self::Element>
    + core::ops::Mul<Output = Self>
    + core::ops::MulAssign
    + core::ops::Mul<Self::Element, Output = Self>
    + core::ops::MulAssign<Self::Element>
{
    #[doc = r" The type of this vector's elements."]
    type Element: SimdElement;
    #[doc = r" The same-width SIMD vector of `u8` lanes used as the byte representation."]
    #[doc = r""]
    #[doc = r" This is the same type as [`Bytes::Bytes`]."]
    #[doc = r""]
    #[doc = r" This associated type exists because expressing the `SimdBase` bound directly on"]
    #[doc = r" [`Bytes::Bytes`] creates a trait-solver cycle. The `Bytes<Bytes ="]
    #[doc = r" Self::ByteVector>` supertrait bound ensures that the two types are identical."]
    #[doc = r" Generic callers should normally use [`Bytes::Bytes`], not this associated type."]
    type ByteVector: SimdBase<S, Element = u8, ByteVector = Self::ByteVector>;
    #[doc = r" This vector type's lane count. This is useful when you're"]
    #[doc = r" working with a native-width vector (e.g. [`Simd::f32s`]) and"]
    #[doc = r" want to process data in native-width chunks."]
    const LEN: usize;
    #[doc = r" A SIMD vector mask with the same number of logical lanes."]
    #[doc = r""]
    #[doc = r" Masks intentionally do not implement [`SimdBase`]. SSE, NEON, WASM, and the"]
    #[doc = r" fallback backend currently store masks as all-zero/all-one integer vectors, but"]
    #[doc = r" AVX-512/RVV/SVE-style targets use compact predicate registers instead."]
    type Mask: SimdMask<S, Element = <Self::Element as SimdElement>::Mask> + Select<Self>;
    #[doc = r" A 128-bit SIMD vector of the same scalar type."]
    type Block: SimdBase<S, Element = Self::Element, Block = Self::Block>;
    #[doc = r" The array type that this vector type corresponds to, which will"]
    #[doc = r" always be `[Self::Element; Self::LEN]`. It has the same layout as"]
    #[doc = r" this vector type, but likely has a lower alignment."]
    type Array: Copy
        + Debug
        + IntoIterator<Item = Self::Element>
        + AsRef<[Self::Element]>
        + AsMut<[Self::Element]>
        + From<Self>;
    fn as_slice(&self) -> &[Self::Element];
    fn as_mut_slice(&mut self) -> &mut [Self::Element];
    #[doc = r" Create a SIMD vector from a slice."]
    #[doc = r""]
    #[doc = r" The slice must be exactly the size of the SIMD vector."]
    fn from_slice(simd: S, slice: &[Self::Element]) -> Self;
    #[doc = r" Store a SIMD vector into a slice."]
    #[doc = r""]
    #[doc = r" The slice must be exactly the size of the SIMD vector."]
    fn store_slice(&self, slice: &mut [Self::Element]);
    #[doc = r" Create a SIMD vector from its corresponding lane array."]
    #[inline(always)]
    fn load_array(simd: S, val: Self::Array) -> Self {
        Self::simd_from(simd, val)
    }
    #[doc = r" Create a SIMD vector from a reference to its corresponding lane array."]
    #[inline(always)]
    fn load_array_ref(simd: S, val: &Self::Array) -> Self {
        Self::load_array(simd, *val)
    }
    #[doc = r" Convert this SIMD vector to its corresponding lane array."]
    #[inline(always)]
    fn to_array(self) -> Self::Array {
        *self
    }
    #[doc = r" Project this SIMD vector reference to its corresponding lane array reference."]
    #[inline(always)]
    fn as_array(&self) -> &Self::Array {
        self
    }
    #[doc = r" Project this mutable SIMD vector reference to its corresponding mutable lane array reference."]
    #[inline(always)]
    fn as_mut_array(&mut self) -> &mut Self::Array {
        self
    }
    #[doc = r" Store this SIMD vector into its corresponding lane array."]
    #[inline(always)]
    fn store_array(self, dest: &mut Self::Array) {
        *dest = self.to_array();
    }
    #[doc = r" Create a SIMD vector from a 128-bit vector of the same scalar"]
    #[doc = r" type, repeated."]
    fn block_splat(block: Self::Block) -> Self;
    #[doc = r" Create a SIMD vector where each element is produced by"]
    #[doc = r" calling `f` with that element's lane index (from 0 to"]
    #[doc = r" [`SimdBase::LEN`] - 1)."]
    fn from_fn(simd: S, f: impl FnMut(usize) -> Self::Element) -> Self;
    #[doc = r" Rotate the vector elements to the left by `OFFSET`."]
    #[doc = r""]
    #[doc = r" If `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    #[inline(always)]
    fn rotate_elements_left<const OFFSET: usize>(self) -> Self {
        match OFFSET % Self::LEN {
            0 => self.slide::<0>(self),
            1 => self.slide::<1>(self),
            2 => self.slide::<2>(self),
            3 => self.slide::<3>(self),
            4 => self.slide::<4>(self),
            5 => self.slide::<5>(self),
            6 => self.slide::<6>(self),
            7 => self.slide::<7>(self),
            8 => self.slide::<8>(self),
            9 => self.slide::<9>(self),
            10 => self.slide::<10>(self),
            11 => self.slide::<11>(self),
            12 => self.slide::<12>(self),
            13 => self.slide::<13>(self),
            14 => self.slide::<14>(self),
            15 => self.slide::<15>(self),
            16 => self.slide::<16>(self),
            17 => self.slide::<17>(self),
            18 => self.slide::<18>(self),
            19 => self.slide::<19>(self),
            20 => self.slide::<20>(self),
            21 => self.slide::<21>(self),
            22 => self.slide::<22>(self),
            23 => self.slide::<23>(self),
            24 => self.slide::<24>(self),
            25 => self.slide::<25>(self),
            26 => self.slide::<26>(self),
            27 => self.slide::<27>(self),
            28 => self.slide::<28>(self),
            29 => self.slide::<29>(self),
            30 => self.slide::<30>(self),
            31 => self.slide::<31>(self),
            32 => self.slide::<32>(self),
            33 => self.slide::<33>(self),
            34 => self.slide::<34>(self),
            35 => self.slide::<35>(self),
            36 => self.slide::<36>(self),
            37 => self.slide::<37>(self),
            38 => self.slide::<38>(self),
            39 => self.slide::<39>(self),
            40 => self.slide::<40>(self),
            41 => self.slide::<41>(self),
            42 => self.slide::<42>(self),
            43 => self.slide::<43>(self),
            44 => self.slide::<44>(self),
            45 => self.slide::<45>(self),
            46 => self.slide::<46>(self),
            47 => self.slide::<47>(self),
            48 => self.slide::<48>(self),
            49 => self.slide::<49>(self),
            50 => self.slide::<50>(self),
            51 => self.slide::<51>(self),
            52 => self.slide::<52>(self),
            53 => self.slide::<53>(self),
            54 => self.slide::<54>(self),
            55 => self.slide::<55>(self),
            56 => self.slide::<56>(self),
            57 => self.slide::<57>(self),
            58 => self.slide::<58>(self),
            59 => self.slide::<59>(self),
            60 => self.slide::<60>(self),
            61 => self.slide::<61>(self),
            62 => self.slide::<62>(self),
            63 => self.slide::<63>(self),
            _ => unreachable!(),
        }
    }
    #[doc = r" Rotate the vector elements to the right by `OFFSET`."]
    #[doc = r""]
    #[doc = r" If `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    #[inline(always)]
    fn rotate_elements_right<const OFFSET: usize>(self) -> Self {
        match Self::LEN - OFFSET % Self::LEN {
            1 => self.slide::<1>(self),
            2 => self.slide::<2>(self),
            3 => self.slide::<3>(self),
            4 => self.slide::<4>(self),
            5 => self.slide::<5>(self),
            6 => self.slide::<6>(self),
            7 => self.slide::<7>(self),
            8 => self.slide::<8>(self),
            9 => self.slide::<9>(self),
            10 => self.slide::<10>(self),
            11 => self.slide::<11>(self),
            12 => self.slide::<12>(self),
            13 => self.slide::<13>(self),
            14 => self.slide::<14>(self),
            15 => self.slide::<15>(self),
            16 => self.slide::<16>(self),
            17 => self.slide::<17>(self),
            18 => self.slide::<18>(self),
            19 => self.slide::<19>(self),
            20 => self.slide::<20>(self),
            21 => self.slide::<21>(self),
            22 => self.slide::<22>(self),
            23 => self.slide::<23>(self),
            24 => self.slide::<24>(self),
            25 => self.slide::<25>(self),
            26 => self.slide::<26>(self),
            27 => self.slide::<27>(self),
            28 => self.slide::<28>(self),
            29 => self.slide::<29>(self),
            30 => self.slide::<30>(self),
            31 => self.slide::<31>(self),
            32 => self.slide::<32>(self),
            33 => self.slide::<33>(self),
            34 => self.slide::<34>(self),
            35 => self.slide::<35>(self),
            36 => self.slide::<36>(self),
            37 => self.slide::<37>(self),
            38 => self.slide::<38>(self),
            39 => self.slide::<39>(self),
            40 => self.slide::<40>(self),
            41 => self.slide::<41>(self),
            42 => self.slide::<42>(self),
            43 => self.slide::<43>(self),
            44 => self.slide::<44>(self),
            45 => self.slide::<45>(self),
            46 => self.slide::<46>(self),
            47 => self.slide::<47>(self),
            48 => self.slide::<48>(self),
            49 => self.slide::<49>(self),
            50 => self.slide::<50>(self),
            51 => self.slide::<51>(self),
            52 => self.slide::<52>(self),
            53 => self.slide::<53>(self),
            54 => self.slide::<54>(self),
            55 => self.slide::<55>(self),
            56 => self.slide::<56>(self),
            57 => self.slide::<57>(self),
            58 => self.slide::<58>(self),
            59 => self.slide::<59>(self),
            60 => self.slide::<60>(self),
            61 => self.slide::<61>(self),
            62 => self.slide::<62>(self),
            63 => self.slide::<63>(self),
            64 => self.slide::<64>(self),
            _ => unreachable!(),
        }
    }
    #[doc = r" Shift the vector elements to the left by `OFFSET`, filling in with `padding` from the right."]
    #[doc = r""]
    #[doc = r" If `OFFSET` is greater than or equal to `Self::LEN`, all lanes are filled with `padding`."]
    #[inline(always)]
    fn shift_elements_left<const OFFSET: usize>(self, padding: Self::Element) -> Self {
        match OFFSET.min(Self::LEN) {
            0 => self.slide::<0>(padding),
            1 => self.slide::<1>(padding),
            2 => self.slide::<2>(padding),
            3 => self.slide::<3>(padding),
            4 => self.slide::<4>(padding),
            5 => self.slide::<5>(padding),
            6 => self.slide::<6>(padding),
            7 => self.slide::<7>(padding),
            8 => self.slide::<8>(padding),
            9 => self.slide::<9>(padding),
            10 => self.slide::<10>(padding),
            11 => self.slide::<11>(padding),
            12 => self.slide::<12>(padding),
            13 => self.slide::<13>(padding),
            14 => self.slide::<14>(padding),
            15 => self.slide::<15>(padding),
            16 => self.slide::<16>(padding),
            17 => self.slide::<17>(padding),
            18 => self.slide::<18>(padding),
            19 => self.slide::<19>(padding),
            20 => self.slide::<20>(padding),
            21 => self.slide::<21>(padding),
            22 => self.slide::<22>(padding),
            23 => self.slide::<23>(padding),
            24 => self.slide::<24>(padding),
            25 => self.slide::<25>(padding),
            26 => self.slide::<26>(padding),
            27 => self.slide::<27>(padding),
            28 => self.slide::<28>(padding),
            29 => self.slide::<29>(padding),
            30 => self.slide::<30>(padding),
            31 => self.slide::<31>(padding),
            32 => self.slide::<32>(padding),
            33 => self.slide::<33>(padding),
            34 => self.slide::<34>(padding),
            35 => self.slide::<35>(padding),
            36 => self.slide::<36>(padding),
            37 => self.slide::<37>(padding),
            38 => self.slide::<38>(padding),
            39 => self.slide::<39>(padding),
            40 => self.slide::<40>(padding),
            41 => self.slide::<41>(padding),
            42 => self.slide::<42>(padding),
            43 => self.slide::<43>(padding),
            44 => self.slide::<44>(padding),
            45 => self.slide::<45>(padding),
            46 => self.slide::<46>(padding),
            47 => self.slide::<47>(padding),
            48 => self.slide::<48>(padding),
            49 => self.slide::<49>(padding),
            50 => self.slide::<50>(padding),
            51 => self.slide::<51>(padding),
            52 => self.slide::<52>(padding),
            53 => self.slide::<53>(padding),
            54 => self.slide::<54>(padding),
            55 => self.slide::<55>(padding),
            56 => self.slide::<56>(padding),
            57 => self.slide::<57>(padding),
            58 => self.slide::<58>(padding),
            59 => self.slide::<59>(padding),
            60 => self.slide::<60>(padding),
            61 => self.slide::<61>(padding),
            62 => self.slide::<62>(padding),
            63 => self.slide::<63>(padding),
            64 => self.slide::<64>(padding),
            _ => unreachable!(),
        }
    }
    #[doc = r" Shift the vector elements to the right by `OFFSET`, filling in with `padding` from the left."]
    #[doc = r""]
    #[doc = r" If `OFFSET` is greater than or equal to `Self::LEN`, all lanes are filled with `padding`."]
    #[inline(always)]
    fn shift_elements_right<const OFFSET: usize>(self, padding: Self::Element) -> Self {
        let padding = Self::splat(self.token(), padding);
        match Self::LEN.saturating_sub(OFFSET) {
            0 => padding.slide::<0>(self),
            1 => padding.slide::<1>(self),
            2 => padding.slide::<2>(self),
            3 => padding.slide::<3>(self),
            4 => padding.slide::<4>(self),
            5 => padding.slide::<5>(self),
            6 => padding.slide::<6>(self),
            7 => padding.slide::<7>(self),
            8 => padding.slide::<8>(self),
            9 => padding.slide::<9>(self),
            10 => padding.slide::<10>(self),
            11 => padding.slide::<11>(self),
            12 => padding.slide::<12>(self),
            13 => padding.slide::<13>(self),
            14 => padding.slide::<14>(self),
            15 => padding.slide::<15>(self),
            16 => padding.slide::<16>(self),
            17 => padding.slide::<17>(self),
            18 => padding.slide::<18>(self),
            19 => padding.slide::<19>(self),
            20 => padding.slide::<20>(self),
            21 => padding.slide::<21>(self),
            22 => padding.slide::<22>(self),
            23 => padding.slide::<23>(self),
            24 => padding.slide::<24>(self),
            25 => padding.slide::<25>(self),
            26 => padding.slide::<26>(self),
            27 => padding.slide::<27>(self),
            28 => padding.slide::<28>(self),
            29 => padding.slide::<29>(self),
            30 => padding.slide::<30>(self),
            31 => padding.slide::<31>(self),
            32 => padding.slide::<32>(self),
            33 => padding.slide::<33>(self),
            34 => padding.slide::<34>(self),
            35 => padding.slide::<35>(self),
            36 => padding.slide::<36>(self),
            37 => padding.slide::<37>(self),
            38 => padding.slide::<38>(self),
            39 => padding.slide::<39>(self),
            40 => padding.slide::<40>(self),
            41 => padding.slide::<41>(self),
            42 => padding.slide::<42>(self),
            43 => padding.slide::<43>(self),
            44 => padding.slide::<44>(self),
            45 => padding.slide::<45>(self),
            46 => padding.slide::<46>(self),
            47 => padding.slide::<47>(self),
            48 => padding.slide::<48>(self),
            49 => padding.slide::<49>(self),
            50 => padding.slide::<50>(self),
            51 => padding.slide::<51>(self),
            52 => padding.slide::<52>(self),
            53 => padding.slide::<53>(self),
            54 => padding.slide::<54>(self),
            55 => padding.slide::<55>(self),
            56 => padding.slide::<56>(self),
            57 => padding.slide::<57>(self),
            58 => padding.slide::<58>(self),
            59 => padding.slide::<59>(self),
            60 => padding.slide::<60>(self),
            61 => padding.slide::<61>(self),
            62 => padding.slide::<62>(self),
            63 => padding.slide::<63>(self),
            64 => padding.slide::<64>(self),
            _ => unreachable!(),
        }
    }
    #[doc = "Compute the absolute value of each element.\n\nUnsigned integers are unchanged. Signed integers use wrapping absolute value: the minimum representable value remains unchanged. This matches `i32::abs()`.\n\nFor floating-point elements, clear the sign bit, preserving all other bits. For example, negative zero becomes positive zero."]
    fn abs(self) -> Self;
    #[doc = "Create a SIMD vector with all elements set to the given value."]
    fn splat(simd: S, val: Self::Element) -> Self;
    #[doc = "Reverse the order of the vector's elements."]
    fn reverse(self) -> Self;
    #[doc = "Concatenate `[self, rhs]` and extract `Self::LEN` elements starting at index `SHIFT`.\n\n`SHIFT` must be within [0, `Self::LEN`].\n\nThis can be used to implement a \"shift items\" operation by providing all zeroes as one operand. For a left shift, the right-hand side should be all zeroes. For a right shift by `M` items, the left-hand side should be all zeroes, and the shift amount will be `Self::LEN - M`.\n\nThis can also be used to rotate items within a vector by providing the same vector as both operands.\n\n```text\n\nslide::<1>([a b c d], [e f g h]) == [b c d e]\n\n```"]
    fn slide<const SHIFT: usize>(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Like `slide`, but operates independently on each 128-bit block."]
    fn slide_within_blocks<const SHIFT: usize>(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Dynamically swizzle this vector's bytes independently within each 128-bit block.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values `0..=15` select the corresponding byte from the same 128-bit input block.\n\nOut-of-range index behavior varies by platform."]
    fn swizzle_dyn_within_blocks(self, indices: impl SimdInto<Self::Bytes, S>) -> Self;
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn swizzle_dyn(self, indices: impl SimdInto<Self::Bytes, S>) -> Self;
    #[doc = "Dynamically swizzle this vector's bytes across the whole vector.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the vector's byte length select the corresponding byte from the input vector. Out-of-range indices produce zero."]
    fn swizzle_dyn_precise(self, indices: impl SimdInto<Self::Bytes, S>) -> Self;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices safely produce implementation-defined byte values.\n\nUse [`SimdBase::concat_swizzle_dyn_precise`] if out-of-range indices must produce zero."]
    fn concat_swizzle_dyn(
        self,
        rhs: impl SimdInto<Self, S>,
        indices: impl SimdInto<Self::Bytes, S>,
    ) -> Self;
    #[doc = "Dynamically select bytes from the concatenation of this vector and `rhs`.\n\nThe `indices` operand is a same-width byte vector. For each output byte, index values within the concatenated vectors' byte length select the corresponding byte: the first vector comes first, followed by `rhs`. Out-of-range indices produce zero."]
    fn concat_swizzle_dyn_precise(
        self,
        rhs: impl SimdInto<Self, S>,
        indices: impl SimdInto<Self::Bytes, S>,
    ) -> Self;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\nThis is equivalent to [`SimdBase::compress_merge`] with a zeroed merge vector."]
    fn compress(self, mask: Self::Mask) -> Self;
    #[doc = "Compact the elements selected by `mask` into consecutive low lanes, preserving their order.\n\nLanes above the number of selected elements retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[k] = self[i];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn compress_merge(self, mask: Self::Mask, merge: impl SimdInto<Self, S>) -> Self;
    #[doc = "Expand consecutive low elements from `self` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes are zero (positive zero for floats).\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros..\n\nThis is equivalent to [`SimdBase::expand_merge`] with a zeroed merge vector."]
    fn expand(self, mask: Self::Mask) -> Self;
    #[doc = "Expand consecutive low elements from `self` into the lanes selected by `mask`, preserving their order.\n\nUnselected lanes retain the corresponding values from `merge`.\n\nElements are moved without changing their bits, including floating-point NaN payloads and signed zeros.\n\n## Pseudo code\n\n```ignore\nlet mut result = merge;\nlet mut k = 0;\nfor i in 0..LEN {\n    if mask[i] {\n        result[i] = self[k];\n        k += 1;\n    }\n}\nreturn result;\n```"]
    fn expand_merge(self, mask: Self::Mask, merge: impl SimdInto<Self, S>) -> Self;
    #[doc = "Return the maximum element in the vector. Integer vectors always return the exact maximum.\n\nFor floating-point vectors with no NaNs, this returns the true maximum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true maximum. See `reduce_max_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_max(self) -> Self::Element;
    #[doc = "Return the minimum element in the vector. Integer vectors always return the exact minimum.\n\nFor floating-point vectors with no NaNs, this returns the true minimum. If any lane is NaN, the entire result is implementation-defined: it may be NaN or a numeric lane that is not the true minimum. See `reduce_min_precise` for a version that ignores quiet NaNs.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned."]
    fn reduce_min(self) -> Self::Element;
    #[doc = "Return the maximum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_max`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true maximum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true maximum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn reduce_max_precise(self) -> Self::Element;
    #[doc = "Return the minimum element in the vector, ignoring quiet NaNs.\n\nFor integer vectors, this operation is the same as `reduce_min`.\n\nFor floating-point vectors, quiet NaNs are ignored. If there is at least one numeric lane, this returns the true minimum of the numeric lanes. If all lanes are quiet NaNs, this returns NaN, with an unspecified payload and sign.\n\nIf the floating-point vector contains both positive zero and negative zero, either sign of zero may be returned.\n\nIf any lane is a *signaling* NaN, the result is fully non-deterministic: it may be NaN or a numeric lane and is not guaranteed to be the true minimum.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn reduce_min_precise(self) -> Self::Element;
    #[doc = "Return the sum of all elements in the vector. Integer addition wraps.\n\n# Floating-point accuracy\n\nFor an input vector with N lanes, any lane's contribution may be rounded at most `log2(N)` times.\n\nFor a fixed vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nBecause floating-point addition is not associative, separately reducing smaller vectors and then adding their results can differ from reducing their combined wider vector. See [Taming Floating-Point Sums](https://orlp.net/blog/taming-float-sums/) for more information and for other summation algorithms, including exact summation without accumulated rounding error. In that article's terms, our method has the precision properties of pairwise summation, although the exact pairing of values is different."]
    fn reduce_sum(self) -> Self::Element;
    #[doc = "Return the product of all elements in the vector. Integer multiplication wraps.\n\n# Floating-point behavior\n\nFor a vector with N elements, this operation performs N-1 roundings.\n\nFor a given vector type and lane count, this operation produces the same result on all platforms and backends down to the bit pattern, except that when the result is NaN, its exact bit pattern is unspecified. This fixed-width guarantee does not make code using native-width associated types such as `S::f32s` independent of the selected SIMD level, because their lane counts can differ.\n\nThe result of this operation is **not** bit-exact to scalar product of the elements because it multiplies elements in a different (but fixed) order.\n\nIntermediate operations can overflow, underflow, or multiply infinity by zero to produce NaN even when the exact real-number product is representable.\n\nBecause floating-point multiplication is not associative, separately reducing smaller vectors and then multiplying their results can differ from reducing their combined wider vector."]
    fn reduce_product(self) -> Self::Element;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `max_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn max(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor floating-point vectors, if either operand is NaN, the result for that lane is implementation-defined-- it could be either the first or second operand. See `min_precise` for a version that returns the non-NaN operand if only one is NaN.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is also implementation-defined, and it could be either one."]
    fn min(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Return the element-wise maximum of two vectors.\n\nFor integer vectors, this operation is the same as `max`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn max_precise(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Return the element-wise minimum of two vectors.\n\nFor integer vectors, this operation is the same as `min`.\n\nFor floating-point vectors, if one operand is a quiet NaN and the other is not, this operation will choose the non-NaN operand.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\nIf a floating-point operand is a *signaling* NaN, the result is not just implementation-defined, but fully non-deterministic: it may be either NaN or the non-NaN operand.\nSignaling NaN values are not produced by floating-point math operations, only from manual initialization with specific bit patterns. You probably don't need to worry about them."]
    fn min_precise(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Clamp each element to the interval `[min, max]`.\n\nIf `min > max`, or `min` or `max` are NaN, the result is implementation-defined for that lane.\n\nIf `self` is NaN, the result is an implementation-defined non-deterministic NaN value. I.e. the result of the lane will be a NaN value but its exact bit pattern is not specified.\n\nIf one floating-point operand is positive zero and the other is negative zero, the result is implementation-defined, and it could be either one.\n\n# Panics\nPanics with debug assertions if `min > max` for any element or any element of `min` or `max` is NaN."]
    fn clamp(self, min: impl SimdInto<Self, S>, max: impl SimdInto<Self, S>) -> Self;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq(self, rhs: impl SimdInto<Self, S>) -> Self::Mask;
    #[doc = "Compare two vectors element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nFor floating-point vectors, this follows Rust's `!=` semantics: a lane is true if either operand is NaN, including when both are NaN. Positive and negative zero compare equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    fn simd_ne(self, rhs: impl SimdInto<Self, S>) -> Self::Mask;
    #[doc = "Compare two vectors element-wise for less than.\n\nReturns a mask where each logical lane is true if `self` is less than `rhs`, and false if not."]
    fn simd_lt(self, rhs: impl SimdInto<Self, S>) -> Self::Mask;
    #[doc = "Compare two vectors element-wise for less than or equal.\n\nReturns a mask where each logical lane is true if `self` is less than or equal to `rhs`, and false if not."]
    fn simd_le(self, rhs: impl SimdInto<Self, S>) -> Self::Mask;
    #[doc = "Compare two vectors element-wise for greater than or equal.\n\nReturns a mask where each logical lane is true if `self` is greater than or equal to `rhs`, and false if not."]
    fn simd_ge(self, rhs: impl SimdInto<Self, S>) -> Self::Mask;
    #[doc = "Compare two vectors element-wise for greater than.\n\nReturns a mask where each logical lane is true if `self` is greater than `rhs`, and false if not."]
    fn simd_gt(self, rhs: impl SimdInto<Self, S>) -> Self::Mask;
    #[doc = "Interleave the lower half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, b0, a1, b1]`.\n\n**Note:** This operation is only useful if you need to discard elements `a2, a3, b2, b3`.\n        For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_low(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Interleave the upper half elements of two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a2, b2, a3, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a1, b0, b1`.For fully interleaving two vectors prefer `interleave`,\n        which is faster than `zip_low` followed by `zip_high` on some platforms."]
    fn zip_high(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Extract even-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a0, a2, b0, b2]`.\n\n**Note:** This operation is only useful if you need to discard elements `a1, a3, b1, b3`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_low(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Extract odd-indexed elements from two vectors.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `[a1, a3, b1, b3]`.\n\n**Note:** This operation is only useful if you need to discard elements `a0, a2, b0, b2`.For fully deinterleaving two vectors prefer `deinterleave`,\n        which is faster than `unzip_low` followed by `unzip_high` on some platforms."]
    fn unzip_high(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Interleave two vectors.\n\nThe resulting vectors contain elements taken alternately from `self` and `rhs`, first filling the first result, and then the second.\n\nThe reverse of this operation is `deinterleave`.\n\nFor vectors `[a0, a1, a2, a3]` and `[b0, b1, b2, b3]`, returns `([a0, b0, a1, b1], [a2, b2, a3, b3])`."]
    fn interleave(self, rhs: impl SimdInto<Self, S>) -> (Self, Self);
    #[doc = "Deinterleave two vectors.\n\nThe first result contains all even-indexed elements from `self` followed by all even-indexed elements from `rhs`. The second result contains all odd-indexed elements from `self` followed by all odd-indexed elements from `rhs`.\n\nThe reverse of this operation is `interleave`.\n\nFor vectors `[a0, b0, a1, b1]` and `[a2, b2, a3, b3]`, returns `([a0, a1, a2, a3], [b0, b1, b2, b3])`."]
    fn deinterleave(self, rhs: impl SimdInto<Self, S>) -> (Self, Self);
}
#[doc = r" Functionality implemented by floating-point SIMD vectors."]
pub trait SimdFloat<S: Simd>:
    SimdBase<S, Element: SimdFloatElement>
    + Seal
    + core::ops::Neg<Output = Self>
    + core::ops::Div<Output = Self>
    + core::ops::DivAssign
    + core::ops::Div<Self::Element, Output = Self>
    + core::ops::DivAssign<Self::Element>
{
    #[doc = r" Bit representation of this SIMD float vector type."]
    type Bits: SimdInt<
            S,
            Element = <Self::Element as SimdFloatElement>::Bits,
            ByteVector = Self::ByteVector,
        >;
    #[doc = r" Raw transmutation to an unsigned integer vector type with the same size and number of elements."]
    #[doc = r""]
    #[doc = r" This is analogous to [`f32::to_bits`] and [`f64::to_bits`]."]
    fn to_bits(self) -> Self::Bits {
        self.bitcast()
    }
    #[doc = r" Raw transmutation from an unsigned integer vector type with the same size and number of elements."]
    #[doc = r""]
    #[doc = r" This is analogous to [`f32::from_bits`] and [`f64::from_bits`]."]
    fn from_bits(bits: Self::Bits) -> Self {
        bits.bitcast()
    }
    #[doc = r" Convert this floating-point type to an integer. This is a convenience method that"]
    #[doc = r" delegates to [`SimdCvtTruncate::truncate_from`], and can only be called if there"]
    #[doc = r" actually exists a target type of the same bit width (`u32`/`i32` for `f32`, or"]
    #[doc = r" `u64`/`i64` for `f64`)."]
    #[doc = r""]
    #[doc = r" For more information about the semantics of this specific conversion, see the"]
    #[doc = r" concrete `SimdCvtTruncate` implementations for integer types."]
    #[inline(always)]
    fn to_int<T: SimdCvtTruncate<Self>>(self) -> T {
        T::truncate_from(self)
    }
    #[doc = r" Convert this floating-point type to an integer, saturating on overflow and returning"]
    #[doc = r" 0 for NaN. This is a convenience method that delegates to"]
    #[doc = r" [`SimdCvtTruncate::truncate_from_precise`], and can only be called if there actually"]
    #[doc = r" exists a target type of the same bit width (`u32`/`i32` for `f32`, or `u64`/`i64`"]
    #[doc = r" for `f64`)."]
    #[doc = r""]
    #[doc = r" For more information about the semantics of this specific conversion, see the"]
    #[doc = r" concrete `SimdCvtTruncate` implementations for integer types."]
    #[inline(always)]
    fn to_int_precise<T: SimdCvtTruncate<Self>>(self) -> T {
        T::truncate_from_precise(self)
    }
    #[doc = "Compute the square root of each element.\n\nNegative elements other than `-0.0` will become NaN."]
    fn sqrt(self) -> Self;
    #[doc = "Compute an approximate reciprocal (`1. / x`) for each element.\n\nThis uses a fast hardware estimate where available, and falls back to exact division otherwise.\n\nOn x86 for `f32`, this has a relative error less than `1.5 × 2^-12`. On `AArch64` (`f32` and `f64`), this has a relative error less than `2^-8`. The precision of this operation may change as new platform support is added."]
    fn approximate_recip(self) -> Self;
    #[doc = "Return a vector with the magnitude of `self` and the sign of `rhs` for each element.\n\nThis operation copies the sign bit, so if an input element is NaN, the output element will be a NaN with the same payload and a copied sign bit."]
    fn copysign(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Compute `(self * op1) + op2` (fused multiply-add) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by an add, which will result in two rounding errors."]
    fn mul_add(self, op1: impl SimdInto<Self, S>, op2: impl SimdInto<Self, S>) -> Self;
    #[doc = "Compute `(self * op1) + op2` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-plus-add rounded once to the element type. This may be substantially slower than `mul_add` on platforms without fused multiply-add instructions, including WebAssembly.\n\n# Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    fn mul_add_precise(self, op1: impl SimdInto<Self, S>, op2: impl SimdInto<Self, S>) -> Self;
    #[doc = "Compute `(self * op1) - op2` (fused multiply-subtract) for each element.\n\nDepending on platform support, the result may be computed with only one rounding error, or may be implemented as a regular multiply followed by a subtract, which will result in two rounding errors."]
    fn mul_sub(self, op1: impl SimdInto<Self, S>, op2: impl SimdInto<Self, S>) -> Self;
    #[doc = "Compute `(self * op1) - op2` for each element, with a single rounding at the end.\n\nThe result is the infinite-precision product-minus-subtrahend rounded once to the element type. This may be substantially slower than `mul_sub` on platforms without fused multiply-add instructions, including WebAssembly.\n        # Precision guarantees\n\nThis function is **not** susceptible to [the bug](https://github.com/rust-lang/compiler-builtins/issues/1262) in Rust standard library and in musl libc that causes incorrect rounding for near-zero values on CPUs without hardware support for this operation.\n\nOn the tier-2 i586-* targets, this function is correct if and only if SSE2 is available on the CPU.\n\nThe exact `NaN` payloads as well as signaling `NaN`s are not preserved."]
    fn mul_sub_precise(self, op1: impl SimdInto<Self, S>, op2: impl SimdInto<Self, S>) -> Self;
    #[doc = "Return the largest integer less than or equal to each element, that is, round towards negative infinity."]
    fn floor(self) -> Self;
    #[doc = "Return the smallest integer greater than or equal to each element, that is, round towards positive infinity."]
    fn ceil(self) -> Self;
    #[doc = "Round each element to the nearest integer, with ties rounding to the nearest even integer."]
    fn round_ties_even(self) -> Self;
    #[doc = "Round each element to the nearest integer, with ties rounding away from zero.\n\n## Performance considerations\n\nOnly `AArch64` has native instructions for this operation. `round` has to be emulated on all other platforms which is around 2-4x slower than `round_ties_even`. Prefer using [`round_ties_even`](SimdFloat::round_ties_even) if possible."]
    fn round(self) -> Self;
    #[doc = "Return the fractional part of each element.\n\nThis is equivalent to `self - self.trunc()`."]
    fn fract(self) -> Self;
    #[doc = "Return the integer part of each element, rounding towards zero."]
    fn trunc(self) -> Self;
    #[doc = "Converts radians to degrees.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    fn to_degrees(self) -> Self;
    #[doc = "Converts degrees to radians.\n\nThe precision of this function is non-deterministic. This means it varies by platform, Rust version, and can even differ within the same execution from one invocation to the next."]
    fn to_radians(self) -> Self;
    #[doc = "Return a mask indicating which elements are NaN."]
    fn is_nan(self) -> Self::Mask;
    #[doc = "Return a mask indicating which elements are positive or negative infinite."]
    fn is_infinite(self) -> Self::Mask;
    #[doc = "Return a mask indicating which elements are neither infinite nor NaN."]
    fn is_finite(self) -> Self::Mask;
    #[doc = "Return a mask indicating which elements are subnormal.\n\nThis classifies the stored bit pattern, even when floating-point operations treat subnormals as zero."]
    fn is_subnormal(self) -> Self::Mask;
    #[doc = "Return a mask indicating which elements are neither zero, infinite, subnormal, or NaN."]
    fn is_normal(self) -> Self::Mask;
    #[doc = "Return a mask indicating which elements have a positive sign, including `+0.0`, NaNs with positive sign bit and positive infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_positive`] for details."]
    fn is_sign_positive(self) -> Self::Mask;
    #[doc = "Return a mask indicating which elements have a negative sign, including `-0.0`, NaNs with negative sign bit and negative infinity.\n\nNaN inputs may produce an unexpected or non-portable result, see [`f32::is_sign_negative`] for details."]
    fn is_sign_negative(self) -> Self::Mask;
}
#[doc = r" Functionality implemented by (signed and unsigned) integer SIMD vectors."]
pub trait SimdInt<S: Simd>:
    SimdBase<S, Element: SimdIntElement>
    + Seal
    + core::ops::BitAnd<Output = Self>
    + core::ops::BitAndAssign
    + core::ops::BitAnd<Self::Element, Output = Self>
    + core::ops::BitAndAssign<Self::Element>
    + core::ops::BitOr<Output = Self>
    + core::ops::BitOrAssign
    + core::ops::BitOr<Self::Element, Output = Self>
    + core::ops::BitOrAssign<Self::Element>
    + core::ops::BitXor<Output = Self>
    + core::ops::BitXorAssign
    + core::ops::BitXor<Self::Element, Output = Self>
    + core::ops::BitXorAssign<Self::Element>
    + core::ops::Not<Output = Self>
    + core::ops::Shl<u32, Output = Self>
    + core::ops::ShlAssign<u32>
    + core::ops::Shl<Output = Self>
    + core::ops::ShlAssign
    + core::ops::Shr<u32, Output = Self>
    + core::ops::ShrAssign<u32>
    + core::ops::Shr<Output = Self>
    + core::ops::ShrAssign
{
    #[doc = r" Convert this integer type to a floating-point type. This is a convenience method"]
    #[doc = r" that delegates to [`SimdCvtFloat::float_from`], and can only be called if there"]
    #[doc = r" actually exists a target type of the same bit width (`f32` or `f64`)."]
    #[inline(always)]
    fn to_float<T: SimdCvtFloat<Self>>(self) -> T {
        T::float_from(self)
    }
    #[doc = "Return the number of ones in the binary representation of each element."]
    fn count_ones(self) -> Self;
    #[doc = "Return the number of zeros in the binary representation of each element."]
    fn count_zeros(self) -> Self;
    #[doc = "Add two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping addition on x86."]
    fn saturating_add(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Subtract two vectors element-wise, saturating on overflow.\n\n\"Saturating\" means that if the result is not representable, the closest representable value (either `Element::MAX` or `Element::MIN`) is returned.\n\nOn x86 it is implemented in hardware only for 8-bit and 16-bit elements. For 32-bit and 64-bit vectors this operation is slower than wrapping subtraction on x86."]
    fn saturating_sub(self, rhs: impl SimdInto<Self, S>) -> Self;
}
#[doc = r" Functionality implemented by SIMD masks."]
#[doc = r""]
#[doc = r" A mask has one logical boolean lane per SIMD lane. Its storage is intentionally opaque:"]
#[doc = r" current backends may use all-zero/all-one integer vectors internally, while future"]
#[doc = r" predicate-register backends may use a compact representation."]
pub trait SimdMask<S: Simd>:
    ExtractToken<S = S>
    + Copy
    + Sync
    + Send
    + 'static
    + Seal
    + Select<Self>
    + core::ops::BitAnd<Output = Self>
    + core::ops::BitAndAssign
    + core::ops::BitOr<Output = Self>
    + core::ops::BitOrAssign
    + core::ops::BitXor<Output = Self>
    + core::ops::BitXorAssign
    + core::ops::Not<Output = Self>
{
    #[doc = r" The signed integer type used when converting this mask to and from lane values."]
    #[doc = r""]
    #[doc = r" False lanes are encoded as all zeroes (integer value 0), and true lanes are encoded as all ones"]
    #[doc = r" (integer value -1)."]
    type Element: SimdIntElement<Mask = Self::Element> + core::ops::Neg<Output = Self::Element>;
    #[doc = r" This mask's corresponding integer vector type."]
    type Ints: SimdInt<S, Element = Self::Element, Mask = Self>
        + core::ops::Neg<Output = Self::Ints>;
    #[doc = r" This mask type's lane count."]
    const LEN: usize;
    #[doc = r" Create a SIMD mask with all lanes set to the given boolean value."]
    fn splat(simd: S, val: bool) -> Self;
    #[doc = r" Create a mask from a compact bitmask."]
    #[doc = r""]
    #[doc = r" Bit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above"]
    #[doc = r" [`Self::LEN`] are ignored."]
    fn from_bitmask(simd: S, bits: u64) -> Self;
    #[doc = r" Convert this mask to a compact bitmask."]
    #[doc = r""]
    #[doc = r" Bit `i` maps to lane `i`, with lane 0 in the least significant bit. Bits above"]
    #[doc = r" [`Self::LEN`] are cleared."]
    fn to_bitmask(self) -> u64;
    #[doc = r" Create a SIMD mask from signed integer mask lanes."]
    fn from_vector(v: Self::Ints) -> Self;
    #[doc = r" Convert this SIMD mask to signed integer mask lanes."]
    fn to_vector(self) -> Self::Ints;
    #[doc = r" Test whether one logical lane is set."]
    #[doc = r""]
    #[doc = r" Panics if `index` is greater than or equal to the number of lanes in the mask."]
    #[inline(always)]
    fn test(&self, index: usize) -> bool {
        assert!(
            index < Self::LEN,
            "mask lane index {index} is out of bounds for {} lanes",
            Self::LEN
        );
        (((*self).to_bitmask() >> index) & 1) != 0
    }
    #[doc = r" Sets the value of one logical lane."]
    #[doc = r""]
    #[doc = r" Panics if `index` is greater than or equal to the number of lanes in the mask."]
    fn set(&mut self, index: usize, value: bool);
    #[doc = r" Create a SIMD mask from signed integer mask lanes."]
    #[doc = r""]
    #[doc = r" The slice must be exactly the size of the SIMD mask."]
    fn from_slice(simd: S, slice: &[Self::Element]) -> Self;
    #[doc = r" Store this SIMD mask as signed integer mask lanes."]
    #[doc = r""]
    #[doc = r" The slice must be exactly the size of the SIMD mask."]
    fn store_slice(&self, slice: &mut [Self::Element]);
    #[doc = "Rotate the mask elements to the left by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_left<const OFFSET: usize>(self) -> Self;
    #[doc = "Rotate the mask elements to the right by `OFFSET`.\n\nIf `OFFSET` is greater than or equal to `Self::LEN`, it wraps modulo `Self::LEN`."]
    fn rotate_elements_right<const OFFSET: usize>(self) -> Self;
    #[doc = "Reverse the order of the mask's logical lanes."]
    fn reverse(self) -> Self;
    #[doc = "Compare two vectors element-wise for equality.\n\nReturns a mask where each logical lane is true if the corresponding elements are equal, and false if not."]
    fn simd_eq(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Compare two masks element-wise for inequality.\n\nReturns a mask where each logical lane is true if the corresponding elements are unequal, and false if equal.\n\nThis is equivalent to negating the mask returned by `simd_eq`."]
    fn simd_ne(self, rhs: impl SimdInto<Self, S>) -> Self;
    #[doc = "Returns true if any logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_true(self) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are true.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_true(self) -> bool;
    #[doc = "Returns true if any logical lanes in this mask are false.\n\nThis is logically equivalent to `!all_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn any_false(self) -> bool;
    #[doc = "Returns true if all logical lanes in this mask are false.\n\nThis is logically equivalent to `!any_true`, but may be faster.\n\nMasks may be converted to and from signed integer lane arrays for compatibility with older APIs. For those conversions, false is encoded as all zeroes (integer value 0) and true is encoded as all ones (integer value -1).\n\nBehavior on masks constructed from any other integer bit pattern is unspecified. It may vary depending on architecture, feature level, the mask elements' width, the mask vector's width, or library version.\n\nThe behavior is also not guaranteed to be logically consistent for such non-canonical masks. `any_true` may not return the same result as `!all_false`, and `all_true` may not return the same result as `!any_false`.\n\nThe [`select`](crate::Select::select) operation also has unspecified behavior for non-canonical masks. That behavior may not match the behavior of this operation."]
    fn all_false(self) -> bool;
}