#[repr(u64)]pub enum PmuEvent {
Show 29 variants
NoEvent = 0,
Cycles = 1,
RetiredInst0 = 2,
RetiredInst1 = 3,
Branches0 = 4,
Branches1 = 5,
DcacheAccess0 = 6,
DcacheAccess1 = 7,
DcacheMisses0 = 8,
DcacheMisses1 = 9,
L2MissReq = 10,
L2MissReqRej = 11,
L2EvictReq = 12,
L2EvictReqRej = 13,
TlInst = 14,
TlOps = 15,
TsInst = 16,
TsOps = 17,
TfmaWaitTenb = 18,
TimaOps = 19,
TxFma3216Ops = 20,
TxFma32Ops = 21,
TxFmaIntOps = 22,
TransOps = 23,
ShortOps = 24,
MaskOps = 25,
TfmaInst = 26,
TreduceInst = 27,
TquantInst = 28,
}Expand description
Minion-level PMU event codes (PRM section 1.3.2, Table 1-3).
Written to mhpmeventN (CSR 0x320 + N, for N in 3..=6) to select what
hpmcounterN accumulates. Firmware or a privileged shim configures the
mapping; U-mode code reads counts via pmu_read and typically cannot
write mhpmeventN without M-mode delegation.
These events apply only to hpmcounter3-hpmcounter6. For
neighbourhood-level events on hpmcounter7-hpmcounter8, use
NeighborhoodEvent.
Variants§
NoEvent = 0
No event; counter does not increment.
Cycles = 1
Clock cycles executed by the core.
Use this event in mhpmevent3-mhpmevent6 to count cycles;
mcycle (CSR 0xC00) is permanently zero on this implementation.
RetiredInst0 = 2
An instruction retired by thread 0 of the core.
minstret (CSR 0xC02) is permanently zero; use this event instead.
RetiredInst1 = 3
An instruction retired by thread 1 of the core.
minstret (CSR 0xC02) is permanently zero; use this event instead.
Branches0 = 4
A branch taken by thread 0 of the core.
Branches1 = 5
A branch taken by thread 1 of the core.
DcacheAccess0 = 6
A load/store by thread 0 accessed the data cache (hit or miss).
Excludes tensor and cache-management operations.
DcacheAccess1 = 7
A load/store by thread 1 accessed the data cache (hit or miss).
Excludes tensor and cache-management operations.
DcacheMisses0 = 8
A load/store by thread 0 missed in the data cache.
Excludes tensor and cache-management operations.
DcacheMisses1 = 9
A load/store by thread 1 missed in the data cache.
Excludes tensor and cache-management operations.
L2MissReq = 10
The data cache sent a miss request to the L2 cache.
L2MissReqRej = 11
The L2 cache rejected a miss request from the data cache.
L2EvictReq = 12
The data cache sent an evict request to the L2 cache.
L2EvictReqRej = 13
The L2 cache rejected an evict request from the data cache.
TlInst = 14
Started execution of a TensorLoad instruction.
TlOps = 15
A TensorLoad sent a request to the L2 cache.
TsInst = 16
Started execution of a TensorStore instruction.
TsOps = 17
A TensorStore sent a request to the L2 cache.
TfmaWaitTenb = 18
Cycles a TensorFMA paired with TensorLoadB was blocked waiting for data from L2. Measures the B-load serialisation cost; high values indicate that the crossbar or DRAM is the bottleneck for B tiles.
TimaOps = 19
Started execution of a micro-op generated by a TensorIMA8A32 instruction.
TxFma3216Ops = 20
Retired a micro-op generated by a TensorFMA16A32 instruction.
TxFma32Ops = 21
Retired an FP instruction (packed or scalar), integer multiplication, or a micro-op from TensorFMA32.
TxFmaIntOps = 22
Retired a packed integer instruction, int-to-FP conversion, or micro-op from integer TensorQuant.
TransOps = 23
Retired a micro-op generated by a transcendental instruction.
ShortOps = 24
Retired a packed integer instruction or a micro-op from TensorFMA32.
MaskOps = 25
Retired a mask instruction.
TfmaInst = 26
Started execution of a TensorFMA instruction.
TreduceInst = 27
Started execution of a tensor reduction instruction.
TquantInst = 28
Started execution of a TensorQuant instruction.