pub struct R(_);
Expand description

Register I2S_TX_CLKM_CONF reader

Implementations

Bits 0:7 - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div]

  • y * n-div. For b > a/2, z * [n-div + x * (n+1)-div]
  • y * (n+1)-div.

Bit 26 - I2S Tx module clock enable signal.

Bits 27:28 - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.

Bit 29 - Set this bit to enable clk gate

Methods from Deref<Target = R<I2S_TX_CLKM_CONF_SPEC>>

Reads raw bits from register.

Trait Implementations

The resulting type after dereferencing.

Dereferences the value.

Converts to this type from the input type.

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The type returned in the event of a conversion error.

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Performs the conversion.