Module esp32s3::i2s1::i2s_tx_clkm_conf

I2S TX clock configure register

Structs

I2S_CLK_EN_R

Field I2S_CLK_EN reader - Set this bit to enable clk gate

I2S_CLK_EN_W

Field I2S_CLK_EN writer - Set this bit to enable clk gate

I2S_TX_CLKM_CONF_SPEC

I2S TX clock configure register

I2S_TX_CLKM_DIV_NUM_R

Field I2S_TX_CLKM_DIV_NUM reader - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div]

I2S_TX_CLKM_DIV_NUM_W

Field I2S_TX_CLKM_DIV_NUM writer - Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div]

I2S_TX_CLK_ACTIVE_R

Field I2S_TX_CLK_ACTIVE reader - I2S Tx module clock enable signal.

I2S_TX_CLK_ACTIVE_W

Field I2S_TX_CLK_ACTIVE writer - I2S Tx module clock enable signal.

I2S_TX_CLK_SEL_R

Field I2S_TX_CLK_SEL reader - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.

I2S_TX_CLK_SEL_W

Field I2S_TX_CLK_SEL writer - Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.

R

Register I2S_TX_CLKM_CONF reader

W

Register I2S_TX_CLKM_CONF writer